* mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
add a comma) so that it more closely match the MIPS ISA
documentation opcode partitioning.
(PREF): Put useful names on opcode fields, and include
instruction-printing string.
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
* mips.igen (do_load_left, do_load_right): Move to be immediately
following do_load.
(do_store_left, do_store_right): Move to be immediately following
do_store.
* mips.igen: Add some additional comments about supported
models, and about which instructions go where.
(BC1b, MFC0, MTC0, RFE): Sort supported models in the same
order as is used in the rest of the file.
* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
indicating that ALU32_END or ALU64_END are there to check
for overflow.
(DADD): Likewise, but also remove previous comment about
overflow checking.
* mips.igen (ADDI): Print immediate value.
(BREAK): Print code.
(DADDIU, DSRAV, DSRLV): Print correct instruction name.
(SLL): Print "nop" specially, and don't run the code
that does the shift for the "nop" case.
PENDING_FILL. Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
2000-10-19 Frank Ch. Eigler <fche@redhat.com>
On advice from Chris G. Demetriou <cgd@sibyte.com>:
* sim-main.h (GPR_CLEAR): Remove unused alternative macro.
* merge from internal repo -> sourceware
2000-03-02 Frank Ch. Eigler <fche@redhat.com>
* configure: Regenerated.
Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
* interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
calls, conditional on the simulator being in verbose mode.
1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
CPU, start periodic background I/O polls.
(tx3904sio_poll): New function: periodic I/O poller.
[ChangeLog]
1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
* mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
start-sanitize-sky
* interp.c (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook.
Call sim_engine_halt on BreakPoint.
end-sanitize-sky
[ChangeLog.sky]
1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
* sky-gdb.c (sky_sim_engine_halt): Do not set CIA here.
1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
(load_word): Call SIM_CORE_SIGNAL hook on error.
(signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
starting. For exception dispatching, pass PC instead of NULL_CIA.
(decode_coproc): Use COP0_BADVADDR to store faulting address.
* sim-main.h (COP0_BADVADDR): Define.
(SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
(SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
(_sim_cpu): Add exc_* fields to store register value snapshots.
* mips.igen (*): Replace memory-related SignalException* calls
with references to SIM_CORE_SIGNAL hook.
* dv-tx3904irc.c (tx3904irc_port_event): printf format warning
fix.
* sim-main.c (*): Minor warning cleanups.
Set mips_fpu, and mips_fpu_bitsize.
Set sim_gen, and sim_igen_machine.
* configure: Rebuild.
* mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
* sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
(tx3904sio_tickle): fflush after a stdout character output.
v850/simops.c, d10v/simops.c, v850/Makefile.in, d10v/Makefile.in:
Include targ-vals.h instead of syscall.h. Replace SYS_* with
TARGET_SYS_*. Add dependency.
z8k/support.c: Include <errno.h>
v850/simops.c: Replace long with portable signed32.
mips/interp.c: Make sim_monitor global - needed by sky.
Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
* r5900.igen (mtsab): Correct typo in input register.
* sim-main.h (TMP_*): New macros for accessing local 128-bit
temporary for multimedia instructions.
* r5900.igen (*): Convert most instructions to use new TMP
macros to store output result during computation.
Hack sanitize so that it doesn't sanitize vrXXX when either of
keep-vr5400 or keep-vr4320 are specified.
Move two basic vr4100 instructions from mips.igen to vr.igen.
Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
register upon non-zero interrupt event level, clear upon zero
event value.
* dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
by passing zero event value.
(*_io_{read,write}_buffer): Endianness fixes.
* dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
(deliver_*_tick): Reduce sim event interval to 75% of count interval.
* interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
serial I/O and timer module at base address 0xFFFF0000.
It is not yet properly tested.
Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904tmr.c: New file - implements tx3904 timer.
* dv-tx3904{irc,cpu}.c: Mild reformatting.
* configure.in: Include tx3904tmr in hw_device list.
* configure: Rebuilt.
* interp.c (sim_open): Instantiate three timer instances.
Fix address typo of tx3904irc instance.
* Followup patch for SCEI PR 15853
* First check-in of TX3904 interrupt controller devices for ECC. [sanitized]
* First implementation of MIPS hardware interrupt emulation.
Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
modules. Recognize TX39 target with "mips*tx39" pattern.
* configure: Rebuilt.
* sim-main.h (*): Added many macros defining bits in
TX39 control registers.
(SignalInterrupt): Send actual PC instead of NULL.
(SignalNMIReset): New exception type.
* interp.c (board): New variable for future use to identify
a particular board being simulated.
(mips_option_handler,mips_options): Added "--board" option.
(interrupt_event): Send actual PC.
(sim_open): Make memory layout conditional on board setting.
(signal_exception): Initial implementation of hardware interrupt
handling. Accept another break instruction variant for simulator
exit.
(decode_coproc): Implement RFE instruction for TX39.
(mips.igen): Decode RFE instruction as such.
start-sanitize-tx3904
* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
* interp.c: Define "jmr3904" and "jmr3904debug" board types and
bbegin to implement memory map.
* dv-tx3904cpu.c: New file.
* dv-tx3904irc.c: New file.
end-sanitize-tx3904
Replace check_op_hilo with check_mult_hilo and check_div_hilo.
Add special r3900 version of do_mult_hilo.
(do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
with calls to check_mult_hilo.
(do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
with calls to check_div_hilo.
* common/aclocal.m4: call AM_EXEEXT in SIM_AC_COMMON, define
AM_CYGWIN32 and AM_EXEEXT.
* common/Make-common.in: set EXEEXT, add missing EXEEXTs
to run and install-common rules.
* common/configure: regenerate
And update all subdirectory ChangeLogs and configure files.
o When unpacking an r5900 FP value,
was not treating IEEE-NaN's as very
large values.
o When packing an r5900 FP result from an infinite
precision intermediate value was saturating
to IEEE-MAX instead of r5900-MAX
o The least significant bit of the FP status
register did not stick to one.
[ChangeLog]
Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (decode_coproc): Add proper 1000000 bit-string at top
of VU lower instruction.
VCALLMS-related were found/fixed.
[ChangeLog.sky]
* sky-vu.c ({read,write}_vu_special_reg): Add CMSAR[01] as special
registers for a VU. Behavior not as mandated.
({read,write}_vu_{misc,special}_reg): Create sim_io_error upon
access to unknown register. Behavior not as mandated.
* sky-vu.h (anonymous register numbering enum): Add CMSAR[01].
* sky-libvpe.c (indebug): Cache $ENV{'SKY_DEBUG'}.
[ChangeLog]
* Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
* interp.c (decode_coproc): Refer to VU CIA as a "special"
register, not as a "misc" register. Aha. Add activity
assertions after VCALLMS* instructions.
work!
[ChangeLog.sky]
* sky-vu.h (vu_device): Represent "macro instruction just stuffed
into fetch buffer" condition with new "m" bit. Rename old "m" to
"l".
* sky-libvpe.c (indebug): Save snapshot of environment value;
workaround for suspected memory corruption.
(fetch_inst): Respect new "m" macro-instruction flag for reporting
successful fetch to caller.
(exec_inst): Disassemble instruction here instead of fetch time.
Renamed old "m" -> "l" flag in VU state to track interlock
release.
(vpecallms_cycle): Call exec_inst only if fetch_inst did some
work.
* sky-vu.c (vu_attach, vu[01]_device): Revamped initialization to
ensure complete clear of tail part of struct at attach time.
(vu0_busy): Fix thinko.
(vu0_macro_issue): Adapt to new "l" flag.
(vu0_micro_interlock_released): Ditto.
(write_vu_special_reg): Ditto.
(read_vu_special_reg): Compute VBS0/VBS1 bits more explicitly.
The other VU status bits are not yet computed.
[ChangeLog]
* interp.c (decode_coproc): Do not apply superfluous E (end) flag
to upper code of generated VU instruction.
masking facility for PATH3 transfers.
[ChangeLog.sky]
Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com>
* sky-libvpe.c (exec-inst): Added "M" bit detection for upper
instruction.
* sky-pke.c (pke_check_stall): Added more assertions.
(pke_code_mskpath3): Use new GPUIF M3P control register.
* sky-pke.h (VU[01]_CIA): New macros that give VU CIA
pseudo-register addresses.
* sky-vu.h (vu_device, VectorUnitState): Merged structs.
(VectorUnitState.mflag): New field.
(VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers.
* sky-vu.c (vu0_busy): New function.
(vu0_q_busy): New function.
(vu0_macro_issue): New function.
(vu0_micro_interlock_released): New function.
(vu0_busy_in_{micro,macro}_mode): Deleted stubs.
(vu0_macro_hazard_check): Deleted stubs.
(vu_attach): Adapted code to merged device & state struct.
(read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register.
[ChangeLog]
start-sanitize-sky
Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (*): Adapt code to merged VU device & state structs.
(decode_coproc): Execute COP2 each macroinstruction without
pipelining, by stepping VU to completion state. Adapted to
read_vu_*_reg style of register access.
* mips.igen ([SL]QC2): Removed these COP2 instructions.
* r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
* sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
end-sanitize-sky
into single PKE-style vu.[ch].
[ChangeLog]
Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
start-sanitize-sky
* Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
* interp.c (sim_{load,store}_register): Use new vu[01]_device
static to access VU registers.
(decode_coproc): Added skeleton of sky COP2 (VU) instruction
decoding. Work in progress.
* mips.igen (LDCzz, SDCzz): Removed *5900 case for this
overlapping/redundant bit pattern.
(LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
progress.
* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
status register.
end-sanitize-sky
* interp.c (cop_lq, cop_sq): New functions for future 128-bit
access to coprocessor registers.
* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
[ChangeLog.sky]
* sky-engine.c (engine_run): Adapted from vu[01] -> vu merge.
* sky-hardware.c (register_devices): Ditto
* sky-pke.c (pke_fifo_*): Made these functions private again, now
that the GPUIF code does not use them.
* sky-pke.h (pke_fifo_*): Removed newly private declarations.
* sky-vu.c (*): Major rework: merge of old sky-vu0.c and
sky-vu1.c. Management of two VU devices parallels two PKEs.
Work in progress.
* sky-vu.h (*): Other half of merge.
(vu_device): New struct, parallel to pke_device.
the stand-alone executable.
[in ChangeLog.sky:]
* sky-gpuif.c (call_gs): Call properly into GPU2 library if
configured --with-sim-gpu2. Use SKY_GPU2_REFRESH symbol as
placeholder for future GPU2-refresh policy.
[in ChangeLog:]
* Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
configurable settings for stand-alone simulator.
start-sanitize-sky
* configure.in: Added --with-sim-gpu2 option to specify path of
sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
links/compiles stand-alone simulator with this library.
* interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
end-sanitize-sky
* configure.in: Added X11 search, just in case.
* configure: Regenerated.
* Makefile.in (vr4320.igen) : Added.
* configure.in (mips64vr4320-*-*): Added.
* configure : Rebuilt.
* mips.igen : Correct the bfd-names in the mips-ISA model entries.
Add the vr4320 model entry and mark the vr4320 insn as necessary.
little struct.
interp.c: Update. Also add floating point Max/Min functions.
mips.igen: Remove r5900 tag from any floating point instructions.
r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st).
r5400.igen: Tag mdmx functions as being mdmx specific.
update v850, tic80 and mips simulators.
IGEN - Prepend prefix to more generated symbols and macros
(idecode_issue, instruction_word).
IGEN - Add -Wnowith option to supress warnings about word size
inflicts in input files.
MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so
that a mips16 simulator built using IGEN can be compiled.
Use the bfd-processor name in the sim-engine switch.
Add nr_cpus argument to sim_engine_run.
tic80, v850, d30v, mips, common:
Update
mips: Fill in bfd-processor field of model records so that
they match ../bfd/archures.
For sim/mips, enable multi-sim support when mips64vr5400-elf is target.
For sim/igen, allow specification of a default machine (will need
more work later).
(ANDI): Was missing mipsIV model, fix assembler syntax.
(do_c_cond_fmt): New function.
(C.cond.fmt): Handle mips I-III which do not support CC field
separatly.
(bc1): Handle mips IV which do not have a delaed FCC separatly.
(SDR): Mask paddr when BigEndianMem, not the converse as specified
in IV3.2 spec.
(DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
vr5000 which saves LO in a GPR separatly.
* configure.in (enable-sim-igen): For vr5000, select vr5000
specific instructions.
* configure: Re-generate.
MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
calls) and sim_open so that they uses the virtual memory data transfer
functions sim_read & sim_write. This eliminates all code (other than
in load_memory & store_memory) that makes assumptions about the
implementation of the underlying memory model.
When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
