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Re-fix 32 bit DSRAV instruction.

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Fix mips16 BRANCH, unsigned ADD/SUB and SRAV instructions.
This commit is contained in:
Andrew Cagney 1998-04-15 14:04:01 +00:00
parent ea5d84f5dc
commit 74025eeea7
2 changed files with 25 additions and 6 deletions
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10
sim/mips/ChangeLog
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@ -1,3 +1,13 @@
Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
* mips.igen (DSRAV): Use function do_dsrav.
(SRAV): Use new function do_srav.
* m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
(B): Sign extend 11 bit immediate.
(EXT-B*): Shift 16 bit immediate left by 1.
(ADDIU*): Don't sign extend immediate value.
Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
* m16run.c (sim_engine_run): Restore CIA after handling an event.

21
sim/mips/mips.igen
View file

@ -1287,7 +1287,7 @@
}
:function:::void:do_srav:int rs, int rt, int rd
:function:::void:do_dsrav:int rs, int rt, int rd
{
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
@ -1313,12 +1313,12 @@
*tx19:
// end-sanitize-tx19
{
do_srav (SD_, RS, RT, RD);
do_dsrav (SD_, RS, RT, RD);
}
00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
"dsrav r<RD>, r<RT>, <SHIFT>"
"dsrl r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
*vr5000:
@ -2857,6 +2857,16 @@
}
:function:::void:do_srav:int rs, int rt, int rd
{
int s = MASKED (GPR[rs], 4, 0);
signed32 temp = (signed32) GPR[rt] >> s;
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
@ -2875,12 +2885,11 @@
*tx19:
// end-sanitize-tx19
{
int s = MASKED (GPR[RS], 4, 0);
signed32 temp = (signed32) GPR[RT] >> s;
GPR[RD] = EXTEND32 (temp);
do_srav (SD_, RS, RT, RD);
}
:function:::void:do_srl:int rt, int rd, int shift
{
unsigned32 temp = (unsigned32) GPR[rt] >> shift;