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* interp.c (sim_fetch_register): Convert internal r5900 regs to

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target byte order
This commit is contained in:
Andrew Cagney 1998-05-21 08:18:21 +00:00
parent 643878d017
commit 8404825993
2 changed files with 10 additions and 1 deletions
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9
sim/mips/ChangeLog
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@ -1,3 +1,10 @@
start-sanitize-r5900
Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_fetch_register): Convert internal r5900 regs to
target byte order
end-sanitize-r5900
Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
@ -35,11 +42,13 @@ Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
function check_op_hilo_hi1lo1 with the pair
check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
start-sanitize-r5900
Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
* tx.igen (madd,maddu): Replace calls to check_op_hilo
with calls to check_div_hilo.
end-sanitize-r5900
Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
* mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):

2
sim/mips/interp.c
View file

@ -1017,7 +1017,7 @@ sim_fetch_register (sd,rn,memory,length)
/* start-sanitize-r5900 */
if (rn >= 90 && rn < 90 + 32)
{
*(unsigned64*)memory = GPR1[rn - 90];
*((unsigned64*)memory) = H2T_8 (GPR1[rn - 90]);
return 8;
}
switch (rn)