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* SYSCALL now uses exception vector.

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* SKY: New memory mapping rules for k1seg, k0seg.
* Modified Files: ChangeLog.sky ChangeLog interp.c sim-main.c
This commit is contained in:
Ian Carmichael 1998-06-02 19:53:36 +00:00
parent 936433a9fd
commit 8e3a0b599f
3 changed files with 75 additions and 36 deletions
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5
sim/mips/ChangeLog
View file

@ -1,3 +1,8 @@
Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
* interp.c (signal_exception): SystemCall exception now uses
the exception vector.
Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (decode_coproc): For TX39, add stub COP0 register #3,

32
sim/mips/interp.c
View file

@ -462,6 +462,7 @@ sim_open (kind, cb, abfd, argv)
{
/* Allocate core managed memory */
#ifndef TARGET_SKY
/* the monitor */
sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
/* For compatibility with the old code - under this (at level one)
@ -469,7 +470,6 @@ sim_open (kind, cb, abfd, argv)
smaller sub region */
sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
/* start-sanitize-sky */
#ifndef TARGET_SKY
/* end-sanitize-sky */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
K1BASE, K0SIZE,
@ -477,11 +477,12 @@ sim_open (kind, cb, abfd, argv)
K0BASE);
/* start-sanitize-sky */
#else
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
K1BASE, K0SIZE,
MEM_SIZE, /* actual size */
K0BASE,
0); /* add alias at 0x0000 */
/* the monitor */
sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE - K1BASE, MONITOR_SIZE);
sim_do_command (sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
/* 16M @ 0x0. Aliases at 0x80000000 and 0xA0000000 are handled by
address_translation() */
sim_do_commandf (sd, "memory size 0x%lx", MEM_SIZE);
#endif
/* end-sanitize-sky */
@ -1772,23 +1773,6 @@ signal_exception (SIM_DESC sd,
switch (exception) {
case SystemCall :
{
va_list ap;
unsigned int instruction;
unsigned int code;
va_start(ap,exception);
instruction = va_arg(ap,unsigned int);
va_end(ap);
code = (instruction >> 6) & 0xFFFFF;
sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
code, pr_addr(cia));
}
break;
case DebugBreakPoint :
if (! (Debug & Debug_DM))
{
@ -1974,12 +1958,12 @@ signal_exception (SIM_DESC sd,
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGFPE);
case SystemCall:
case Trap:
sim_engine_restart (SD, CPU, NULL, PC);
break;
case Watch:
case SystemCall:
PC = EPC;
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGTRAP);

74
sim/mips/sim-main.c
View file

@ -75,6 +75,23 @@ address_translation (SIM_DESC sd,
vAddr &= 0xFFFFFFFF;
*pAddr = vAddr; /* default for isTARGET */
/* start-sanitize-sky */
#ifdef TARGET_SKY
if (vAddr >= 0x80000000)
{
if (vAddr < 0xa0000000)
{
*pAddr = vAddr - 0x80000000;
}
else if (vAddr < 0xc0000000)
{
*pAddr = vAddr - 0xa0000000;
}
}
#endif
/* end-sanitize-sky */
*CCA = Uncached; /* not used for isHOST */
return(res);
@ -145,12 +162,15 @@ load_memory (SIM_DESC SD,
sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
#endif /* WARN_MEM */
#if !(WITH_IGEN)
/* IGEN performs this test in ifetch16() / ifetch32() */
/* If instruction fetch then we need to check that the two lo-order
bits are zero, otherwise raise a InstructionFetch exception: */
if ((IorD == isINSTRUCTION)
&& ((pAddr & 0x3) != 0)
&& (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
SignalExceptionInstructionFetch ();
#endif
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
{
@ -361,22 +381,52 @@ ifetch32 (SIM_DESC SD,
address_word vaddr)
{
/* Copy the action of the LW instruction */
address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
unsigned64 value;
address_word mask = LOADDRMASK;
address_word access = AccessLength_WORD;
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
unsigned32 instruction;
unsigned byte;
int cca;
AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
return instruction;
int uncached;
unsigned64 memval;
if ((vaddr & access) != 0)
SignalExceptionInstructionFetch ();
AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
byte = ((vaddr & mask) ^ bigendiancpu);
return (memval >> (8 * byte));
}
INLINE_SIM_MAIN (unsigned16)
ifetch16 (SIM_DESC SD,
sim_cpu *CPU,
address_word cia,
address_word vaddr)
{
/* Copy the action of the LH instruction */
address_word mask = LOADDRMASK;
address_word access = AccessLength_HALFWORD;
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
int uncached;
unsigned64 memval;
if ((vaddr & access) != 0)
SignalExceptionInstructionFetch ();
AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
byte = ((vaddr & mask) ^ bigendiancpu);
return (memval >> (8 * byte));
}
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* Order loads and stores to synchronise shared memory. Perform the
action necessary to make the effects of groups of synchronizable