Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1,
SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI, MFHI instructions. Trace nullified instruction.
This commit is contained in:
Andrew Cagney
parent
f445a8902d
commit
030843d7f8
5 changed files with 396 additions and 121 deletions
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@ -1,3 +1,22 @@
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Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* mips.igen: Delay slot branches add OFFSET to NIA not CIA.
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(MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
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(start-sanitize-r5900):
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(LWXC1, SWXC1): Delete from r5900 instruction set.
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(end-sanitize-r5900):
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(MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
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PENDING_FILL versions of instructions.
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(X): New function.
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(MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
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instructions.
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(BEQZ, ...): Explicitly cast GPR to a signed value.
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(MTHI, MFHI): Disable code checking HI-LO.
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* sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
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global.
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(NULLIFY_NEXT_INSTRUCTION): Call dotrace.
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Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* gencode.c (build_mips16_operands): Replace IPC with cia.
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@ -103,7 +103,6 @@ char* pr_uword64 PARAMS ((uword64 addr));
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/*-- GDB simulator interface ------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static void dotrace PARAMS((SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...));
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static void ColdReset PARAMS((SIM_DESC sd));
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/*---------------------------------------------------------------------------*/
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@ -144,7 +143,7 @@ static void ColdReset PARAMS((SIM_DESC sd));
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#if defined(TRACE)
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static char *tracefile = "trace.din"; /* default filename for trace log */
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static FILE *tracefh = NULL;
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FILE *tracefh = NULL;
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static void open_trace PARAMS((SIM_DESC sd));
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#endif /* TRACE */
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@ -806,7 +805,7 @@ sim_monitor(sd,cia,reason)
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address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
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H2T (value);
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sim_write (sd, A0, (char *)&value, sizeof (value));
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sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n");
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/* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
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break;
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}
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@ -1129,8 +1128,8 @@ mips16_entry (sd,insn)
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currently have an ARM version of their tool called ChARM. */
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static
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void dotrace(SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
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void
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dotrace (SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
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{
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if (STATE & simTRACE) {
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va_list ap;
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@ -50,11 +50,18 @@
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// Pseudo instructions known by IGEN
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:internal::::illegal:
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{
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/* FIXME: This ifetch causes a double count of a fetch at CIA */
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SignalException (ReservedInstruction, IMEM (CIA));
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SignalException (ReservedInstruction, 0);
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}
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// Pseudo instructions known by interp.c
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// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
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000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
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"rsvd <OP>"
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{
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SignalException (ReservedInstruction, instruction_0);
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}
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//
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@ -212,8 +219,8 @@
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// end-sanitize-tx19
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] == GPR[RT])
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
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DELAY_SLOT (NIA + offset);
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}
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@ -234,8 +241,8 @@
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// end-sanitize-tx19
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] == GPR[RT])
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
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DELAY_SLOT (NIA + offset);
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else
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NULLIFY_NEXT_INSTRUCTION ();
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}
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@ -259,8 +266,8 @@
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// end-sanitize-tx19
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] >= 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] >= 0)
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DELAY_SLOT (NIA + offset);
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}
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@ -283,8 +290,8 @@
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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RA = (CIA + 8);
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if (GPR[RS] >= 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] >= 0)
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DELAY_SLOT (NIA + offset);
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}
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@ -308,8 +315,8 @@
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RA = (CIA + 8);
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/* NOTE: The branch occurs AFTER the next instruction has been
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executed */
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if (GPR[RS] >= 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] >= 0)
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DELAY_SLOT (NIA + offset);
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else
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NULLIFY_NEXT_INSTRUCTION ();
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}
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@ -332,8 +339,8 @@
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// end-sanitize-tx19
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] >= 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] >= 0)
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DELAY_SLOT (NIA + offset);
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else
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NULLIFY_NEXT_INSTRUCTION ();
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}
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@ -357,8 +364,8 @@
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// end-sanitize-tx19
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] > 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] > 0)
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DELAY_SLOT (NIA + offset);
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}
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@ -381,8 +388,8 @@
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address_word offset = EXTEND16 (OFFSET) << 2;
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/* NOTE: The branch occurs AFTER the next instruction has been
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executed */
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if (GPR[RS] > 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] > 0)
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DELAY_SLOT (NIA + offset);
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else
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NULLIFY_NEXT_INSTRUCTION ();
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}
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@ -408,8 +415,8 @@
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address_word offset = EXTEND16 (OFFSET) << 2;
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/* NOTE: The branch occurs AFTER the next instruction has been
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executed */
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if (GPR[RS] <= 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] <= 0)
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DELAY_SLOT (NIA + offset);
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}
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@ -430,8 +437,8 @@
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// end-sanitize-tx19
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] <= 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] <= 0)
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DELAY_SLOT (NIA + offset);
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else
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NULLIFY_NEXT_INSTRUCTION ();
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}
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@ -455,8 +462,8 @@
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// end-sanitize-tx19
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] < 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] < 0)
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DELAY_SLOT (NIA + offset);
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}
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@ -481,8 +488,8 @@
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RA = (CIA + 8);
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/* NOTE: The branch occurs AFTER the next instruction has been
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executed */
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if (GPR[RS] < 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] < 0)
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DELAY_SLOT (NIA + offset);
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}
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@ -504,8 +511,8 @@
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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RA = (CIA + 8);
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if (GPR[RS] < 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] < 0)
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DELAY_SLOT (NIA + offset);
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else
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NULLIFY_NEXT_INSTRUCTION ();
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}
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@ -530,8 +537,8 @@
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address_word offset = EXTEND16 (OFFSET) << 2;
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/* NOTE: The branch occurs AFTER the next instruction has been
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executed */
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if (GPR[RS] < 0)
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] < 0)
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DELAY_SLOT (NIA + offset);
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else
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NULLIFY_NEXT_INSTRUCTION ();
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}
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@ -555,8 +562,8 @@
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// end-sanitize-tx19
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] != GPR[RT])
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
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DELAY_SLOT (NIA + offset);
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}
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@ -577,8 +584,8 @@
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// end-sanitize-tx19
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] != GPR[RT])
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DELAY_SLOT (CIA + offset);
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if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
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DELAY_SLOT (NIA + offset);
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else
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NULLIFY_NEXT_INSTRUCTION ();
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}
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@ -1998,7 +2005,9 @@
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// end-sanitize-tx19
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{
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GPR[RD] = HI;
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#if 0
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HIACCESS = 3;
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#endif
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}
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@ -2020,7 +2029,9 @@
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// end-sanitize-tx19
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{
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GPR[RD] = LO;
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#if 0
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LOACCESS = 3; /* 3rd instruction will be safe */
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#endif
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}
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@ -2071,10 +2082,14 @@
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*tx19:
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// end-sanitize-tx19
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{
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#if 0
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if (HIACCESS != 0)
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sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
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#endif
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HI = GPR[RS];
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#if 0
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HIACCESS = 3; /* 3rd instruction will be safe */
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#endif
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}
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@ -2095,19 +2110,33 @@
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*tx19:
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// end-sanitize-tx19
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{
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#if 0
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if (LOACCESS != 0)
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sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
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#endif
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LO = GPR[RS];
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#if 0
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LOACCESS = 3; /* 3rd instruction will be safe */
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#endif
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}
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000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
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000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
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"mult r<RS>, r<RT>"
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*mipsI:
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*mipsII:
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*mipsIII:
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*mipsIV:
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{
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signed64 prod;
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CHECKHILO ("Multiplication");
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prod = (((signed64)(signed32) GPR[RS])
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* ((signed64)(signed32) GPR[RT]));
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LO = EXTEND32 (VL4_8 (prod));
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HI = EXTEND32 (VH4_8 (prod));
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}
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000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
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"mult r<RD>, r<RS>, r<RT>"
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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@ -2125,15 +2154,27 @@
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* ((signed64)(signed32) GPR[RT]));
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LO = EXTEND32 (VL4_8 (prod));
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HI = EXTEND32 (VH4_8 (prod));
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if (RD != 0)
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GPR[RD] = LO;
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}
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000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
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000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
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"multu r<RS>, r<RT>"
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*mipsI:
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*mipsII:
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*mipsIII:
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*mipsIV:
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{
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unsigned64 prod;
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CHECKHILO ("Multiplication");
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prod = (((unsigned64)(unsigned32) GPR[RS])
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* ((unsigned64)(unsigned32) GPR[RT]));
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LO = EXTEND32 (VL4_8 (prod));
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HI = EXTEND32 (VH4_8 (prod));
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}
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000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
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"multu r<RD>, r<RS>, r<RT>"
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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@ -2151,6 +2192,8 @@
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* ((unsigned64)(unsigned32) GPR[RT]));
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LO = EXTEND32 (VL4_8 (prod));
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HI = EXTEND32 (VH4_8 (prod));
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if (RD != 0)
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GPR[RD] = LO;
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}
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@ -3412,6 +3455,16 @@
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}
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}
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:%s::::X:int x
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{
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switch (x)
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{
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case 0: return "f";
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case 1: return "t";
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default: return "?";
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}
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}
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:%s::::TF:int tf
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{
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if (tf)
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@ -3553,7 +3606,7 @@
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int condition = (PREVCOC1() == boolean);
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/* NOTE: The branch occurs AFTER the next instruction has been executed */
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if (condition) {
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DELAY_SLOT (CIA + offset);
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DELAY_SLOT (NIA + offset);
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}
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else if (likely) {
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NULLIFY_NEXT_INSTRUCTION ();
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@ -3688,10 +3741,32 @@
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// CFC1
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// CTC1
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01000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1
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010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
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"c%s<X>c1 r<RT>, f<FS>"
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*mipsI:
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*mipsII:
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*mipsIII:
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{
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if (X)
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{
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if (FS == 0)
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PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
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else if (FS == 31)
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PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
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/* else NOP */
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PENDING_FILL(COCIDX,0); /* special case */
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}
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else
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{ /* control from */
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if (FS == 0)
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PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
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else if (FS == 31)
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PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
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/* else NOP */
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}
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}
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010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
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"c%s<X>c1 r<RT>, f<FS>"
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*mipsIV:
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// start-sanitize-vr5400
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*vr5400:
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@ -3704,26 +3779,23 @@
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*tx19:
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// end-sanitize-tx19
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{
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unsigned32 instruction = instruction_0;
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int fs = ((instruction >> 11) & 0x0000001F);
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int ft = ((instruction >> 16) & 0x0000001F);
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int to = ((instruction >> 23) & 0x00000001);
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{
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if (to) {
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if (fs == 0) {
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PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft]));
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} else if (fs == 31) {
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PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft]));
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} /* else NOP */
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PENDING_FILL(COCIDX,0); /* special case */
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} else { /* control from */
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if (fs == 0) {
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PENDING_FILL(ft,SIGNEXTEND(FCR0,32));
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} else if (fs == 31) {
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PENDING_FILL(ft,SIGNEXTEND(FCR31,32));
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} /* else NOP */
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if (X)
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{
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if (FS == 0)
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FCR0 = VL4_8(GPR[RT]);
|
||||
else if (FS == 31)
|
||||
FCR31 = VL4_8(GPR[RT]);
|
||||
/* else NOP */
|
||||
SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
|
||||
}
|
||||
else
|
||||
{ /* control from */
|
||||
if (FS == 0)
|
||||
GPR[RT] = SIGNEXTEND (FCR0, 32);
|
||||
else if (FS == 31)
|
||||
GPR[RT] = SIGNEXTEND (FCR31, 32);
|
||||
/* else NOP */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -3884,8 +3956,32 @@
|
|||
|
||||
// DMFC1
|
||||
// DMTC1
|
||||
01000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1
|
||||
010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
|
||||
"dm%s<X>c1 r<RT>, f<FS>"
|
||||
*mipsIII:
|
||||
{
|
||||
if (X)
|
||||
{
|
||||
if (SizeFGR() == 64)
|
||||
PENDING_FILL((FS + FGRIDX),GPR[RT]);
|
||||
else if ((FS & 0x1) == 0)
|
||||
{
|
||||
PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
|
||||
PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (SizeFGR() == 64)
|
||||
PENDING_FILL(RT,FGR[FS]);
|
||||
else if ((FS & 0x1) == 0)
|
||||
PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
|
||||
else
|
||||
PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
|
||||
}
|
||||
}
|
||||
010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
|
||||
"dm%s<X>c1 r<RT>, f<FS>"
|
||||
*mipsIV:
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
|
|
@ -3898,31 +3994,25 @@
|
|||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
unsigned32 instruction = instruction_0;
|
||||
int fs = ((instruction >> 11) & 0x0000001F);
|
||||
int ft = ((instruction >> 16) & 0x0000001F);
|
||||
int to = ((instruction >> 23) & 0x00000001);
|
||||
{
|
||||
if (to) {
|
||||
if (SizeFGR() == 64) {
|
||||
PENDING_FILL((fs + FGRIDX),GPR[ft]);
|
||||
} else
|
||||
if ((fs & 0x1) == 0)
|
||||
{
|
||||
PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft]));
|
||||
PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft]));
|
||||
}
|
||||
} else {
|
||||
if (SizeFGR() == 64) {
|
||||
PENDING_FILL(ft,FGR[fs]);
|
||||
} else
|
||||
if ((fs & 0x1) == 0) {
|
||||
PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs]));
|
||||
} else {
|
||||
PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
|
||||
if (X)
|
||||
{
|
||||
if (SizeFGR() == 64)
|
||||
FGR[FS] = GPR[RT];
|
||||
else if ((FS & 0x1) == 0)
|
||||
{
|
||||
FGR[FS + 1] = VH4_8 (GPR[RT]);
|
||||
FGR[FS] = VL4_8 (GPR[RT]);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (SizeFGR() == 64)
|
||||
GPR[RT] = FGR[FS];
|
||||
else if ((FS & 0x1) == 0)
|
||||
GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
|
||||
else
|
||||
GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -3983,8 +4073,45 @@
|
|||
}
|
||||
|
||||
|
||||
// LDC1
|
||||
110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1
|
||||
110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
|
||||
"ldc1 f<FD>, <OFFSET>(r<BASE>)"
|
||||
*mipsII:
|
||||
*mipsIII:
|
||||
*mipsIV:
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
*r3900:
|
||||
// start-sanitize-tx19
|
||||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
signed_word offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16);
|
||||
int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
|
||||
signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
|
||||
{
|
||||
address_word vaddr = ((uword64)op1 + offset);
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
if ((vaddr & 7) != 0)
|
||||
SignalExceptionAddressLoad();
|
||||
else
|
||||
{
|
||||
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
||||
{
|
||||
uword64 memval = 0;
|
||||
uword64 memval1 = 0;
|
||||
uword64 mask = 0x7;
|
||||
unsigned int shift = 4;
|
||||
unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
|
||||
unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
|
||||
unsigned int byte UNUSED;
|
||||
LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
|
||||
COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
|
||||
|
|
@ -3993,9 +4120,6 @@
|
|||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-r5900
|
||||
*r5900:
|
||||
// end-sanitize-r5900
|
||||
{
|
||||
unsigned32 instruction = instruction_0;
|
||||
int destreg = ((instruction >> 6) & 0x0000001F);
|
||||
|
|
@ -4021,8 +4145,53 @@
|
|||
}
|
||||
|
||||
|
||||
// LWC1
|
||||
110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
|
||||
|
||||
110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
|
||||
"swc1 f<FT>, <OFFSET>(r<BASE>)"
|
||||
*mipsI:
|
||||
*mipsII:
|
||||
*mipsIII:
|
||||
*mipsIV:
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-r5900
|
||||
*r5900:
|
||||
// end-sanitize-r5900
|
||||
*r3900:
|
||||
// start-sanitize-tx19
|
||||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
unsigned32 instruction = instruction_0;
|
||||
signed_word offset = EXTEND16 (OFFSET);
|
||||
int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
|
||||
signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
|
||||
{
|
||||
address_word vaddr = ((uword64)op1 + offset);
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
if ((vaddr & 3) != 0)
|
||||
SignalExceptionAddressLoad();
|
||||
else
|
||||
{
|
||||
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
||||
{
|
||||
uword64 memval = 0;
|
||||
uword64 memval1 = 0;
|
||||
uword64 mask = 0x7;
|
||||
unsigned int shift = 2;
|
||||
unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
|
||||
unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
|
||||
unsigned int byte UNUSED;
|
||||
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
|
||||
LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
|
||||
byte = ((vaddr & mask) ^ (bigend << shift));
|
||||
COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
|
||||
|
|
@ -4031,9 +4200,6 @@
|
|||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-r5900
|
||||
*r5900:
|
||||
// end-sanitize-r5900
|
||||
{
|
||||
unsigned32 instruction = instruction_0;
|
||||
int destreg = ((instruction >> 6) & 0x0000001F);
|
||||
|
|
@ -4113,11 +4279,25 @@
|
|||
|
||||
|
||||
// MFC1
|
||||
// MTC1
|
||||
010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
|
||||
"m<X>c1 r<RT>, f<FS>"
|
||||
"m%s<X>c1 r<RT>, f<FS>"
|
||||
*mipsI:
|
||||
*mipsII:
|
||||
*mipsIII:
|
||||
{
|
||||
if (X)
|
||||
{ /*MTC1*/
|
||||
if (SizeFGR() == 64)
|
||||
PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
|
||||
else
|
||||
PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
|
||||
}
|
||||
else /*MFC1*/
|
||||
PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
|
||||
}
|
||||
010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
|
||||
"m%s<X>c1 r<RT>, f<FS>"
|
||||
*mipsIV:
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
|
|
@ -4130,21 +4310,15 @@
|
|||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
unsigned32 instruction = instruction_0;
|
||||
int fs = ((instruction >> 11) & 0x0000001F);
|
||||
int ft = ((instruction >> 16) & 0x0000001F);
|
||||
int to = ((instruction >> 23) & 0x00000001);
|
||||
{
|
||||
if (to) {
|
||||
if (SizeFGR() == 64) {
|
||||
PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft])));
|
||||
} else {
|
||||
PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft]));
|
||||
}
|
||||
} else {
|
||||
PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32));
|
||||
if (X)
|
||||
{ /*MTC1*/
|
||||
if (SizeFGR() == 64)
|
||||
FGR[FS] = (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT]));
|
||||
else
|
||||
FGR[FS] = VL4_8 (GPR[RT]);
|
||||
}
|
||||
}
|
||||
else /*MFC1*/
|
||||
GPR[RT] = SIGNEXTEND(FGR[FS],32);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -4560,7 +4734,43 @@
|
|||
}
|
||||
|
||||
|
||||
// SDC1
|
||||
111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
|
||||
"sdc1 f<FT>, <OFFSET>(r<BASE>)"
|
||||
*mipsII:
|
||||
*mipsIII:
|
||||
*mipsIV:
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
*r3900:
|
||||
// start-sanitize-tx19
|
||||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
unsigned32 instruction = instruction_0;
|
||||
signed_word offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16);
|
||||
int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
|
||||
signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
|
||||
{
|
||||
address_word vaddr = ((uword64)op1 + offset);
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
if ((vaddr & 7) != 0)
|
||||
SignalExceptionAddressStore();
|
||||
else
|
||||
{
|
||||
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
||||
{
|
||||
uword64 memval = 0;
|
||||
uword64 memval1 = 0;
|
||||
memval = (uword64)COP_SD(((instruction >> 26) & 0x3),destreg);
|
||||
{
|
||||
StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
|
||||
|
|
@ -4568,9 +4778,6 @@
|
|||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-r5900
|
||||
*r5900:
|
||||
// end-sanitize-r5900
|
||||
{
|
||||
unsigned32 instruction = instruction_0;
|
||||
int fs = ((instruction >> 11) & 0x0000001F);
|
||||
|
|
@ -4658,7 +4865,52 @@
|
|||
}
|
||||
|
||||
|
||||
// SWC1
|
||||
|
||||
111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
|
||||
"swc1 f<FT>, <OFFSET>(r<BASE>)"
|
||||
*mipsI:
|
||||
*mipsII:
|
||||
*mipsIII:
|
||||
*mipsIV:
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-r5900
|
||||
*r5900:
|
||||
// end-sanitize-r5900
|
||||
*r3900:
|
||||
// start-sanitize-tx19
|
||||
*tx19:
|
||||
// end-sanitize-tx19
|
||||
{
|
||||
unsigned32 instruction = instruction_0;
|
||||
signed_word offset = EXTEND16 (OFFSET);
|
||||
int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
|
||||
signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
|
||||
{
|
||||
address_word vaddr = ((uword64)op1 + offset);
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
if ((vaddr & 3) != 0)
|
||||
SignalExceptionAddressStore();
|
||||
else
|
||||
{
|
||||
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
||||
{
|
||||
uword64 memval = 0;
|
||||
uword64 memval1 = 0;
|
||||
uword64 mask = 0x7;
|
||||
unsigned int byte;
|
||||
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
|
||||
byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
|
||||
memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
|
||||
{
|
||||
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
|
||||
|
|
@ -4667,9 +4919,6 @@
|
|||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-r5900
|
||||
*r5900:
|
||||
// end-sanitize-r5900
|
||||
{
|
||||
unsigned32 instruction = instruction_0;
|
||||
int fs = ((instruction >> 11) & 0x0000001F);
|
||||
|
|
@ -4899,7 +5148,9 @@
|
|||
// start-sanitize-r5900
|
||||
*r5900:
|
||||
// end-sanitize-r5900
|
||||
|
||||
{
|
||||
DecodeCoproc (instruction_0);
|
||||
}
|
||||
|
||||
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
|
||||
"mtc0 r<RT>, r<RD> # <REGX>"
|
||||
|
|
@ -4913,6 +5164,9 @@
|
|||
// start-sanitize-r5900
|
||||
*r5900:
|
||||
// end-sanitize-r5900
|
||||
{
|
||||
DecodeCoproc (instruction_0);
|
||||
}
|
||||
|
||||
|
||||
010000,10000,000000000000000,001000:COP0:32::TLBP
|
||||
|
|
|
|||
|
|
@ -316,6 +316,7 @@ struct _sim_cpu {
|
|||
#define NULLIFY_NEXT_INSTRUCTION() \
|
||||
do { \
|
||||
sim_events_slip (sd, 1); \
|
||||
dotrace (sd, tracefh, 2, NIA, 4, "load instruction"); \
|
||||
NIA = CIA + 8; \
|
||||
} while (0)
|
||||
|
||||
|
|
@ -712,5 +713,7 @@ void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAdd
|
|||
unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr));
|
||||
#define IMEM(CIA) ifetch32 (SD, (CIA), (CIA))
|
||||
|
||||
void dotrace PARAMS ((SIM_DESC sd, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
|
||||
FILE *tracefh;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@
|
|||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply and Move Low.
|
||||
// Unsigned Multiply and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00001,011001::::MULU
|
||||
"mulu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
|
|
|
|||
Loading…
Reference in a new issue