Add new file vr.igen which is a merge of vr5400.igen and vr4320.igen.
Hack sanitize so that it doesn't sanitize vrXXX when either of keep-vr5400 or keep-vr4320 are specified. Move two basic vr4100 instructions from mips.igen to vr.igen.
This commit is contained in:
Andrew Cagney
parent
5a483f4d88
commit
e1b20d3048
3 changed files with 555 additions and 2 deletions
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@ -86,6 +86,7 @@ m16.dc
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m16run.c
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mips.dc
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tx.igen
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vr.igen
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Things-to-lose:
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@ -212,7 +213,7 @@ else
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fi
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vr5400_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen vr5400.igen mdmx.igen"
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vr5400_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc vr5400.igen mdmx.igen vr.igen"
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if ( echo $* | grep keep\-vr5400 > /dev/null ) ; then
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for i in $vr5400_files ; do
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@ -241,7 +242,7 @@ else
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done
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fi
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vr4320_files="ChangeLog Makefile.in configure configure.in mips.igen"
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vr4320_files="ChangeLog Makefile.in configure configure.in mips.igen vr.igen vr4320.igen"
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if ( echo $* | grep keep\-vr4320 > /dev/null ) ; then
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for i in $vr4320_files ; do
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@ -271,6 +272,36 @@ else
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fi
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vrXXXX_files="vr.igen"
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if ( echo $* | grep keep\-vr > /dev/null ) ; then
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for i in $vrXXXX_files ; do
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if test ! -d $i && (grep sanitize-vrXXXX $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Keeping vrXXXX stuff in $i
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fi
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fi
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done
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else
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for i in * ; do
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if test ! -d $i && (grep sanitize-vrXXXX $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Removing traces of \"vrXXXX\" from $i...
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fi
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cp $i new
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sed '/start\-sanitize\-vrXXXX/,/end-\sanitize\-vrXXXX/d' < $i > new
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if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
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if [ -n "${verbose}" ] ; then
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echo Caching $i in .Recover...
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fi
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mv $i .Recover
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fi
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mv new $i
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fi
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done
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fi
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tx3904_files="ChangeLog configure configure.in interp.c"
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if ( echo $* | grep keep\-tx3904 > /dev/null ) ; then
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@ -1,3 +1,34 @@
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Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* vr.igen: New file.
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(MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
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* mips.igen: Define vr4100 model. Include vr.igen.
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start-sanitize-r5900
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Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* r5900.igen (r59fp_overflow): Replace argument ANS with argument
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SIGN_P.
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(r59fp_zero): Ditto.
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(r59fp_store): Update calls.
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(DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
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end-sanitize-r5900
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start-sanitize-branchbug4011
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Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com>
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* interp.c (OPTION_BRANCH_BUG_4011): Add.
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(mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
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(mips_options): Define the option.
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* mips.igen (check_4011_branch_bug): New.
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(mark_4011_branch_bug): New.
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(all branch insn): Call mark_branch_bug, and check_branch_bug.
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* sim-main.h (branchbug4011_option, branchbug4011_last_target,
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branchbug4011_last_cia, BRANCHBUG4011_OPTION,
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BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
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check_branch_bug, mark_branch_bug): Define.
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end-sanitize-branchbug4011
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Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
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* mips.igen (check_mf_hilo): Correct check.
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491
sim/mips/vr.igen
Normal file
491
sim/mips/vr.igen
Normal file
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@ -0,0 +1,491 @@
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// -*- C -*-
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//
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// NEC specific instructions
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//
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// Integer Instructions
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// --------------------
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//
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// MulAcc is the Multiply Accumulator.
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// This register is mapped on the the HI and LO registers.
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// Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
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// Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
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:function:::unsigned64:MulAcc:
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{
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unsigned64 result = U8_4 (HI, LO);
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return result;
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}
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:function:::void:SET_MulAcc:unsigned64 value
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{
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*AL4_8 (&HI) = VH4_8 (value);
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*AL4_8 (&LO) = VL4_8 (value);
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}
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:function:::signed64:SignedMultiply:signed32 l, signed32 r
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{
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signed64 result = (signed64) l * (signed64) r;
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return result;
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}
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:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
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{
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unsigned64 result = (unsigned64) l * (unsigned64) r;
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return result;
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}
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:function:::unsigned64:Low32Bits:unsigned64 value
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{
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unsigned64 result = (signed64) (signed32) VL4_8 (value);
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return result;
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}
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:function:::unsigned64:High32Bits:unsigned64 value
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{
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unsigned64 result = (signed64) (signed32) VH4_8 (value);
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return result;
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}
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// Multiply, Accumulate
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000000,5.RS,5.RT,00000,00000,101000::::MAC
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"mac r<RS>, r<RT>"
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*vr4100:
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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{
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SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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}
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// D-Multiply, Accumulate
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000000,5.RS,5.RT,00000,00000,101001::::DMAC
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"dmac r<RS>, r<RT>"
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*vr4100:
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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{
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LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
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}
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// start-sanitize-vr4320
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// Count Leading Zeros
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000000,5.RS,00000,5.RD,00000,110101::::CLZ
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"clz r<RD>, r<RS>"
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// end-sanitize-vr4320
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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// start-sanitize-vr4320
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{
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unsigned32 t = Low32Bits (SD_, GPR[RS]);
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signed64 c = 0;
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while (! (t & ( 1 << 31))
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&& c < 32)
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{
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c++;
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t <<= 1;
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}
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GPR[RD] = c;
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}
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// end-sanitize-vr4320
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// start-sanitize-vr4320
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// D-Count Leading Zeros
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000000,5.RS,00000,5.RD,00000,111101::::DCLZ
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"dclz r<RD>, r<RS>"
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// end-sanitize-vr4320
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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// start-sanitize-vr4320
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{
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unsigned64 t = GPR[RS];
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signed64 c = 0;
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while (! (t & ( (unsigned64)1 << 63))
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&& c < 64)
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{
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c++;
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t <<= 1;
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}
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printf("lo %d\n", (int) c);
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GPR[RD] = c;
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}
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// end-sanitize-vr4320
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// start-sanitize-vrXXXX
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// Multiply and Move LO.
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000000,5.RS,5.RT,5.RD,00100,101000::::MUL
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"mul r<RD>, r<RS>, r<RT>"
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// end-sanitize-vrXXXX
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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// start-sanitize-vrXXXX
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{
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SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitize-vrXXXX
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// start-sanitize-vrXXXX
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// Unsigned Multiply and Move LO.
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000000,5.RS,5.RT,5.RD,00101,101000::::MULU
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"mulu r<RD>, r<RS>, r<RT>"
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// end-sanitize-vrXXXX
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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// start-sanitize-vrXXXX
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{
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SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitize-vrXXXX
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// start-sanitize-vrXXXX
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// Multiply and Move HI.
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000000,5.RS,5.RT,5.RD,01100,101000::::MULHI
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"mulhi r<RD>, r<RS>, r<RT>"
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// end-sanitize-vrXXXX
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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// start-sanitize-vrXXXX
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{
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SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitize-vrXXXX
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// start-sanitize-vrXXXX
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// Unsigned Multiply and Move HI.
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000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU
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"mulhiu r<RD>, r<RS>, r<RT>"
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// end-sanitize-vrXXXX
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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// start-sanitize-vrXXXX
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{
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SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitize-vrXXXX
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// start-sanitze-vr5400
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// Multiply, Negate and Move LO.
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000000,5.RS,5.RT,5.RD,00011,011000::::MULS
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"muls r<RD>, r<RS>, r<RT>"
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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{
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SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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// Unsigned Multiply, Negate and Move LO.
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000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
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"mulsu r<RD>, r<RS>, r<RT>"
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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{
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SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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// Multiply, Negate and Move HI.
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000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
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"mulshi r<RD>, r<RS>, r<RT>"
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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{
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SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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// Unsigned Multiply, Negate and Move HI.
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000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
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"mulshiu r<RD>, r<RS>, r<RT>"
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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// start-sanitze-vr5400
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{
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SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitze-vr5400
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// Multiply, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00010,101000::::MACC
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"macc r<RD>, r<RS>, r<RT>"
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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{
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SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitize-vr4320
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// start-sanitize-vrXXXX
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// Unsigned Multiply, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00011,101000::::MACCU
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"maccu r<RD>, r<RS>, r<RT>"
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// end-sanitize-vrXXXX
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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// start-sanitize-vrXXXX
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{
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SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitize-vrXXXX
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// start-sanitize-vrXXXX
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// Multiply, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI
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"macchi r<RD>, r<RS>, r<RT>"
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// end-sanitize-vrXXXX
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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// start-sanitze-vr5400
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*vr5400:
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// end-sanitze-vr5400
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// start-sanitize-vrXXXX
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{
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SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// end-sanitize-vrXXXX
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||||
// start-sanitize-vrXXXX
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// Unsigned Multiply, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU
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"macchiu r<RD>, r<RS>, r<RT>"
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// start-sanitize-vr4320
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*vr4320:
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// end-sanitize-vr4320
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||||
// start-sanitze-vr5400
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*vr5400:
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||||
// end-sanitze-vr5400
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{
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SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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||||
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// end-sanitize-vrXXXX
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// start-sanitize-vr5400
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// Multiply, Negate, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
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"msac r<RD>, r<RS>, r<RT>"
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// end-sanitize-vr5400
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||||
// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-vr5400
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{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
// Unsigned Multiply, Negate, Accumulate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
|
||||
"msacu r<RD>, r<RS>, r<RT>"
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
// Multiply, Negate, Accumulate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
|
||||
"msachi r<RD>, r<RS>, r<RT>"
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
// Unsigned Multiply, Negate, Accumulate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
|
||||
"msachiu r<RD>, r<RS>, r<RT>"
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
// Rotate Right.
|
||||
000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
|
||||
"ror r<RD>, r<RT>, <SHIFT>"
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
{
|
||||
int s = SHIFT;
|
||||
GPR[RD] = ROTR32 (GPR[RT], s);
|
||||
}
|
||||
|
||||
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
// Rotate Right Variable.
|
||||
000000,5.RS,5.RT,5.RD,00001,000110::::RORV
|
||||
"rorv r<RD>, r<RT>, <RS>"
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
{
|
||||
int s = MASKED (GPR[RS], 4, 0);
|
||||
GPR[RD] = ROTR32 (GPR[RT], s);
|
||||
}
|
||||
|
||||
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
// Double Rotate Right.
|
||||
000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
|
||||
"dror r<RD>, r<RT>, <SHIFT>"
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
{
|
||||
int s = SHIFT;
|
||||
GPR[RD] = ROTR64 (GPR[RT], s);
|
||||
}
|
||||
|
||||
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
// Double Rotate Right Plus 32.
|
||||
000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
|
||||
"dror32 r<RD>, r<RT>, <SHIFT>"
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
{
|
||||
int s = SHIFT + 32;
|
||||
GPR[RD] = ROTR64 (GPR[RT], s);
|
||||
}
|
||||
|
||||
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
// Double Rotate Right Variable.
|
||||
000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
|
||||
"drorv r<RD>, r<RT>, <RS>"
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
*vr5400:
|
||||
// end-sanitize-vr5400
|
||||
// start-sanitize-vr5400
|
||||
{
|
||||
int s = MASKED (GPR[RS], 5, 0);
|
||||
GPR[RD] = ROTR64 (GPR[RT], s);
|
||||
}
|
||||
|
||||
|
||||
// end-sanitize-vr5400
|
||||
Loading…
Reference in a new issue