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Allow reads/writes to C0_CONFIG register.

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This commit is contained in:
Andrew Cagney 1997-11-20 09:17:06 +00:00
parent 942f33aeb1
commit a09a30d298
3 changed files with 40 additions and 13 deletions
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6
sim/mips/ChangeLog
View file

@ -1,3 +1,9 @@
Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-main.h (Config): New register.
* interp.c (decode_coproc): Allow access to Config register.
Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
* Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).

28
sim/mips/interp.c
View file

@ -2065,12 +2065,16 @@ store_fpr(sd,cia,fpr,fmt,value)
if (SizeFGR() == 64) {
switch (fmt) {
case fmt_uninterpreted_32:
fmt = fmt_uninterpreted;
case fmt_single :
case fmt_word :
FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
FPR_STATE[fpr] = fmt;
break;
case fmt_uninterpreted_64:
fmt = fmt_uninterpreted;
case fmt_uninterpreted:
case fmt_double :
case fmt_long :
@ -2085,12 +2089,16 @@ store_fpr(sd,cia,fpr,fmt,value)
}
} else {
switch (fmt) {
case fmt_uninterpreted_32:
fmt = fmt_uninterpreted;
case fmt_single :
case fmt_word :
FGR[fpr] = (value & 0xFFFFFFFF);
FPR_STATE[fpr] = fmt;
break;
case fmt_uninterpreted_64:
fmt = fmt_uninterpreted;
case fmt_uninterpreted:
case fmt_double :
case fmt_long :
@ -3019,6 +3027,12 @@ decode_coproc(sd,cia,instruction)
break;
#else
/* 16 = Config R4000 VR4100 VR4300 */
case 16:
if (code == 0x00)
GPR[rt] = C0_CONFIG;
else
C0_CONFIG = GPR[rt];
break;
#endif
#ifdef SUBTARGET_R3900
/* 17 = Debug */
@ -3239,18 +3253,8 @@ sim_engine_run (sd, next_cpu_nr, siggnal)
[NOTE: pipeline_count has been replaced the event queue] */
#if defined(HASFPU)
/* Set previous flag, depending on current: */
if (STATE & simPCOC0)
STATE |= simPCOC1;
else
STATE &= ~simPCOC1;
/* and update the current value: */
if (GETFCC(0))
STATE |= simPCOC0;
else
STATE &= ~simPCOC0;
#endif /* HASFPU */
/* shuffle the floating point status pipeline state */
ENGINE_ISSUE_PREFIX_HOOK();
/* NOTE: For multi-context simulation environments the "instruction"
variable should be local to this routine. */

19
sim/mips/sim-main.h
View file

@ -97,6 +97,8 @@ typedef enum {
range, and are used in the register status vector. */
fmt_unknown = 0x10000000,
fmt_uninterpreted = 0x20000000,
fmt_uninterpreted_32 = 0x40000000,
fmt_uninterpreted_64 = 0x80000000,
} FP_formats;
unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
@ -339,7 +341,19 @@ struct _sim_cpu {
#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
#define ENGINE_ISSUE_PREFIX_HOOK() \
{ \
/* Set previous flag, depending on current: */ \
if (STATE & simPCOC0) \
STATE |= simPCOC1; \
else \
STATE &= ~simPCOC1; \
/* and update the current value: */ \
if (GETFCC(0)) \
STATE |= simPCOC0; \
else \
STATE &= ~simPCOC0; \
}
/* This is nasty, since we have to rely on matching the register
@ -385,6 +399,9 @@ struct _sim_cpu {
#define EPC (REGISTERS[88])
#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
unsigned_word c0_config_reg;
#define C0_CONFIG ((STATE_CPU (sd,0))->c0_config_reg)
/* The following are pseudonyms for standard registers */
#define ZERO (REGISTERS[0])
#define V0 (REGISTERS[2])