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* configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.

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Set mips_fpu, and mips_fpu_bitsize.
	Set sim_gen, and sim_igen_machine.
	* configure: Rebuild.
	* mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
	* sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
This commit is contained in:
Gavin Romig-Koch 1998-12-12 22:43:54 +00:00
parent b3f1799e81
commit 82aeada70c
4 changed files with 236 additions and 257 deletions
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12
sim/mips/ChangeLog
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@ -1,3 +1,15 @@
1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
start-sanitize-vr4xxx
* configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.
Set mips_fpu, and mips_fpu_bitsize.
Set sim_gen, and sim_igen_machine.
* configure: Rebuild.
end-sanitize-vr4xxx
* mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
* sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
* mips/interp.c (DEBUG): Cleanups.

466
sim/mips/configure vendored
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File diff suppressed because it is too large Load diff

11
sim/mips/configure.in
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@ -18,6 +18,9 @@ SIM_AC_OPTION_WARNINGS
# in question.
#
case "${target}" in
# start-sanitize-vr4xxx
mips64vr4xxx-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
# end-sanitize-vr4xxx
# start-sanitize-tx19
mips*tx19*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
# end-sanitize-tx19
@ -85,6 +88,9 @@ case "${target}" in
mips*tx39*) mips_fpu=HARD_FLOATING_POINT
mips_fpu_bitsize=32
;;
# start-sanitize-vr4xxx
mips64vr4xxx-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
# end-sanitize-vr4xxx
# start-sanitize-r5900
mips64r59*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;;
# end-sanitize-r5900
@ -161,6 +167,11 @@ case "${target}" in
sim_igen_machine="-M vr5000,vr5400 -G gen-multi-sim=vr5000"
;;
# end-sanitize-cygnus
# start-sanitize-vr4xxx
mips64vr4xxx-*-*) sim_gen=IGEN
sim_igen_machine="-M mipsIV,vr4100 -G gen-multi-sim=mipsIV"
;;
# end-sanitize-vr4xxx
mips64vr41*) sim_gen=M16
sim_igen_machine="-M vr4100"
sim_m16_machine="-M vr4100"

4
sim/mips/mips.igen
View file

@ -4178,7 +4178,7 @@
// BC1T
// BC1TL
010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
"bc1%s<TF>%s<ND> <OFFSET>"
*mipsI,mipsII,mipsIII:
*vr4100:
@ -4206,7 +4206,7 @@
}
}
010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
*mipsIV: