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old-cross-binutils/sim/mips/interp.c

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* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/*> interp.c <*/
/* Simulator for the MIPS architecture.
This file is part of the MIPS sim
THIS SOFTWARE IS NOT COPYRIGHTED
Cygnus offers the following for use in the public domain. Cygnus
makes no warranty with regard to the software or it's performance
and the user accepts the software "AS IS" with all faults.
CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
$Revision$
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
$Date$
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
NOTEs:
The IDT monitor (found on the VR4300 board), seems to lie about
register contents. It seems to treat the registers as sign-extended
32-bit values. This cause *REAL* problems when single-stepping 64-bit
code on the hardware.
*/
Delete profile support from MIPS simulator, use sim/common/sim-profile module instead. Generate a "gmon.out" (gprof) when profiling the target PC. Add target PC profiling option --profile-pc-granularity (bucket size)
1997-10-21 03:41:21 +00:00
/* The TRACE manifests enable the provision of extra features. If they
are not defined then a simpler (quicker) simulator is constructed
without the required run-time checks, etc. */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#if 1 /* 0 to allow user build selection, 1 to force inclusion */
#define TRACE (1)
#endif
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
#include "bfd.h"
#include "sim-main.h"
#include "sim-utils.h"
#include "sim-options.h"
Watchpoint interface.
1997-05-21 06:54:13 +00:00
#include "sim-assert.h"
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
#include "sim-hw.h"
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
/* start-sanitize-sky */
#ifdef TARGET_SKY
#include "sky-vu.h"
#include "sky-vpe.h"
#include "sky-libvpe.h"
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
#include "sky-pke.h"
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
#include "idecode.h"
* Changes to make interp.c compile under mips64r5900-sky-elf target. Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Make COP2 branch code compile after igen signature changes.
1998-04-15 19:02:04 +00:00
#include "support.h"
* Updated several files to place all sky specific runtime options in sky-gdb.c. * Added two new runtime options --sky-debug and --screen-refresh * ChangeLog.sky contains a detailed description of the mods
1998-06-10 17:07:09 +00:00
#include "sky-gdb.h"
* Changes to make interp.c compile under mips64r5900-sky-elf target. Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Make COP2 branch code compile after igen signature changes.
1998-04-15 19:02:04 +00:00
#undef SD
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
#endif
/* end-sanitize-sky */
* configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set stamp-h. * configure: Rebuild. * config.in: New file, generated by autoheader. * interp.c: Include "config.h". Include <stdlib.h>, <string.h>, and <strings.h> if they exist. Replace #ifdef sun with #ifdef HAVE_ANINT and HAVE_AINT, as appropriate. * Makefile.in (run): Use @LIBS@ rather than -lm. (interp.o): Depend upon config.h. (Makefile): Just rebuild Makefile. (clean): Remove stamp-h. (mostlyclean): Make the same as clean, not as distclean. (config.h, stamp-h): New targets.
1996-06-03 15:58:45 +00:00
#include "config.h"
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#include <stdio.h>
#include <stdarg.h>
#include <ansidecl.h>
#include <ctype.h>
#include <limits.h>
#include <math.h>
* configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set stamp-h. * configure: Rebuild. * config.in: New file, generated by autoheader. * interp.c: Include "config.h". Include <stdlib.h>, <string.h>, and <strings.h> if they exist. Replace #ifdef sun with #ifdef HAVE_ANINT and HAVE_AINT, as appropriate. * Makefile.in (run): Use @LIBS@ rather than -lm. (interp.o): Depend upon config.h. (Makefile): Just rebuild Makefile. (clean): Remove stamp-h. (mostlyclean): Make the same as clean, not as distclean. (config.h, stamp-h): New targets.
1996-06-03 15:58:45 +00:00
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
#ifdef HAVE_STRING_H
#include <string.h>
#else
#ifdef HAVE_STRINGS_H
#include <strings.h>
#endif
#endif
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#include "getopt.h"
#include "libiberty.h"
* Makefile.in (SIM_OBJS): Add sim-load.o. * interp.c: #include bfd.h. (target_byte_order): Delete. (sim_kind, myname, big_endian_p): New static locals. (sim_open): Set sim_kind, myname. Move call to set_endianness to after argument parsing. Recognize -E arg, set endianness accordingly. (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to load file into simulator. Set PC from bfd. (sim_create_inferior): Return SIM_RC. Delete arg start_address. (set_endianness): Use big_endian_p instead of target_byte_order.
1997-04-17 10:23:48 +00:00
#include "bfd.h"
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#include "callback.h" /* GDB simulator callback interface */
* Makefile.in: Delete stuff moved to ../common/Make-common.in. (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. * configure.in: Simplify using macros in ../common/aclocal.m4. * configure: Regenerated. * tconfig.in: New file.
1996-11-20 10:00:42 +00:00
#include "remote-sim.h" /* GDB simulator interface */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#include "sysdep.h"
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
#ifndef PARAMS
#define PARAMS(x)
#endif
char* pr_addr PARAMS ((SIM_ADDR addr));
Cleanups to compile under FreeBSD
1997-04-17 06:05:19 +00:00
char* pr_uword64 PARAMS ((uword64 addr));
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* Get the simulator engine description, without including the code: */
Re-do load/store operations so that they work for both 32 and 64 bit ISAs. Enable tx39 as igen again.
1998-04-02 19:35:39 +00:00
#if !(WITH_IGEN)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#define SIM_MANIFESTS
Rename generated file engine.c to oengine.c.
1997-10-16 03:39:13 +00:00
#include "oengine.c"
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#undef SIM_MANIFESTS
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
#endif
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
/* Within interp.c we refer to the sim_state and sim_cpu directly. */
#define CPU cpu
* Changes to make interp.c compile under mips64r5900-sky-elf target. Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Make COP2 branch code compile after igen signature changes.
1998-04-15 19:02:04 +00:00
#define SD sd
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (xfer_direct_word, xfer_direct_long, swap_direct_word, swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, xfer_little_long, swap_word,swap_long): Added. * interp.c (ColdReset): Provide function indirection to host<->simulated_target transfer routines. * interp.c (sim_store_register, sim_fetch_register): Updated to make use of indirected transfer routines.
1996-05-08 14:22:12 +00:00
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* The following reserved instruction value is used when a simulator
trap is required. NOTE: Care must be taken, since this value may be
used in later revisions of the MIPS ISA. */
Implement ERET instruction. Add {signed,unsigned}_address type.
1998-04-21 04:30:27 +00:00
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
#define RSVD_INSTRUCTION (0x00000005)
#define RSVD_INSTRUCTION_MASK (0xFC00003F)
#define RSVD_INSTRUCTION_ARG_SHIFT 6
#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
/* Bits in the Debug register */
#define Debug_DBD 0x80000000 /* Debug Branch Delay */
#define Debug_DM 0x40000000 /* Debug Mode */
#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
* Makefile.in: Delete stuff moved to ../common/Make-common.in. (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. * configure.in: Simplify using macros in ../common/aclocal.m4. * configure: Regenerated. * tconfig.in: New file.
1996-11-20 10:00:42 +00:00
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
static void ColdReset PARAMS((SIM_DESC sd));
* Makefile.in: Delete stuff moved to ../common/Make-common.in. (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. * configure.in: Simplify using macros in ../common/aclocal.m4. * configure: Regenerated. * tconfig.in: New file.
1996-11-20 10:00:42 +00:00
/*---------------------------------------------------------------------------*/
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#define DELAYSLOT() {\
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (STATE & simDELAYSLOT)\
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
STATE |= simDELAYSLOT;\
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
* gencode.c (build_mips16_operands): Fix base PC value for PC relative operands. (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a jal instruction. * interp.c (simJALDELAYSLOT): Define. (JALDELAYSLOT): Define. (INDELAYSLOT, INJALDELAYSLOT): Define. (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1996-12-16 20:01:15 +00:00
#define JALDELAYSLOT() {\
DELAYSLOT ();\
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
STATE |= simJALDELAYSLOT;\
* gencode.c (build_mips16_operands): Fix base PC value for PC relative operands. (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a jal instruction. * interp.c (simJALDELAYSLOT): Define. (JALDELAYSLOT): Define. (INDELAYSLOT, INJALDELAYSLOT): Define. (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1996-12-16 20:01:15 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#define NULLIFY() {\
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
STATE &= ~simDELAYSLOT;\
STATE |= simSKIPNEXT;\
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
#define CANCELDELAYSLOT() {\
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
DSSTATE = 0;\
STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
}
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
* gencode.c (build_mips16_operands): Fix base PC value for PC relative operands. (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a jal instruction. * interp.c (simJALDELAYSLOT): Define. (JALDELAYSLOT): Define. (INDELAYSLOT, INJALDELAYSLOT): Define. (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1996-12-16 20:01:15 +00:00
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
#define K0BASE (0x80000000)
#define K0SIZE (0x20000000)
#define K1BASE (0xA0000000)
#define K1SIZE (0x20000000)
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
#define MONITOR_BASE (0xBFC00000)
#define MONITOR_SIZE (1 << 11)
#define MEM_SIZE (2 << 20)
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
Define CPU_INDEX. Initialize. For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
1998-03-27 04:25:45 +00:00
/* start-sanitize-sky */
#ifdef TARGET_SKY
#undef MEM_SIZE
#define MEM_SIZE (16 << 20) /* 16 MB */
#endif
/* end-sanitize-sky */
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#if defined(TRACE)
* configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set stamp-h. * configure: Rebuild. * config.in: New file, generated by autoheader. * interp.c: Include "config.h". Include <stdlib.h>, <string.h>, and <strings.h> if they exist. Replace #ifdef sun with #ifdef HAVE_ANINT and HAVE_AINT, as appropriate. * Makefile.in (run): Use @LIBS@ rather than -lm. (interp.o): Depend upon config.h. (Makefile): Just rebuild Makefile. (clean): Remove stamp-h. (mostlyclean): Make the same as clean, not as distclean. (config.h, stamp-h): New targets.
1996-06-03 15:58:45 +00:00
static char *tracefile = "trace.din"; /* default filename for trace log */
Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI, MFHI instructions. Trace nullified instruction.
1997-11-11 07:50:13 +00:00
FILE *tracefh = NULL;
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
static void open_trace PARAMS((SIM_DESC sd));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* TRACE */
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
/* simulation target board. NULL=canonical */
static char* board = NULL;
* interp.c (DECLARE_OPTION_HANDLER): Use it. (mips_option_handler): New argument `cpu'. (sim_open): Update call to sim_add_option_table.
1998-02-28 02:43:31 +00:00
static DECLARE_OPTION_HANDLER (mips_option_handler);
* sky-dma.c: Clarify text in warning msg. * interp.c: Add global option "float-type". * sky-vu.h: Add SIM_DESC sd; to VectorUnitState for accessing global options.
1998-03-31 21:46:31 +00:00
enum {
* Updated several files to place all sky specific runtime options in sky-gdb.c. * Added two new runtime options --sky-debug and --screen-refresh * ChangeLog.sky contains a detailed description of the mods
1998-06-10 17:07:09 +00:00
OPTION_DINERO_TRACE = OPTION_START,
OPTION_DINERO_FILE,
OPTION_BOARD
* sky-dma.c: Clarify text in warning msg. * interp.c: Add global option "float-type". * sky-vu.h: Add SIM_DESC sd; to VectorUnitState for accessing global options.
1998-03-31 21:46:31 +00:00
};
Delete -l and -n options, didn't do anything. Rename option trace to dinero-trace & dinero-file - -t clashed with common options. Enable common trace options.
1997-11-05 01:08:12 +00:00
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
Watchpoint interface.
1997-05-21 06:54:13 +00:00
static SIM_RC
* interp.c (DECLARE_OPTION_HANDLER): Use it. (mips_option_handler): New argument `cpu'. (sim_open): Update call to sim_add_option_table.
1998-02-28 02:43:31 +00:00
mips_option_handler (sd, cpu, opt, arg, is_command)
Watchpoint interface.
1997-05-21 06:54:13 +00:00
SIM_DESC sd;
* interp.c (DECLARE_OPTION_HANDLER): Use it. (mips_option_handler): New argument `cpu'. (sim_open): Update call to sim_add_option_table.
1998-02-28 02:43:31 +00:00
sim_cpu *cpu;
Watchpoint interface.
1997-05-21 06:54:13 +00:00
int opt;
char *arg;
* interp.c (DECLARE_OPTION_HANDLER): Use it. (mips_option_handler): New argument `cpu'. (sim_open): Update call to sim_add_option_table.
1998-02-28 02:43:31 +00:00
int is_command;
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
{
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
int cpu_nr;
Watchpoint interface.
1997-05-21 06:54:13 +00:00
switch (opt)
{
Delete -l and -n options, didn't do anything. Rename option trace to dinero-trace & dinero-file - -t clashed with common options. Enable common trace options.
1997-11-05 01:08:12 +00:00
case OPTION_DINERO_TRACE: /* ??? */
Watchpoint interface.
1997-05-21 06:54:13 +00:00
#if defined(TRACE)
/* Eventually the simTRACE flag could be treated as a toggle, to
allow external control of the program points being traced
(i.e. only from main onwards, excluding the run-time setup,
etc.). */
Define CPU_INDEX. Initialize. For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
1998-03-27 04:25:45 +00:00
for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
Watchpoint interface.
1997-05-21 06:54:13 +00:00
{
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
if (arg == NULL)
STATE |= simTRACE;
else if (strcmp (arg, "yes") == 0)
STATE |= simTRACE;
else if (strcmp (arg, "no") == 0)
STATE &= ~simTRACE;
else if (strcmp (arg, "on") == 0)
STATE |= simTRACE;
else if (strcmp (arg, "off") == 0)
STATE &= ~simTRACE;
else
{
* sky-dma.c: Clarify text in warning msg. * interp.c: Add global option "float-type". * sky-vu.h: Add SIM_DESC sd; to VectorUnitState for accessing global options.
1998-03-31 21:46:31 +00:00
fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
return SIM_RC_FAIL;
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
}
return SIM_RC_OK;
#else /* !TRACE */
fprintf(stderr,"\
Delete -l and -n options, didn't do anything. Rename option trace to dinero-trace & dinero-file - -t clashed with common options. Enable common trace options.
1997-11-05 01:08:12 +00:00
Simulator constructed without dinero tracing support (for performance).\n\
Watchpoint interface.
1997-05-21 06:54:13 +00:00
Re-compile simulator with \"-DTRACE\" to enable this option.\n");
return SIM_RC_FAIL;
#endif /* !TRACE */
Delete -l and -n options, didn't do anything. Rename option trace to dinero-trace & dinero-file - -t clashed with common options. Enable common trace options.
1997-11-05 01:08:12 +00:00
case OPTION_DINERO_FILE:
Watchpoint interface.
1997-05-21 06:54:13 +00:00
#if defined(TRACE)
if (optarg != NULL) {
char *tmp;
tmp = (char *)malloc(strlen(optarg) + 1);
if (tmp == NULL)
{
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
Watchpoint interface.
1997-05-21 06:54:13 +00:00
return SIM_RC_FAIL;
}
else {
strcpy(tmp,optarg);
tracefile = tmp;
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
Watchpoint interface.
1997-05-21 06:54:13 +00:00
}
}
#endif /* TRACE */
return SIM_RC_OK;
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
case OPTION_BOARD:
{
if (arg)
{
board = zalloc(strlen(arg) + 1);
strcpy(board, arg);
}
return SIM_RC_OK;
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
}
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
Watchpoint interface.
1997-05-21 06:54:13 +00:00
return SIM_RC_OK;
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
Watchpoint interface.
1997-05-21 06:54:13 +00:00
static const OPTION mips_options[] =
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
{
Delete -l and -n options, didn't do anything. Rename option trace to dinero-trace & dinero-file - -t clashed with common options. Enable common trace options.
1997-11-05 01:08:12 +00:00
{ {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
'\0', "on|off", "Enable dinero tracing",
Watchpoint interface.
1997-05-21 06:54:13 +00:00
mips_option_handler },
Delete -l and -n options, didn't do anything. Rename option trace to dinero-trace & dinero-file - -t clashed with common options. Enable common trace options.
1997-11-05 01:08:12 +00:00
{ {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
'\0', "FILE", "Write dinero trace to FILE",
Watchpoint interface.
1997-05-21 06:54:13 +00:00
mips_option_handler },
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
{ {"board", required_argument, NULL, OPTION_BOARD},
'\0', "none" /* rely on compile-time string concatenation for other options */
/* start-sanitize-tx3904 */
#define BOARD_JMR3904 "jmr3904"
"|" BOARD_JMR3904
* Updates to tx3904 peripheral simulations for ECC. Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE register upon non-zero interrupt event level, clear upon zero event value. * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal by passing zero event value. (*_io_{read,write}_buffer): Endianness fixes. * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. (deliver_*_tick): Reduce sim event interval to 75% of count interval. * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based serial I/O and timer module at base address 0xFFFF0000.
1998-06-09 16:54:09 +00:00
#define BOARD_JMR3904_PAL "jmr3904pal"
"|" BOARD_JMR3904_PAL
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
#define BOARD_JMR3904_DEBUG "jmr3904debug"
"|" BOARD_JMR3904_DEBUG
/* end-sanitize-tx3904 */
, "Customize simulation for a particular board.", mips_option_handler },
Watchpoint interface.
1997-05-21 06:54:13 +00:00
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
};
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
int interrupt_pending;
* Support for sky hardware interrupts. The sky-dma cannot trigger interrupts properly yet (jlemke TODO). Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): For TX39, add stub COP0 register #7, to allay warnings. (interrupt_event): Made non-static. start-sanitize-tx3904 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental interchange of configuration values for external vs. internal clock dividers. end-sanitize-tx3904 start-sanitize-sky * sky-device.c (sky_signal_interrupt): New function to generate interrupt event. * sky-device.h: Declare it. * sky-dma.c (check_int1): Call it. * sky-pke.c (pke_begin_interrupt_stall): Call it. end-sanitize-sky
1998-06-10 17:07:10 +00:00
void
Watchpoint interface.
1997-05-21 06:54:13 +00:00
interrupt_event (SIM_DESC sd, void *data)
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
{
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
address_word cia = CIA_GET (cpu);
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
if (SR & status_IE)
{
interrupt_pending = 0;
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
SignalExceptionInterrupt ();
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
}
else if (!interrupt_pending)
sim_events_schedule (sd, 1, interrupt_event, data);
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
}
Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (xfer_direct_word, xfer_direct_long, swap_direct_word, swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, xfer_little_long, swap_word,swap_long): Added. * interp.c (ColdReset): Provide function indirection to host<->simulated_target transfer routines. * interp.c (sim_store_register, sim_fetch_register): Updated to make use of indirected transfer routines.
1996-05-08 14:22:12 +00:00
* Add hardware_init hook.
1998-02-09 23:53:33 +00:00
/*---------------------------------------------------------------------------*/
/*-- Device registration hook -----------------------------------------------*/
/*---------------------------------------------------------------------------*/
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
static void device_init(SIM_DESC sd) {
* Add hardware_init hook.
1998-02-09 23:53:33 +00:00
#ifdef DEVICE_INIT
extern void register_devices(SIM_DESC);
register_devices(sd);
#endif
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
SIM_DESC
Add ABFD argument to sim_open call. Pass through to sim_config so that image properties such as endianness can be checked. More strongly document the expected behavour of each of the sim_* interfaces. Add default endian argument to simulator config macro SIM_AC_OPTION_ENDIAN. Use in sim_config.
1997-08-25 23:14:25 +00:00
sim_open (kind, cb, abfd, argv)
Cleanups to compile under FreeBSD
1997-04-17 06:05:19 +00:00
SIM_OPEN_KIND kind;
Watchpoint interface.
1997-05-21 06:54:13 +00:00
host_callback *cb;
Add ABFD argument to sim_open call. Pass through to sim_config so that image properties such as endianness can be checked. More strongly document the expected behavour of each of the sim_* interfaces. Add default endian argument to simulator config macro SIM_AC_OPTION_ENDIAN. Use in sim_config.
1997-08-25 23:14:25 +00:00
struct _bfd *abfd;
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
char **argv;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
SIM_DESC sd = sim_state_alloc (kind, cb);
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
configure.in, interp.c: Add configure option --with-sim-funit.
1998-04-21 21:24:24 +00:00
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
Watchpoint interface.
1997-05-21 06:54:13 +00:00
/* FIXME: watchpoints code shouldn't need this */
STATE_WATCHPOINTS (sd)->pc = &(PC);
STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
STATE = 0;
Watchpoint interface.
1997-05-21 06:54:13 +00:00
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
return 0;
* interp.c (DECLARE_OPTION_HANDLER): Use it. (mips_option_handler): New argument `cpu'. (sim_open): Update call to sim_add_option_table.
1998-02-28 02:43:31 +00:00
sim_add_option_table (sd, NULL, mips_options);
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
* Updated several files to place all sky specific runtime options in sky-gdb.c. * Added two new runtime options --sky-debug and --screen-refresh * ChangeLog.sky contains a detailed description of the mods
1998-06-10 17:07:09 +00:00
/* start-sanitize-sky */
#ifdef TARGET_SKY
* interp.c: added call to sky_command_options_end() to close any open file handles before exiting * sky-gpuif.[c|h]: add disassembly on the fly code, log and log file option support * sky-gdb.[c|h] (sky_command_options_close()): new function, added some body to the log and log file option sections
1998-06-12 18:58:26 +00:00
sky_command_options_open (sd);
* Updated several files to place all sky specific runtime options in sky-gdb.c. * Added two new runtime options --sky-debug and --screen-refresh * ChangeLog.sky contains a detailed description of the mods
1998-06-10 17:07:09 +00:00
#endif
/* end-sanitize-sky */
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
print_filtered. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
/* handle board-specific memory maps */
if (board == NULL)
{
/* Allocate core managed memory */
* Move the sanitize comments to the right place.
1998-06-02 21:04:49 +00:00
/* start-sanitize-sky */
* SYSCALL now uses exception vector. * SKY: New memory mapping rules for k1seg, k0seg. * Modified Files: ChangeLog.sky ChangeLog interp.c sim-main.c
1998-06-02 19:53:36 +00:00
#ifndef TARGET_SKY
* Move the sanitize comments to the right place.
1998-06-02 21:04:49 +00:00
/* end-sanitize-sky */
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
/* the monitor */
sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
/* For compatibility with the old code - under this (at level one)
are the kernel spaces K0 & K1. Both of these map to a single
smaller sub region */
sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
K1BASE, K0SIZE,
MEM_SIZE, /* actual size */
K0BASE);
* Move the sanitize comments to the right place.
1998-06-02 21:04:49 +00:00
/* start-sanitize-sky */
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
#else
* SYSCALL now uses exception vector. * SKY: New memory mapping rules for k1seg, k0seg. * Modified Files: ChangeLog.sky ChangeLog interp.c sim-main.c
1998-06-02 19:53:36 +00:00
/* the monitor */
sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE - K1BASE, MONITOR_SIZE);
sim_do_command (sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
/* 16M @ 0x0. Aliases at 0x80000000 and 0xA0000000 are handled by
address_translation() */
sim_do_commandf (sd, "memory size 0x%lx", MEM_SIZE);
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
#endif
* Move the sanitize comments to the right place.
1998-06-02 21:04:49 +00:00
/* end-sanitize-sky */
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
device_init(sd);
}
/* start-sanitize-tx3904 */
* Small TX39-only patch for ECC. Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): For TX39, add stub COP0 register #3, to allay warnings.
1998-06-01 16:29:43 +00:00
#if (WITH_HW)
if (board != NULL
&& (strcmp(board, BOARD_JMR3904) == 0 ||
* Updates to tx3904 peripheral simulations for ECC. Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE register upon non-zero interrupt event level, clear upon zero event value. * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal by passing zero event value. (*_io_{read,write}_buffer): Endianness fixes. * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. (deliver_*_tick): Reduce sim event interval to 75% of count interval. * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based serial I/O and timer module at base address 0xFFFF0000.
1998-06-09 16:54:09 +00:00
strcmp(board, BOARD_JMR3904_PAL) == 0 ||
* Small TX39-only patch for ECC. Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): For TX39, add stub COP0 register #3, to allay warnings.
1998-06-01 16:29:43 +00:00
strcmp(board, BOARD_JMR3904_DEBUG) == 0))
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
{
/* match VIRTUAL memory layout of JMR-TX3904 board */
/* --- memory --- */
/* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x9FC00000,
4 * 1024 * 1024, /* 4 MB */
0xBFC00000);
/* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x80000000,
4 * 1024 * 1024, /* 4 MB */
0xA0000000);
/* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x88000000,
32 * 1024 * 1024, /* 32 MB */
0xA8000000);
/* --- simulated devices --- */
* Early check-in of tx3904 timer sim implementation for ECC. It is not yet properly tested. Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904tmr.c: New file - implements tx3904 timer. * dv-tx3904{irc,cpu}.c: Mild reformatting. * configure.in: Include tx3904tmr in hw_device list. * configure: Rebuilt. * interp.c (sim_open): Instantiate three timer instances. Fix address typo of tx3904irc instance.
1998-06-04 12:43:45 +00:00
sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
sim_hw_parse (sd, "/tx3904cpu");
* Early check-in of tx3904 timer sim implementation for ECC. It is not yet properly tested. Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904tmr.c: New file - implements tx3904 timer. * dv-tx3904{irc,cpu}.c: Mild reformatting. * configure.in: Include tx3904tmr in hw_device list. * configure: Rebuilt. * interp.c (sim_open): Instantiate three timer instances. Fix address typo of tx3904irc instance.
1998-06-04 12:43:45 +00:00
sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
/* -- device connections --- */
sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
* Early check-in of tx3904 timer sim implementation for ECC. It is not yet properly tested. Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904tmr.c: New file - implements tx3904 timer. * dv-tx3904{irc,cpu}.c: Mild reformatting. * configure.in: Include tx3904tmr in hw_device list. * configure: Rebuilt. * interp.c (sim_open): Instantiate three timer instances. Fix address typo of tx3904irc instance.
1998-06-04 12:43:45 +00:00
sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
* Updates to tx3904 peripheral simulations for ECC. Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE register upon non-zero interrupt event level, clear upon zero event value. * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal by passing zero event value. (*_io_{read,write}_buffer): Endianness fixes. * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. (deliver_*_tick): Reduce sim event interval to 75% of count interval. * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based serial I/O and timer module at base address 0xFFFF0000.
1998-06-09 16:54:09 +00:00
/* add PAL timer & I/O module */
if(! strcmp(board, BOARD_JMR3904_PAL))
{
/* the device */
sim_hw_parse (sd, "/pal@0xffff0000");
sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
/* wire up interrupt ports to irc */
sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
}
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
if(! strcmp(board, BOARD_JMR3904_DEBUG))
{
/* -- DEBUG: glue interrupt generators --- */
sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
}
device_init(sd);
}
* Small TX39-only patch for ECC. Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): For TX39, add stub COP0 register #3, to allay warnings.
1998-06-01 16:29:43 +00:00
#endif
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
/* end-sanitize-tx3904 */
Add ABFD argument to sim_create_inferior. Document. Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-08-27 04:44:41 +00:00
/* check for/establish the a reference program image */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL),
abfd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
Add ABFD argument to sim_open call. Pass through to sim_config so that image properties such as endianness can be checked. More strongly document the expected behavour of each of the sim_* interfaces. Add default endian argument to simulator config macro SIM_AC_OPTION_ENDIAN. Use in sim_config.
1997-08-25 23:14:25 +00:00
/* Configure/verify the target byte order and other runtime
configuration options */
Add ABFD argument to sim_create_inferior. Document. Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-08-27 04:44:41 +00:00
if (sim_config (sd) != SIM_RC_OK)
Add ABFD argument to sim_open call. Pass through to sim_config so that image properties such as endianness can be checked. More strongly document the expected behavour of each of the sim_* interfaces. Add default endian argument to simulator config macro SIM_AC_OPTION_ENDIAN. Use in sim_config.
1997-08-25 23:14:25 +00:00
{
sim_module_uninstall (sd);
return 0;
}
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
/* verify assumptions the simulator made about the host type system.
This macro does not return if there is a problem */
IGEN likes to cache the current instruction address (CIA). Change the MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* This is NASTY, in that we are assuming the size of specific
registers: */
{
int rn;
Add support for configuring the size of the floating point unit (fp_word). For mips, move fp_registers into a separate array of type fp_word[].
1998-02-02 14:06:52 +00:00
for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
{
if (rn < 32)
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
else if ((rn >= 33) && (rn <= 37))
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
else if ((rn == SRIDX)
|| (rn == FCR0IDX)
|| (rn == FCR31IDX)
|| ((rn >= 72) && (rn <= 89)))
Add support for configuring the size of the floating point unit (fp_word). For mips, move fp_registers into a separate array of type fp_word[].
1998-02-02 14:06:52 +00:00
cpu->register_widths[rn] = 32;
else
cpu->register_widths[rn] = 0;
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
/* start-sanitize-r5900 */
/* set the 5900 "upper" registers to 64 bits */
for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
cpu->register_widths[rn] = 64;
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
/* end-sanitize-r5900 */
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
/* start-sanitize-sky */
#ifdef TARGET_SKY
/* Now the VU registers */
sim-main.h: track SKY register number changes from gdb interp.c: ditto
1998-03-04 08:47:31 +00:00
for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
cpu->register_widths[rn + NUM_R5900_REGS] = 16;
cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
}
sim-main.h: track SKY register number changes from gdb interp.c: ditto
1998-03-04 08:47:31 +00:00
for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
cpu->register_widths[rn + NUM_R5900_REGS] = 32;
cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
}
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
/* Finally the VIF registers */
for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ )
cpu->register_widths[rn + NUM_R5900_REGS] = 32;
Initial Breakpoint support: * sim-main.h: (struct _sim_cpu): add cur_device field. Define cur_device values, breakpoint value, and SIM_ENGINE_HALT_HOOK * interp.c (sim_open): initialize cur_device * sky-engine.c (engine_run): use cur_device to set current_cpu * sky-libvpe.c (vpecallms_cycle): add check for breakpoint * sky-hardware.h: delete NUMBER_CPUS * sky-hardware.c (attach_devices): create a memory mapped comm area for GDB/SIM interactions misc: * sky-vu.c ({read,write}_vu_misc_reg): do default behavior for unknown regs instead of sim_io_error. MP reg is float (was missing cast).
1998-05-07 14:36:42 +00:00
cpu->cur_device = 0;
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
#endif
/* end-sanitize-sky */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#if defined(TRACE)
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (STATE & simTRACE)
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
open_trace(sd);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* TRACE */
Implement ERET instruction. Add {signed,unsigned}_address type.
1998-04-21 04:30:27 +00:00
/* Write an abort sequence into the TRAP (common) exception vector
addresses. This is to catch code executing a TRAP (et.al.)
instruction without installing a trap handler. */
{
unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
HALT_INSTRUCTION /* BREAK */ };
H2T (halt[0]);
H2T (halt[1]);
sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
}
Add ABFD argument to sim_create_inferior. Document. Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-08-27 04:44:41 +00:00
/* Write the monitor trap address handlers into the monitor (eeprom)
address space. This can only be done once the target endianness
has been determined. */
{
unsigned loop;
/* Entry into the IDT monitor is via fixed address vectors, and
not using machine instructions. To avoid clashing with use of
the MIPS TRAP system, we place our own (simulator specific)
"undefined" instructions into the relevant vector slots. */
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
{
address_word vaddr = (MONITOR_BASE + loop);
unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
H2T (insn);
sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
}
Add ABFD argument to sim_create_inferior. Document. Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-08-27 04:44:41 +00:00
/* The PMON monitor uses the same address space, but rather than
branching into it the address of a routine is loaded. We can
cheat for the moment, and direct the PMON routine to IDT style
instructions within the monitor space. This relies on the IDT
monitor not using the locations from 0xBFC00500 onwards as its
entry points.*/
for (loop = 0; (loop < 24); loop++)
{
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
Add ABFD argument to sim_create_inferior. Document. Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-08-27 04:44:41 +00:00
switch (loop)
{
case 0: /* read */
value = 7;
break;
case 1: /* write */
value = 8;
break;
case 2: /* open */
value = 6;
break;
case 3: /* close */
value = 10;
break;
case 5: /* printf */
value = ((0x500 - 16) / 8); /* not an IDT reason code */
break;
case 8: /* cliexit */
value = 17;
break;
case 11: /* flush_cache */
value = 28;
break;
}
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
/* FIXME - should monitor_base be SIM_ADDR?? */
value = ((unsigned int)MONITOR_BASE + (value * 8));
H2T (value);
sim_write (sd, vaddr, (char *)&value, sizeof (value));
Add ABFD argument to sim_create_inferior. Document. Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-08-27 04:44:41 +00:00
/* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
vaddr -= 0x300;
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
sim_write (sd, vaddr, (char *)&value, sizeof (value));
Add ABFD argument to sim_create_inferior. Document. Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-08-27 04:44:41 +00:00
}
}
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
return sd;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
For NEC 4100/4300 project * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
1996-12-10 19:39:55 +00:00
#if defined(TRACE)
static void
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
open_trace(sd)
SIM_DESC sd;
For NEC 4100/4300 project * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
1996-12-10 19:39:55 +00:00
{
tracefh = fopen(tracefile,"wb+");
if (tracefh == NULL)
{
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
For NEC 4100/4300 project * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
1996-12-10 19:39:55 +00:00
tracefh = stderr;
}
}
#endif /* TRACE */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
void
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
sim_close (sd, quitting)
SIM_DESC sd;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
int quitting;
{
#ifdef DEBUG
printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
#endif
* interp.c: added call to sky_command_options_end() to close any open file handles before exiting * sky-gpuif.[c|h]: add disassembly on the fly code, log and log file option support * sky-gdb.[c|h] (sky_command_options_close()): new function, added some body to the log and log file option sections
1998-06-12 18:58:26 +00:00
/* start-sanitize-sky */
#ifdef TARGET_SKY
sky_command_options_close (sd);
#endif
/* end-sanitize-sky */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* "quitting" is non-zero if we cannot hang on errors */
/* Ensure that any resources allocated through the callback
mechanism are released: */
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_shutdown (sd);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#if defined(TRACE)
* Makefile.in: Delete stuff moved to ../common/Make-common.in. (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. * configure.in: Simplify using macros in ../common/aclocal.m4. * configure: Regenerated. * tconfig.in: New file.
1996-11-20 10:00:42 +00:00
if (tracefh != NULL && tracefh != stderr)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
fclose(tracefh);
* Makefile.in: Delete stuff moved to ../common/Make-common.in. (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. * configure.in: Simplify using macros in ../common/aclocal.m4. * configure: Regenerated. * tconfig.in: New file.
1996-11-20 10:00:42 +00:00
tracefh = NULL;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* TRACE */
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
/* FIXME - free SD */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
return;
}
int
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
sim_write (sd,addr,buffer,size)
SIM_DESC sd;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
SIM_ADDR addr;
unsigned char *buffer;
int size;
{
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
int index;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* Return the number of bytes written, or zero if error. */
#ifdef DEBUG
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
/* We use raw read and write routines, since we do not want to count
the GDB memory accesses in our statistics gathering. */
for (index = 0; index < size; index++)
{
address_word vaddr = (address_word)addr + index;
address_word paddr;
int cca;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
break;
Define CPU_INDEX. Initialize. For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
1998-03-27 04:25:45 +00:00
if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
Rewrite the MIPS simulator's memory model so that it uses the generic common/sim-core. Add support for 3, 5, 6, 7 byte transfers to sim core.
1997-11-05 08:17:26 +00:00
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
return(index);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
int
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
sim_read (sd,addr,buffer,size)
SIM_DESC sd;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
SIM_ADDR addr;
unsigned char *buffer;
int size;
{
int index;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* Return the number of bytes read, or zero if error. */
#ifdef DEBUG
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
for (index = 0; (index < size); index++)
{
address_word vaddr = (address_word)addr + index;
address_word paddr;
int cca;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
break;
Define CPU_INDEX. Initialize. For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
1998-03-27 04:25:45 +00:00
if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
Rewrite the MIPS simulator's memory model so that it uses the generic common/sim-core. Add support for 3, 5, 6, 7 byte transfers to sim core.
1997-11-05 08:17:26 +00:00
break;
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
return(index);
}
* interp.c (load_memory): Add missing "break"'s.
1998-02-19 15:24:10 +00:00
int
sim_store_register (sd,rn,memory,length)
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
SIM_DESC sd;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
int rn;
unsigned char *memory;
* interp.c (load_memory): Add missing "break"'s.
1998-02-19 15:24:10 +00:00
int length;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
Watchpoint interface.
1997-05-21 06:54:13 +00:00
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
/* Unfortunately this suffers from the same problem as the register
numbering one. We need to know what the width of each logical
register number is for the architecture being simulated. */
Watchpoint interface.
1997-05-21 06:54:13 +00:00
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (cpu->register_widths[rn] == 0)
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
{
sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
return 0;
}
/* start-sanitize-r5900 */
if (rn >= 90 && rn < 90 + 32)
{
GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
return 8;
}
switch (rn)
{
case REGISTER_SA:
SA = T2H_8(*(unsigned64*)memory);
return 8;
case 122: /* FIXME */
LO1 = T2H_8(*(unsigned64*)memory);
return 8;
case 123: /* FIXME */
HI1 = T2H_8(*(unsigned64*)memory);
return 8;
}
/* end-sanitize-r5900 */
Make it compile again for -DTARGET_SKY
1998-02-23 23:40:40 +00:00
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
/* start-sanitize-sky */
#ifdef TARGET_SKY
sim-main.h: track SKY register number changes from gdb interp.c: ditto
1998-03-04 08:47:31 +00:00
if (rn >= NUM_R5900_REGS)
Make it compile again for -DTARGET_SKY
1998-02-23 23:40:40 +00:00
{
rn = rn - NUM_R5900_REGS;
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
if( rn < NUM_VU_REGS )
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
{
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
if (rn < NUM_VU_INTEGER_REGS)
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_int_reg (&(vu0_device.regs), rn, memory);
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
else if (rn >= FIRST_VEC_REG)
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
{
rn -= FIRST_VEC_REG;
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3,
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
memory);
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_special_reg (&vu0_device, VU_REG_CIA,
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
memory);
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
case 1:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
memory);
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
case 2: /* VU0 has no P register */
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
return 4;
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
case 3:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
memory);
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
case 4:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
memory);
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
default:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_acc_reg (&(vu0_device.regs),
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
}
Make it compile again for -DTARGET_SKY
1998-02-23 23:40:40 +00:00
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
rn = rn - NUM_VU_REGS;
if (rn < NUM_VU_REGS)
{
if (rn < NUM_VU_INTEGER_REGS)
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_int_reg (&(vu1_device.regs), rn, memory);
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
else if (rn >= FIRST_VEC_REG)
{
rn -= FIRST_VEC_REG;
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_vec_reg (&(vu1_device.regs),
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
rn >> 2, rn & 3, memory);
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_special_reg (&vu1_device, VU_REG_CIA,
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
memory);
case 1:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR,
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
memory);
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
case 2:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP,
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
memory);
case 3:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI,
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
memory);
case 4:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ,
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
memory);
default:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return write_vu_acc_reg (&(vu1_device.regs),
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
}
sim-main.h: track SKY register number changes from gdb interp.c: ditto
1998-03-04 08:47:31 +00:00
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
rn -= NUM_VU_REGS; /* VIF0 registers are next */
if (rn < NUM_VIF_REGS)
{
if (rn < NUM_VIF_REGS-1)
return write_pke_reg (&pke0_device, rn, memory);
else
{
sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" );
return 0;
}
}
rn -= NUM_VIF_REGS; /* VIF1 registers are last */
if (rn < NUM_VIF_REGS)
{
if (rn < NUM_VIF_REGS-1)
return write_pke_reg (&pke1_device, rn, memory);
else
{
sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" );
return 0;
}
}
sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
return 0;
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
}
#endif
/* end-sanitize-sky */
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
Add support for configuring the size of the floating point unit (fp_word). For mips, move fp_registers into a separate array of type fp_word[].
1998-02-02 14:06:52 +00:00
{
if (cpu->register_widths[rn] == 32)
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
{
cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
return 4;
}
Add support for configuring the size of the floating point unit (fp_word). For mips, move fp_registers into a separate array of type fp_word[].
1998-02-02 14:06:52 +00:00
else
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
{
cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
return 8;
}
Add support for configuring the size of the floating point unit (fp_word). For mips, move fp_registers into a separate array of type fp_word[].
1998-02-02 14:06:52 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
if (cpu->register_widths[rn] == 32)
{
cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
return 4;
}
else
{
cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
return 8;
}
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
return 0;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
* interp.c (load_memory): Add missing "break"'s.
1998-02-19 15:24:10 +00:00
int
sim_fetch_register (sd,rn,memory,length)
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
SIM_DESC sd;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
int rn;
unsigned char *memory;
* interp.c (load_memory): Add missing "break"'s.
1998-02-19 15:24:10 +00:00
int length;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
Watchpoint interface.
1997-05-21 06:54:13 +00:00
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (cpu->register_widths[rn] == 0)
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
{
sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
return 0;
}
/* start-sanitize-r5900 */
if (rn >= 90 && rn < 90 + 32)
{
* interp.c (sim_fetch_register): Convert internal r5900 regs to target byte order
1998-05-21 08:18:21 +00:00
*((unsigned64*)memory) = H2T_8 (GPR1[rn - 90]);
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
return 8;
}
switch (rn)
{
case REGISTER_SA:
*((unsigned64*)memory) = H2T_8(SA);
return 8;
case 122: /* FIXME */
*((unsigned64*)memory) = H2T_8(LO1);
return 8;
case 123: /* FIXME */
*((unsigned64*)memory) = H2T_8(HI1);
return 8;
}
/* end-sanitize-r5900 */
Make it compile again for -DTARGET_SKY
1998-02-23 23:40:40 +00:00
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
/* start-sanitize-sky */
#ifdef TARGET_SKY
sim-main.h: track SKY register number changes from gdb interp.c: ditto
1998-03-04 08:47:31 +00:00
if (rn >= NUM_R5900_REGS)
Make it compile again for -DTARGET_SKY
1998-02-23 23:40:40 +00:00
{
rn = rn - NUM_R5900_REGS;
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
if (rn < NUM_VU_REGS)
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
{
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
if (rn < NUM_VU_INTEGER_REGS)
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_int_reg (&(vu0_device.regs), rn, memory);
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
else if (rn >= FIRST_VEC_REG)
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
{
rn -= FIRST_VEC_REG;
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3,
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
memory);
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_special_reg(&vu0_device, VU_REG_CIA, memory);
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
case 1:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
memory);
case 2: /* VU0 has no P register */
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
*((int *) memory) = 0;
return 4;
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
case 3:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
memory);
case 4:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
memory);
default:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_acc_reg (&(vu0_device.regs),
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
}
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
rn -= NUM_VU_REGS; /* VU1 registers are next */
if (rn < NUM_VU_REGS)
sim-main.h: track SKY register number changes from gdb interp.c: ditto
1998-03-04 08:47:31 +00:00
{
if (rn < NUM_VU_INTEGER_REGS)
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_int_reg (&(vu1_device.regs), rn, memory);
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
else if (rn >= FIRST_VEC_REG)
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
{
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
rn -= FIRST_VEC_REG;
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_vec_reg (&(vu1_device.regs),
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
rn >> 2, rn & 3, memory);
sky-vu.[ch]: prototype decls, cast floats to ints before register transfer interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
}
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_special_reg(&vu1_device, VU_REG_CIA, memory);
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
case 1:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_misc_reg (&(vu1_device.regs),
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
VU_REG_MR, memory);
case 2:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_misc_reg (&(vu1_device.regs),
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
VU_REG_MP, memory);
case 3:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_misc_reg (&(vu1_device.regs),
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
VU_REG_MI, memory);
case 4:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_misc_reg (&(vu1_device.regs),
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
VU_REG_MQ, memory);
default:
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
return read_vu_acc_reg (&(vu1_device.regs),
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
}
rn -= NUM_VU_REGS; /* VIF0 registers are next */
if (rn < NUM_VIF_REGS)
{
if (rn < NUM_VIF_REGS-1)
return read_pke_reg (&pke0_device, rn, memory);
sim-main.h: track SKY register number changes from gdb interp.c: ditto
1998-03-04 08:47:31 +00:00
else
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
return read_pke_pc (&pke0_device, memory);
sim-main.h: track SKY register number changes from gdb interp.c: ditto
1998-03-04 08:47:31 +00:00
}
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
rn -= NUM_VIF_REGS; /* VIF1 registers are last */
if (rn < NUM_VIF_REGS)
{
if (rn < NUM_VIF_REGS-1)
return read_pke_reg (&pke1_device, rn, memory);
else
return read_pke_pc (&pke1_device, memory);
}
sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure. sim-main.h: Define regs for sky if -DTARGET_SKY interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
}
#endif
/* end-sanitize-sky */
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
/* Any floating point register */
if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
Add support for configuring the size of the floating point unit (fp_word). For mips, move fp_registers into a separate array of type fp_word[].
1998-02-02 14:06:52 +00:00
{
if (cpu->register_widths[rn] == 32)
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
{
*(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
return 4;
}
Add support for configuring the size of the floating point unit (fp_word). For mips, move fp_registers into a separate array of type fp_word[].
1998-02-02 14:06:52 +00:00
else
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
{
*(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
return 8;
}
Add support for configuring the size of the floating point unit (fp_word). For mips, move fp_registers into a separate array of type fp_word[].
1998-02-02 14:06:52 +00:00
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
if (cpu->register_widths[rn] == 32)
{
*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
return 4;
}
else
{
*(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
return 8;
}
aclocal.m4: Don't enable inlining when cross-compiling. mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
return 0;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
* Makefile.in (SIM_OBJS): Add sim-load.o. * interp.c: #include bfd.h. (target_byte_order): Delete. (sim_kind, myname, big_endian_p): New static locals. (sim_open): Set sim_kind, myname. Move call to set_endianness to after argument parsing. Recognize -E arg, set endianness accordingly. (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to load file into simulator. Set PC from bfd. (sim_create_inferior): Return SIM_RC. Delete arg start_address. (set_endianness): Use big_endian_p instead of target_byte_order.
1997-04-17 10:23:48 +00:00
SIM_RC
Add ABFD argument to sim_create_inferior. Document. Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-08-27 04:44:41 +00:00
sim_create_inferior (sd, abfd, argv,env)
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
SIM_DESC sd;
Add ABFD argument to sim_create_inferior. Document. Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-08-27 04:44:41 +00:00
struct _bfd *abfd;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
char **argv;
char **env;
{
Watchpoint interface.
1997-05-21 06:54:13 +00:00
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* Makefile.in (SIM_OBJS): Add sim-load.o. * interp.c: #include bfd.h. (target_byte_order): Delete. (sim_kind, myname, big_endian_p): New static locals. (sim_open): Set sim_kind, myname. Move call to set_endianness to after argument parsing. Recognize -E arg, set endianness accordingly. (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to load file into simulator. Set PC from bfd. (sim_create_inferior): Return SIM_RC. Delete arg start_address. (set_endianness): Use big_endian_p instead of target_byte_order.
1997-04-17 10:23:48 +00:00
printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
pr_addr(PC));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
ColdReset(sd);
Watchpoint interface.
1997-05-21 06:54:13 +00:00
Add ABFD argument to sim_create_inferior. Document. Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-08-27 04:44:41 +00:00
if (abfd != NULL)
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
{
/* override PC value set by ColdReset () */
int cpu_nr;
for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
{
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
}
}
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#if 0 /* def DEBUG */
Add function to fetch 32bit instructions When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
if (argv || env)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
Add function to fetch 32bit instructions When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
/* We should really place the argv slot values into the argument
registers, and onto the stack as required. However, this
assumes that we have a stack defined, which is not
necessarily true at the moment. */
char **cptr;
sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
for (cptr = argv; (cptr && *cptr); cptr++)
printf("DBG: arg \"%s\"\n",*cptr);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#endif /* DEBUG */
* Makefile.in (SIM_OBJS): Add sim-load.o. * interp.c: #include bfd.h. (target_byte_order): Delete. (sim_kind, myname, big_endian_p): New static locals. (sim_open): Set sim_kind, myname. Move call to set_endianness to after argument parsing. Recognize -E arg, set endianness accordingly. (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to load file into simulator. Set PC from bfd. (sim_create_inferior): Return SIM_RC. Delete arg start_address. (set_endianness): Use big_endian_p instead of target_byte_order.
1997-04-17 10:23:48 +00:00
return SIM_RC_OK;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
void
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
sim_do_command (sd,cmd)
SIM_DESC sd;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
char *cmd;
{
Rewrite the MIPS simulator's memory model so that it uses the generic common/sim-core. Add support for 3, 5, 6, 7 byte transfers to sim core.
1997-11-05 08:17:26 +00:00
if (sim_args_command (sd, cmd) != SIM_RC_OK)
sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
cmd);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
/*---------------------------------------------------------------------------*/
/*-- Private simulator support interface ------------------------------------*/
/*---------------------------------------------------------------------------*/
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
/* Read a null terminated string from memory, return in a buffer */
static char *
fetch_str (sd, addr)
SIM_DESC sd;
address_word addr;
{
char *buf;
int nr = 0;
char null;
while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
nr++;
buf = NZALLOC (char, nr + 1);
sim_read (sd, addr, buf, nr);
return buf;
}
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
static void
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_monitor (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
unsigned int reason)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
#ifdef DEBUG
printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
#endif /* DEBUG */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* The IDT monitor actually allows two instructions per vector
slot. However, the simulator currently causes a trap on each
individual instruction. We cheat, and lose the bottom bit. */
reason >>= 1;
/* The following callback functions are available, however the
monitor we are simulating does not make use of them: get_errno,
isatty, lseek, rename, system, time and unlink */
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
switch (reason)
{
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case 6: /* int open(char *path,int flags) */
{
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
char *path = fetch_str (sd, A0);
V0 = sim_io_open (sd, path, (int)A1);
zfree (path);
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
case 7: /* int read(int file,char *ptr,int len) */
{
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
int fd = A0;
int nr = A2;
char *buf = zalloc (nr);
V0 = sim_io_read (sd, fd, buf, nr);
sim_write (sd, A1, buf, nr);
zfree (buf);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
break;
case 8: /* int write(int file,char *ptr,int len) */
{
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
int fd = A0;
int nr = A2;
char *buf = zalloc (nr);
sim_read (sd, A1, buf, nr);
V0 = sim_io_write (sd, fd, buf, nr);
zfree (buf);
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
case 10: /* int close(int file) */
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
{
V0 = sim_io_close (sd, (int)A0);
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
* interp.c (sim_monitor): Handle Densan monitor outbyte and inbyte functions.
1998-01-05 23:43:30 +00:00
case 2: /* Densan monitor: char inbyte(int waitflag) */
{
if (A0 == 0) /* waitflag == NOWAIT */
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
V0 = (unsigned_word)-1;
* interp.c (sim_monitor): Handle Densan monitor outbyte and inbyte functions.
1998-01-05 23:43:30 +00:00
}
/* Drop through to case 11 */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case 11: /* char inbyte(void) */
{
char tmp;
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
{
sim_io_error(sd,"Invalid return from character read");
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
V0 = (unsigned_word)-1;
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
else
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
V0 = (unsigned_word)tmp;
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
* interp.c (sim_monitor): Handle Densan monitor outbyte and inbyte functions.
1998-01-05 23:43:30 +00:00
case 3: /* Densan monitor: void co(char chr) */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case 12: /* void outbyte(char chr) : write a byte to "stdout" */
{
char tmp = (char)(A0 & 0xFF);
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
sim_io_write_stdout (sd, &tmp, sizeof(char));
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
case 17: /* void _exit() */
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
{
sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
(unsigned int)(A0 & 0xFFFFFFFF));
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
add flush_cache PMON routine
1996-12-25 06:14:26 +00:00
case 28 : /* PMON flush_cache */
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case 55: /* void get_mem_info(unsigned int *ptr) */
/* in: A0 = pointer to three word memory location */
/* out: [A0 + 0] = size */
/* [A0 + 4] = instruction cache size */
/* [A0 + 8] = data cache size */
{
For mips get_mem_size call. Force the return of a 32 bit value regardless of the target's word bitsize.
1998-04-02 03:27:24 +00:00
unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
unsigned_4 zero = 0;
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
H2T (value);
For mips get_mem_size call. Force the return of a 32 bit value regardless of the target's word bitsize.
1998-04-02 03:27:24 +00:00
sim_write (sd, A0 + 0, (char *)&value, 4);
sim_write (sd, A0 + 4, (char *)&zero, 4);
sim_write (sd, A0 + 8, (char *)&zero, 4);
Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI, MFHI instructions. Trace nullified instruction.
1997-11-11 07:50:13 +00:00
/* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
case 158 : /* PMON printf */
/* in: A0 = pointer to format string */
/* A1 = optional argument 1 */
/* A2 = optional argument 2 */
/* A3 = optional argument 3 */
/* out: void */
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
/* The following is based on the PMON printf source */
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
{
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
address_word s = A0;
char c;
signed_word *ap = &A1; /* 1st argument */
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
/* This isn't the quickest way, since we call the host print
routine for every character almost. But it does avoid
having to allocate and manage a temporary string buffer. */
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
/* TODO: Include check that we only use three arguments (A1,
A2 and A3) */
while (sim_read (sd, s++, &c, 1) && c != '\0')
{
if (c == '%')
{
char tmp[40];
enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
int width = 0, trunc = 0, haddot = 0, longlong = 0;
while (sim_read (sd, s++, &c, 1) && c != '\0')
{
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
if (strchr ("dobxXulscefg%", c))
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
break;
else if (c == '-')
fmt = FMT_LJUST;
else if (c == '0')
fmt = FMT_RJUST0;
else if (c == '~')
fmt = FMT_CENTER;
else if (c == '*')
{
if (haddot)
trunc = (int)*ap++;
else
width = (int)*ap++;
}
else if (c >= '1' && c <= '9')
{
address_word t = s;
unsigned int n;
while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
tmp[s - t] = c;
tmp[s - t] = '\0';
n = (unsigned int)strtol(tmp,NULL,10);
if (haddot)
trunc = n;
else
width = n;
s--;
}
else if (c == '.')
haddot = 1;
}
switch (c)
{
case '%':
sim_io_printf (sd, "%%");
break;
case 's':
if ((int)*ap != 0)
{
address_word p = *ap++;
char ch;
while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
sim_io_printf(sd, "%c", ch);
}
else
sim_io_printf(sd,"(null)");
break;
case 'c':
sim_io_printf (sd, "%c", (int)*ap++);
break;
default:
if (c == 'l')
{
sim_read (sd, s++, &c, 1);
if (c == 'l')
{
longlong = 1;
sim_read (sd, s++, &c, 1);
}
}
if (strchr ("dobxXu", c))
{
word64 lv = (word64) *ap++;
if (c == 'b')
sim_io_printf(sd,"<binary not supported>");
else
{
sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
if (longlong)
sim_io_printf(sd, tmp, lv);
else
sim_io_printf(sd, tmp, (int)lv);
}
}
else if (strchr ("eEfgG", c))
{
double dbl = *(double*)(ap++);
sprintf (tmp, "%%%d.%d%c", width, trunc, c);
sim_io_printf (sd, tmp, dbl);
trunc = 0;
}
}
}
else
sim_io_printf(sd, "%c", c);
}
break;
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
default:
Rewrite sim_monitor (implements read, write, open, et.al. system calls) and sim_open so that they uses the virtual memory data transfer functions sim_read & sim_write. This eliminates all code (other than in load_memory & store_memory) that makes assumptions about the implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
reason, pr_addr(cia));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
break;
}
return;
}
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
/* Store a word into memory. */
static void
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
store_word (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
uword64 vaddr,
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
signed_word val)
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
{
Add function to fetch 32bit instructions When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
address_word paddr;
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
int uncached;
if ((vaddr & 3) != 0)
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
SignalExceptionAddressStore ();
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
else
{
if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
isTARGET, isREAL))
{
const uword64 mask = 7;
uword64 memval;
unsigned int byte;
paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
byte = (vaddr & mask) ^ (BigEndianCPU << 2);
memval = ((uword64) val) << (8 * byte);
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
isREAL);
}
}
}
/* Load a word from memory. */
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
static signed_word
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
load_word (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
uword64 vaddr)
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
{
if ((vaddr & 3) != 0)
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
SignalExceptionAddressLoad ();
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
else
{
Add function to fetch 32bit instructions When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
address_word paddr;
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
int uncached;
if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
isTARGET, isREAL))
{
const uword64 mask = 0x7;
const unsigned int reverse = ReverseEndian ? 1 : 0;
const unsigned int bigend = BigEndianCPU ? 1 : 0;
uword64 memval;
unsigned int byte;
paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
isDATA, isREAL);
byte = (vaddr & mask) ^ (bigend << 2);
return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
}
}
return 0;
}
/* Simulate the mips16 entry and exit pseudo-instructions. These
would normally be handled by the reserved instruction exception
code, but for ease of simulation we just handle them directly. */
static void
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
mips16_entry (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
unsigned int insn)
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
{
int aregs, sregs, rreg;
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
#ifdef DEBUG
printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
#endif /* DEBUG */
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
aregs = (insn & 0x700) >> 8;
sregs = (insn & 0x0c0) >> 6;
rreg = (insn & 0x020) >> 5;
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
/* This should be checked by the caller. */
if (sregs == 3)
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
abort ();
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
if (aregs < 5)
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
{
int i;
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
signed_word tsp;
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
/* This is the entry pseudo-instruction. */
for (i = 0; i < aregs; i++)
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
tsp = SP;
SP -= 32;
if (rreg)
{
tsp -= 4;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
store_word (SD, CPU, cia, (uword64) tsp, RA);
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
}
for (i = 0; i < sregs; i++)
{
tsp -= 4;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
}
}
else
{
int i;
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
signed_word tsp;
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
/* This is the exit pseudo-instruction. */
tsp = SP + 32;
if (rreg)
{
tsp -= 4;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
RA = load_word (SD, CPU, cia, (uword64) tsp);
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
}
for (i = 0; i < sregs; i++)
{
tsp -= 4;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
}
SP += 32;
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
{
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
if (aregs == 5)
{
FGR[0] = WORD64LO (GPR[4]);
FPR_STATE[0] = fmt_uninterpreted;
}
else if (aregs == 6)
{
FGR[0] = WORD64LO (GPR[5]);
FGR[1] = WORD64LO (GPR[4]);
FPR_STATE[0] = fmt_uninterpreted;
FPR_STATE[1] = fmt_uninterpreted;
}
}
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
PC = RA;
}
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/*-- trace support ----------------------------------------------------------*/
/* The TRACE support is provided (if required) in the memory accessing
routines. Since we are also providing the architecture specific
features, the architecture simulation code can also deal with
notifying the TRACE world of cache flushes, etc. Similarly we do
not need to provide profiling support in the simulator engine,
since we can sample in the instruction fetch control loop. By
defining the TRACE manifest, we add tracing as a run-time
option. */
#if defined(TRACE)
/* Tracing by default produces "din" format (as required by
dineroIII). Each line of such a trace file *MUST* have a din label
and address field. The rest of the line is ignored, so comments can
be included if desired. The first field is the label which must be
one of the following values:
0 read data
1 write data
2 instruction fetch
3 escape record (treated as unknown access type)
4 escape record (causes cache flush)
The address field is a 32bit (lower-case) hexadecimal address
value. The address should *NOT* be preceded by "0x".
The size of the memory transfer is not important when dealing with
cache lines (as long as no more than a cache line can be
transferred in a single operation :-), however more information
could be given following the dineroIII requirement to allow more
complete memory and cache simulators to provide better
results. i.e. the University of Pisa has a cache simulator that can
also take bus size and speed as (variable) inputs to calculate
complete system performance (a much more useful ability when trying
to construct an end product, rather than a processor). They
currently have an ARM version of their tool called ChARM. */
* Makefile.in: Delete stuff moved to ../common/Make-common.in. (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. * configure.in: Simplify using macros in ../common/aclocal.m4. * configure: Regenerated. * tconfig.in: New file.
1996-11-20 10:00:42 +00:00
Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI, MFHI instructions. Trace nullified instruction.
1997-11-11 07:50:13 +00:00
void
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
dotrace (SIM_DESC sd,
sim_cpu *cpu,
FILE *tracefh,
int type,
SIM_ADDR address,
int width,
char *comment,...)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (STATE & simTRACE) {
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
va_list ap;
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
fprintf(tracefh,"%d %s ; width %d ; ",
For NEC 4100/4300 project * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
1996-12-10 19:39:55 +00:00
type,
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
pr_addr(address),
width);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
va_start(ap,comment);
For NEC 4100/4300 project * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
1996-12-10 19:39:55 +00:00
vfprintf(tracefh,comment,ap);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
va_end(ap);
fprintf(tracefh,"\n");
}
/* NOTE: Since the "din" format will only accept 32bit addresses, and
we may be generating 64bit ones, we should put the hi-32bits of the
address into the comment field. */
/* TODO: Provide a buffer for the trace lines. We can then avoid
performing writes until the buffer is filled, or the file is
being closed. */
/* NOTE: We could consider adding a comment field to the "din" file
produced using type 3 markers (unknown access). This would then
allow information about the program that the "din" is for, and
the MIPs world that was being simulated, to be placed into the
trace file. */
return;
}
#endif /* TRACE */
/*---------------------------------------------------------------------------*/
/*-- simulator engine -------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
static void
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
ColdReset (SIM_DESC sd)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
int cpu_nr;
for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
Add function to fetch 32bit instructions When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
{
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
/* RESET: Fixed PC address: */
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
/* The reset vector address is in the unmapped, uncached memory space. */
SR &= ~(status_SR | status_TS | status_RP);
SR |= (status_ERL | status_BEV);
/* Cheat and allow access to the complete register set immediately */
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
&& WITH_TARGET_WORD_BITSIZE == 64)
SR |= status_FR; /* 64bit registers */
/* Ensure that any instructions with pending register updates are
cleared: */
Rewrite the mipsI/II/III pending-slot code.
1998-02-02 13:49:17 +00:00
PENDING_INVALIDATE();
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
/* Initialise the FPU registers to the unknown state */
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
int rn;
for (rn = 0; (rn < 32); rn++)
FPR_STATE[rn] = fmt_uninterpreted;
}
Add function to fetch 32bit instructions When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* Signal an exception condition. This will result in an exception
that aborts the instruction. The instruction operation pseudocode
Watchpoint interface.
1997-05-21 06:54:13 +00:00
will never see a return from this function call. */
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
void
IGEN likes to cache the current instruction address (CIA). Change the MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
signal_exception (SIM_DESC sd,
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_cpu *cpu,
IGEN likes to cache the current instruction address (CIA). Change the MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
address_word cia,
int exception,...)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
* Small TX39-only patch for ECC. Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): For TX39, add stub COP0 register #3, to allay warnings.
1998-06-01 16:29:43 +00:00
/* int vector; */
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
#ifdef DEBUG
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
#endif /* DEBUG */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* Ensure that any active atomic read/modify/write operation will fail: */
LLBIT = 0;
switch (exception) {
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
case DebugBreakPoint :
if (! (Debug & Debug_DM))
{
if (INDELAYSLOT())
{
CANCELDELAYSLOT();
Debug |= Debug_DBD; /* signaled from within in delay slot */
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
DEPC = cia - 4; /* reference the branch instruction */
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
}
else
{
Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
DEPC = cia;
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
}
Debug |= Debug_DM; /* in debugging mode */
Debug |= Debug_DBp; /* raising a DBp exception */
PC = 0xBFC00200;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_engine_restart (SD, CPU, NULL, NULL_CIA);
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
}
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case ReservedInstruction :
{
va_list ap;
unsigned int instruction;
va_start(ap,exception);
instruction = va_arg(ap,unsigned int);
va_end(ap);
/* Provide simple monitor support using ReservedInstruction
exceptions. The following code simulates the fixed vector
entry points into the IDT monitor by causing a simulator
trap, performing the monitor operation, and returning to
the address held in the $ra register (standard PCS return
address). This means we only need to pre-load the vector
space with suitable instruction values. For systems were
actual trap instructions are used, we would not need to
perform this magic. */
IGEN likes to cache the current instruction address (CIA). Change the MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
{
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
IGEN likes to cache the current instruction address (CIA). Change the MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
/* NOTE: This assumes that a branch-and-link style
instruction was used to enter the vector (which is the
case with the current IDT monitor). */
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_engine_restart (SD, CPU, NULL, RA);
IGEN likes to cache the current instruction address (CIA). Change the MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
}
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
/* Look for the mips16 entry and exit instructions, and
simulate a handler for them. */
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
else if ((cia & 1) != 0
* interp.c (store_word, load_word): New static functions. (mips16_entry): New static function. (SignalException): Look for mips16 entry and exit instructions. (simulate): Use the correct index when setting fpr_state after doing a pending move.
1996-12-30 22:37:30 +00:00
&& (instruction & 0xf81f) == 0xe809
IGEN likes to cache the current instruction address (CIA). Change the MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
&& (instruction & 0x0c0) != 0x0c0)
{
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
mips16_entry (SD, CPU, cia, instruction);
IGEN likes to cache the current instruction address (CIA). Change the MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
sim_engine_restart (sd, NULL, NULL, NULL_CIA);
}
/* else fall through to normal exception processing */
Debug tx19 built from igen sources. Rework ifetch{16,32} to match the more recent do_load function.
1998-04-15 07:23:28 +00:00
sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
* interp.c (sim_engine_run): Reset the ZERO register to zero regardless of FEATURE_WARN_ZERO.
1997-07-02 18:13:00 +00:00
default:
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* Store exception code into current exception id variable (used
by exit code): */
/* TODO: If not simulating exceptions then stop the simulator
execution. At the moment we always stop the simulation. */
* Makefile.in: Delete stuff moved to ../common/Make-common.in. (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. * configure.in: Simplify using macros in ../common/aclocal.m4. * configure: Regenerated. * tconfig.in: New file.
1996-11-20 10:00:42 +00:00
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
#ifdef SUBTARGET_R3900
/* update interrupt-related registers */
/* insert exception code in bits 6:2 */
CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
/* shift IE/KU history bits left */
SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
if (STATE & simDELAYSLOT)
{
STATE &= ~simDELAYSLOT;
CAUSE |= cause_BD;
EPC = (cia - 4); /* reference the branch instruction */
}
else
EPC = cia;
if (SR & status_BEV)
PC = (signed)0xBFC00000 + 0x180;
else
PC = (signed)0x80000000 + 0x080;
#else
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
/* See figure 5-17 for an outline of the code below */
if (! (SR & status_EXL))
{
CAUSE = (exception << 2);
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (STATE & simDELAYSLOT)
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
{
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
STATE &= ~simDELAYSLOT;
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
CAUSE |= cause_BD;
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
EPC = (cia - 4); /* reference the branch instruction */
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
}
else
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
EPC = cia;
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
/* FIXME: TLB et.al. */
* Small TX39-only patch for ECC. Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): For TX39, add stub COP0 register #3, to allay warnings.
1998-06-01 16:29:43 +00:00
/* vector = 0x180; */
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
}
else
{
* interp.c (sim_engine_run): Reset the ZERO register to zero regardless of FEATURE_WARN_ZERO.
1997-07-02 18:13:00 +00:00
CAUSE = (exception << 2);
* Small TX39-only patch for ECC. Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): For TX39, add stub COP0 register #3, to allay warnings.
1998-06-01 16:29:43 +00:00
/* vector = 0x180; */
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
}
SR |= status_EXL;
* Makefile.in: Delete stuff moved to ../common/Make-common.in. (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. * configure.in: Simplify using macros in ../common/aclocal.m4. * configure: Regenerated. * tconfig.in: New file.
1996-11-20 10:00:42 +00:00
/* Store exception code into current exception id variable (used
by exit code): */
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
if (SR & status_BEV)
PC = (signed)0xBFC00200 + 0x180;
else
PC = (signed)0x80000000 + 0x180;
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
#endif
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
Watchpoint interface.
1997-05-21 06:54:13 +00:00
switch ((CAUSE >> 2) & 0x1F)
{
case Interrupt:
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
/* Interrupts arrive during event processing, no need to
restart */
return;
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
case NMIReset:
/* Ditto */
#ifdef SUBTARGET_3900
/* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
PC = (signed)0xBFC00000;
#endif SUBTARGET_3900
return;
Watchpoint interface.
1997-05-21 06:54:13 +00:00
case TLBModification:
case TLBLoad:
case TLBStore:
case AddressLoad:
case AddressStore:
case InstructionFetch:
case DataReference:
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
/* The following is so that the simulator will continue from the
exception address on breakpoint operations. */
PC = EPC;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
o Add SIM_SIGFPE to sim-signals o Start SIM_SIG* at 64 so that the use of host signal numbers can be detected and reported. o Update MIPS simulator to use sim-signal.
1997-11-20 09:50:36 +00:00
sim_stopped, SIM_SIGBUS);
Watchpoint interface.
1997-05-21 06:54:13 +00:00
case ReservedInstruction:
case CoProcessorUnusable:
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
PC = EPC;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
o Add SIM_SIGFPE to sim-signals o Start SIM_SIG* at 64 so that the use of host signal numbers can be detected and reported. o Update MIPS simulator to use sim-signal.
1997-11-20 09:50:36 +00:00
sim_stopped, SIM_SIGILL);
Watchpoint interface.
1997-05-21 06:54:13 +00:00
case IntegerOverflow:
case FPE:
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
o Add SIM_SIGFPE to sim-signals o Start SIM_SIG* at 64 so that the use of host signal numbers can be detected and reported. o Update MIPS simulator to use sim-signal.
1997-11-20 09:50:36 +00:00
sim_stopped, SIM_SIGFPE);
Watchpoint interface.
1997-05-21 06:54:13 +00:00
* Handle 10 and 20-bit versions of Break instruction. Move handling * of special values from signal_exception() in interp.c into mips.igen. * * Modified: gencode.c interp.c mips.igen sim-main.h
1998-06-09 16:54:08 +00:00
case BreakPoint:
* SYSCALL now uses exception vector. * SKY: New memory mapping rules for k1seg, k0seg. * Modified Files: ChangeLog.sky ChangeLog interp.c sim-main.c
1998-06-02 19:53:36 +00:00
case SystemCall:
Watchpoint interface.
1997-05-21 06:54:13 +00:00
case Trap:
Implement ERET instruction. Add {signed,unsigned}_address type.
1998-04-21 04:30:27 +00:00
sim_engine_restart (SD, CPU, NULL, PC);
break;
Watchpoint interface.
1997-05-21 06:54:13 +00:00
case Watch:
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
PC = EPC;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
o Add SIM_SIGFPE to sim-signals o Start SIM_SIG* at 64 so that the use of host signal numbers can be detected and reported. o Update MIPS simulator to use sim-signal.
1997-11-20 09:50:36 +00:00
sim_stopped, SIM_SIGTRAP);
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default : /* Unknown internal exception */
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
PC = EPC;
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_engine_halt (SD, CPU, NULL, NULL_CIA,
o Add SIM_SIGFPE to sim-signals o Start SIM_SIG* at 64 so that the use of host signal numbers can be detected and reported. o Update MIPS simulator to use sim-signal.
1997-11-20 09:50:36 +00:00
sim_stopped, SIM_SIGABRT);
Watchpoint interface.
1997-05-21 06:54:13 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case SimulatorFault:
{
va_list ap;
char *msg;
va_start(ap,exception);
msg = va_arg(ap,char *);
Watchpoint interface.
1997-05-21 06:54:13 +00:00
va_end(ap);
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_engine_abort (SD, CPU, NULL_CIA,
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
"FATAL: Simulator error \"%s\"\n",msg);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
}
return;
}
#if defined(WARN_RESULT)
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* This function indicates that the result of the operation is
undefined. However, this should not affect the instruction
stream. All that is meant to happen is that the destination
register is set to an undefined result. To keep the simulator
simple, we just don't bother updating the destination register, so
the overall result will be undefined. If desired we can stop the
simulator by raising a pseudo-exception. */
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
#define UndefinedResult() undefined_result (sd,cia)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
static void
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
undefined_result(sd,cia)
SIM_DESC sd;
address_word cia;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
state |= simSTOP;
#endif
return;
}
#endif /* WARN_RESULT */
/*-- FPU support routines ---------------------------------------------------*/
/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
formats conform to ANSI/IEEE Std 754-1985. */
/* SINGLE precision floating:
* seeeeeeeefffffffffffffffffffffff
* s = 1bit = sign
* e = 8bits = exponent
* f = 23bits = fraction
*/
/* SINGLE precision fixed:
* siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
* s = 1bit = sign
* i = 31bits = integer
*/
/* DOUBLE precision floating:
* seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
* s = 1bit = sign
* e = 11bits = exponent
* f = 52bits = fraction
*/
/* DOUBLE precision fixed:
* siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
* s = 1bit = sign
* i = 63bits = integer
*/
/* Extract sign-bit: */
#define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
#define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* Extract biased exponent: */
#define FP_S_be(v) (((v) >> 23) & 0xFF)
#define FP_D_be(v) (((v) >> 52) & 0x7FF)
/* Extract unbiased Exponent: */
#define FP_S_e(v) (FP_S_be(v) - 0x7F)
#define FP_D_e(v) (FP_D_be(v) - 0x3FF)
/* Extract complete fraction field: */
#define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
#define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* Extract numbered fraction bit: */
#define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
#define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
/* Explicit QNaN values used when value required: */
#define FPQNaN_SINGLE (0x7FBFFFFF)
#define FPQNaN_WORD (0x7FFFFFFF)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
#define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
#define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* Explicit Infinity values used when required: */
#define FPINF_SINGLE (0x7F800000)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
#define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#if 1 /* def DEBUG */
#define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
#endif /* DEBUG */
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
value_fpr (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int fpr,
FP_formats fmt)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
Watchpoint interface.
1997-05-21 06:54:13 +00:00
uword64 value = 0;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
int err = 0;
/* Treat unused register values, as fixed-point 64bit values: */
if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
#if 1
/* If request to read data as "uninterpreted", then use the current
encoding: */
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
fmt = FPR_STATE[fpr];
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#else
fmt = fmt_long;
#endif
/* For values not yet accessed, set to the desired format: */
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (FPR_STATE[fpr] == fmt_uninterpreted) {
FPR_STATE[fpr] = fmt;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
#endif /* DEBUG */
}
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (fmt != FPR_STATE[fpr]) {
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
FPR_STATE[fpr] = fmt_unknown;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (FPR_STATE[fpr] == fmt_unknown) {
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* Set QNaN value: */
switch (fmt) {
case fmt_single:
value = FPQNaN_SINGLE;
break;
case fmt_double:
value = FPQNaN_DOUBLE;
break;
case fmt_word:
value = FPQNaN_WORD;
break;
case fmt_long:
value = FPQNaN_LONG;
break;
default:
err = -1;
break;
}
} else if (SizeFGR() == 64) {
switch (fmt) {
case fmt_single:
case fmt_word:
value = (FGR[fpr] & 0xFFFFFFFF);
break;
case fmt_uninterpreted:
case fmt_double:
case fmt_long:
value = FGR[fpr];
break;
default :
err = -1;
break;
}
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
} else {
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
switch (fmt) {
case fmt_single:
case fmt_word:
value = (FGR[fpr] & 0xFFFFFFFF);
break;
case fmt_uninterpreted:
case fmt_double:
case fmt_long:
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
if ((fpr & 1) == 0) { /* even registers only */
value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
} else {
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
SignalException(ReservedInstruction,0);
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
break;
default :
err = -1;
break;
}
}
if (err)
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
return(value);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
void
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
store_fpr (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int fpr,
FP_formats fmt,
uword64 value)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
int err = 0;
#ifdef DEBUG
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
if (SizeFGR() == 64) {
switch (fmt) {
Allow reads/writes to C0_CONFIG register.
1997-11-20 09:17:06 +00:00
case fmt_uninterpreted_32:
fmt = fmt_uninterpreted;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case fmt_single :
case fmt_word :
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
FPR_STATE[fpr] = fmt;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
break;
Allow reads/writes to C0_CONFIG register.
1997-11-20 09:17:06 +00:00
case fmt_uninterpreted_64:
fmt = fmt_uninterpreted;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case fmt_uninterpreted:
case fmt_double :
case fmt_long :
FGR[fpr] = value;
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
FPR_STATE[fpr] = fmt;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
break;
default :
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
FPR_STATE[fpr] = fmt_unknown;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
err = -1;
break;
}
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
} else {
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
switch (fmt) {
Allow reads/writes to C0_CONFIG register.
1997-11-20 09:17:06 +00:00
case fmt_uninterpreted_32:
fmt = fmt_uninterpreted;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case fmt_single :
case fmt_word :
FGR[fpr] = (value & 0xFFFFFFFF);
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
FPR_STATE[fpr] = fmt;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
break;
Allow reads/writes to C0_CONFIG register.
1997-11-20 09:17:06 +00:00
case fmt_uninterpreted_64:
fmt = fmt_uninterpreted;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case fmt_uninterpreted:
case fmt_double :
case fmt_long :
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
if ((fpr & 1) == 0) { /* even register number only */
FGR[fpr+1] = (value >> 32);
FGR[fpr] = (value & 0xFFFFFFFF);
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
FPR_STATE[fpr + 1] = fmt;
FPR_STATE[fpr] = fmt;
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
} else {
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
FPR_STATE[fpr] = fmt_unknown;
FPR_STATE[fpr + 1] = fmt_unknown;
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
SignalException(ReservedInstruction,0);
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
break;
default :
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
FPR_STATE[fpr] = fmt_unknown;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
err = -1;
break;
}
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
}
#if defined(WARN_RESULT)
else
UndefinedResult();
#endif /* WARN_RESULT */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
if (err)
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
return;
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
int
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
NaN(op,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
int boolean = 0;
switch (fmt) {
case fmt_single:
case fmt_word:
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
{
sim_fpu wop;
sim_fpu_32to (&wop, op);
boolean = sim_fpu_is_nan (&wop);
break;
}
case fmt_double:
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case fmt_long:
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
{
sim_fpu wop;
sim_fpu_64to (&wop, op);
boolean = sim_fpu_is_nan (&wop);
break;
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
return(boolean);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
int
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Infinity(op,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
int boolean = 0;
#ifdef DEBUG
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
switch (fmt) {
case fmt_single:
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
{
sim_fpu wop;
sim_fpu_32to (&wop, op);
boolean = sim_fpu_is_infinity (&wop);
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case fmt_double:
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
{
sim_fpu wop;
sim_fpu_64to (&wop, op);
boolean = sim_fpu_is_infinity (&wop);
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
default:
printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
break;
}
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
return(boolean);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
int
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Less(op1,op2,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op1;
uword64 op2;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
int boolean = 0;
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
/* Argument checking already performed by the FPCOMPARE code */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
boolean = sim_fpu_is_lt (&wop1, &wop2);
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
case fmt_double:
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
boolean = sim_fpu_is_lt (&wop1, &wop2);
break;
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#ifdef DEBUG
printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
#endif /* DEBUG */
return(boolean);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
int
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Equal(op1,op2,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op1;
uword64 op2;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
int boolean = 0;
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
/* Argument checking already performed by the FPCOMPARE code */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
boolean = sim_fpu_is_eq (&wop1, &wop2);
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case fmt_double:
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
boolean = sim_fpu_is_eq (&wop1, &wop2);
break;
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#ifdef DEBUG
printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
#endif /* DEBUG */
return(boolean);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
AbsoluteValue(op,fmt)
uword64 op;
FP_formats fmt;
{
Watchpoint interface.
1997-05-21 06:54:13 +00:00
uword64 result = 0;
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
#endif /* DEBUG */
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop;
unsigned32 ans;
sim_fpu_32to (&wop, op);
sim_fpu_abs (&wop, &wop);
sim_fpu_to32 (&ans, &wop);
result = ans;
break;
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
}
case fmt_double:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop;
unsigned64 ans;
sim_fpu_64to (&wop, op);
sim_fpu_abs (&wop, &wop);
sim_fpu_to64 (&ans, &wop);
result = ans;
break;
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> * gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
1996-04-19 14:53:16 +00:00
}
return(result);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Negate(op,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
Watchpoint interface.
1997-05-21 06:54:13 +00:00
uword64 result = 0;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop;
unsigned32 ans;
sim_fpu_32to (&wop, op);
sim_fpu_neg (&wop, &wop);
sim_fpu_to32 (&ans, &wop);
result = ans;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
case fmt_double:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop;
unsigned64 ans;
sim_fpu_64to (&wop, op);
sim_fpu_neg (&wop, &wop);
sim_fpu_to64 (&ans, &wop);
result = ans;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
return(result);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Add(op1,op2,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op1;
uword64 op2;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
Watchpoint interface.
1997-05-21 06:54:13 +00:00
uword64 result = 0;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop1;
sim_fpu wop2;
sim_fpu ans;
unsigned32 res;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
sim_fpu_add (&ans, &wop1, &wop2);
sim_fpu_to32 (&res, &ans);
result = res;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
case fmt_double:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop1;
sim_fpu wop2;
sim_fpu ans;
unsigned64 res;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
sim_fpu_add (&ans, &wop1, &wop2);
sim_fpu_to64 (&res, &ans);
result = res;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
return(result);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Sub(op1,op2,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op1;
uword64 op2;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
Watchpoint interface.
1997-05-21 06:54:13 +00:00
uword64 result = 0;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop1;
sim_fpu wop2;
sim_fpu ans;
unsigned32 res;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
sim_fpu_sub (&ans, &wop1, &wop2);
sim_fpu_to32 (&res, &ans);
result = res;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
break;
case fmt_double:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop1;
sim_fpu wop2;
sim_fpu ans;
unsigned64 res;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
sim_fpu_sub (&ans, &wop1, &wop2);
sim_fpu_to64 (&res, &ans);
result = res;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
break;
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
return(result);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Multiply(op1,op2,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op1;
uword64 op2;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
Watchpoint interface.
1997-05-21 06:54:13 +00:00
uword64 result = 0;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop1;
sim_fpu wop2;
sim_fpu ans;
unsigned32 res;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
sim_fpu_mul (&ans, &wop1, &wop2);
sim_fpu_to32 (&res, &ans);
result = res;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
case fmt_double:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop1;
sim_fpu wop2;
sim_fpu ans;
unsigned64 res;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
sim_fpu_mul (&ans, &wop1, &wop2);
sim_fpu_to64 (&res, &ans);
result = res;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
return(result);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Divide(op1,op2,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op1;
uword64 op2;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
Watchpoint interface.
1997-05-21 06:54:13 +00:00
uword64 result = 0;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop1;
sim_fpu wop2;
sim_fpu ans;
unsigned32 res;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
sim_fpu_div (&ans, &wop1, &wop2);
sim_fpu_to32 (&res, &ans);
result = res;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
case fmt_double:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop1;
sim_fpu wop2;
sim_fpu ans;
unsigned64 res;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
sim_fpu_div (&ans, &wop1, &wop2);
sim_fpu_to64 (&res, &ans);
result = res;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
return(result);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64 UNUSED
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Recip(op,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
Watchpoint interface.
1997-05-21 06:54:13 +00:00
uword64 result = 0;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop;
sim_fpu ans;
unsigned32 res;
sim_fpu_32to (&wop, op);
sim_fpu_inv (&ans, &wop);
sim_fpu_to32 (&res, &ans);
result = res;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
case fmt_double:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop;
sim_fpu ans;
unsigned64 res;
sim_fpu_64to (&wop, op);
sim_fpu_inv (&ans, &wop);
sim_fpu_to64 (&res, &ans);
result = res;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
return(result);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
SquareRoot(op,fmt)
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 op;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
FP_formats fmt;
{
Watchpoint interface.
1997-05-21 06:54:13 +00:00
uword64 result = 0;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop;
sim_fpu ans;
unsigned32 res;
sim_fpu_32to (&wop, op);
sim_fpu_sqrt (&ans, &wop);
sim_fpu_to32 (&res, &ans);
result = res;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
case fmt_double:
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop;
sim_fpu ans;
unsigned64 res;
sim_fpu_64to (&wop, op);
sim_fpu_sqrt (&ans, &wop);
sim_fpu_to64 (&res, &ans);
result = res;
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
return(result);
}
Define CPU_INDEX. Initialize. For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
1998-03-27 04:25:45 +00:00
#if 0
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
uword64
Max (uword64 op1,
uword64 op2,
FP_formats fmt)
{
int cmp;
unsigned64 result;
#ifdef DEBUG
printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
/* The format type should already have been checked: */
switch (fmt)
{
case fmt_single:
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
cmp = sim_fpu_cmp (&wop1, &wop2);
break;
}
case fmt_double:
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
cmp = sim_fpu_cmp (&wop1, &wop2);
break;
}
default:
fprintf (stderr, "Bad switch\n");
abort ();
}
switch (cmp)
{
case SIM_FPU_IS_SNAN:
case SIM_FPU_IS_QNAN:
result = op1;
case SIM_FPU_IS_NINF:
case SIM_FPU_IS_NNUMBER:
case SIM_FPU_IS_NDENORM:
case SIM_FPU_IS_NZERO:
result = op2; /* op1 - op2 < 0 */
case SIM_FPU_IS_PINF:
case SIM_FPU_IS_PNUMBER:
case SIM_FPU_IS_PDENORM:
case SIM_FPU_IS_PZERO:
result = op1; /* op1 - op2 > 0 */
default:
fprintf (stderr, "Bad switch\n");
abort ();
}
#ifdef DEBUG
printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
Define CPU_INDEX. Initialize. For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
1998-03-27 04:25:45 +00:00
#endif
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
Define CPU_INDEX. Initialize. For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
1998-03-27 04:25:45 +00:00
#if 0
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
uword64
Min (uword64 op1,
uword64 op2,
FP_formats fmt)
{
int cmp;
unsigned64 result;
#ifdef DEBUG
printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
/* The format type should already have been checked: */
switch (fmt)
{
case fmt_single:
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
cmp = sim_fpu_cmp (&wop1, &wop2);
break;
}
case fmt_double:
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
cmp = sim_fpu_cmp (&wop1, &wop2);
break;
}
default:
fprintf (stderr, "Bad switch\n");
abort ();
}
switch (cmp)
{
case SIM_FPU_IS_SNAN:
case SIM_FPU_IS_QNAN:
result = op1;
case SIM_FPU_IS_NINF:
case SIM_FPU_IS_NNUMBER:
case SIM_FPU_IS_NDENORM:
case SIM_FPU_IS_NZERO:
result = op1; /* op1 - op2 < 0 */
case SIM_FPU_IS_PINF:
case SIM_FPU_IS_PNUMBER:
case SIM_FPU_IS_PDENORM:
case SIM_FPU_IS_PZERO:
result = op2; /* op1 - op2 > 0 */
default:
fprintf (stderr, "Bad switch\n");
abort ();
}
#ifdef DEBUG
printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
Define CPU_INDEX. Initialize. For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
1998-03-27 04:25:45 +00:00
#endif
sim-main.h: Re-arange r5900 registers so that they have their own little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
convert (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int rm,
uword64 op,
FP_formats from,
FP_formats to)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
sim_fpu wop;
sim_fpu_round round;
unsigned32 result32;
unsigned64 result64;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
switch (rm)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
case FP_RM_NEAREST:
/* Round result to nearest representable value. When two
representable values are equally near, round to the value
that has a least significant bit of zero (i.e. is even). */
round = sim_fpu_round_near;
break;
case FP_RM_TOZERO:
/* Round result to the value closest to, and not greater in
magnitude than, the result. */
round = sim_fpu_round_zero;
break;
case FP_RM_TOPINF:
/* Round result to the value closest to, and not less than,
the result. */
round = sim_fpu_round_up;
break;
case FP_RM_TOMINF:
/* Round result to the value closest to, and not greater than,
the result. */
round = sim_fpu_round_down;
break;
default:
round = 0;
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
/* Convert the input to sim_fpu internal format */
switch (from)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
case fmt_double:
sim_fpu_64to (&wop, op);
break;
case fmt_single:
sim_fpu_32to (&wop, op);
break;
case fmt_word:
sim_fpu_i32to (&wop, op, round);
break;
case fmt_long:
sim_fpu_i64to (&wop, op, round);
break;
default:
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
/* Convert sim_fpu format into the output */
/* The value WOP is converted to the destination format, rounding
using mode RM. When the destination is a fixed-point format, then
a source value of Infinity, NaN or one which would round to an
integer outside the fixed point range then an IEEE Invalid
Operation condition is raised. */
switch (to)
{
case fmt_single:
sim_fpu_round_32 (&wop, round, 0);
sim_fpu_to32 (&result32, &wop);
result64 = result32;
break;
case fmt_double:
sim_fpu_round_64 (&wop, round, 0);
sim_fpu_to64 (&result64, &wop);
break;
case fmt_word:
sim_fpu_to32i (&result32, &wop, round);
result64 = result32;
break;
case fmt_long:
sim_fpu_to64i (&result64, &wop, round);
break;
default:
result64 = 0;
fprintf (stderr, "Bad switch\n");
abort ();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
return(result64);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/*-- co-processor support routines ------------------------------------------*/
Extend xor-endian and per-cpu support in core module. Allow negated test when watching value within core.
1997-05-27 06:48:20 +00:00
static int UNUSED
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
CoProcPresent(coproc_number)
unsigned int coproc_number;
{
/* Return TRUE if simulator provides a model for the given co-processor number */
return(0);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
void
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
cop_lw (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int coproc_num,
int coproc_reg,
unsigned int memword)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
switch (coproc_num)
{
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case 1:
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
StoreFPR(coproc_reg,fmt_word,(uword64)memword);
FPR_STATE[coproc_reg] = fmt_uninterpreted;
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
default:
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#if 0 /* this should be controlled by a configuration option */
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#endif
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
return;
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
void
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
cop_ld (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int coproc_num,
int coproc_reg,
uword64 memword)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
switch (coproc_num) {
case 1:
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
StoreFPR(coproc_reg,fmt_uninterpreted,memword);
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
default:
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#if 0 /* this message should be controlled by a configuration option */
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#endif
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
break;
}
return;
}
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
/* start-sanitize-sky */
#ifdef TARGET_SKY
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
void
cop_lq (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int coproc_num,
int coproc_reg,
unsigned128 memword)
{
switch (coproc_num)
{
case 2:
* R5900 COP2 is now ready for testing. Let loose the dogs! Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses for TARGET_SKY. * r5900.igen (SQC2): Thinko.
1998-04-07 00:01:31 +00:00
{
* Fixed data mangling problems in R5900 COP2 LQC2/SQC2 instructions.
1998-04-17 19:04:53 +00:00
int i;
* R5900 COP2 is now ready for testing. Let loose the dogs! Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses for TARGET_SKY. * r5900.igen (SQC2): Thinko.
1998-04-07 00:01:31 +00:00
while(vu0_busy())
vu0_issue(sd);
/* one word at a time, argh! */
* Fixed data mangling problems in R5900 COP2 LQC2/SQC2 instructions.
1998-04-17 19:04:53 +00:00
for(i=0; i<4; i++)
{
unsigned_4 value;
value = H2T_4(*A4_16(& memword, 3-i));
write_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
}
* R5900 COP2 is now ready for testing. Let loose the dogs! Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses for TARGET_SKY. * r5900.igen (SQC2): Thinko.
1998-04-07 00:01:31 +00:00
}
break;
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
default:
sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
coproc_num,coproc_reg,pr_addr(cia));
break;
}
return;
}
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
#endif /* TARGET_SKY */
/* end-sanitize-sky */
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
unsigned int
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
cop_sw (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int coproc_num,
int coproc_reg)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
unsigned int value = 0;
* interp.c (mips16_entry): Add support for floating point cases. (SignalException): Pass floating point cases to mips16_entry. (ValueFPR): Don't restrict fmt_single and fmt_word to even registers. (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single or fmt_word. (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, and then set the state to fmt_uninterpreted. (COP_SW): Temporarily set the state to fmt_word while calling ValueFPR.
1997-02-06 22:19:05 +00:00
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
switch (coproc_num)
{
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case 1:
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
FP_formats hold;
hold = FPR_STATE[coproc_reg];
FPR_STATE[coproc_reg] = fmt_word;
value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
FPR_STATE[coproc_reg] = hold;
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
default:
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#if 0 /* should be controlled by configuration option */
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#endif
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
return(value);
}
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
uword64
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
cop_sd (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int coproc_num,
int coproc_reg)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
uword64 value = 0;
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
switch (coproc_num)
{
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case 1:
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
value = ValueFPR(coproc_reg,fmt_uninterpreted);
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
default:
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#if 0 /* should be controlled by configuration option */
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#endif
Always compile FP code (test for FP at run-time). Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
break;
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
return(value);
}
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
/* start-sanitize-sky */
#ifdef TARGET_SKY
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
unsigned128
cop_sq (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int coproc_num,
int coproc_reg)
{
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
unsigned128 value = U16_8(0, 0);
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
switch (coproc_num)
{
case 2:
* R5900 COP2 is now ready for testing. Let loose the dogs! Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses for TARGET_SKY. * r5900.igen (SQC2): Thinko.
1998-04-07 00:01:31 +00:00
{
unsigned_16 xyzw;
* Fixed data mangling problems in R5900 COP2 LQC2/SQC2 instructions.
1998-04-17 19:04:53 +00:00
int i;
* R5900 COP2 is now ready for testing. Let loose the dogs! Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses for TARGET_SKY. * r5900.igen (SQC2): Thinko.
1998-04-07 00:01:31 +00:00
while(vu0_busy())
vu0_issue(sd);
/* one word at a time, argh! */
* Fixed data mangling problems in R5900 COP2 LQC2/SQC2 instructions.
1998-04-17 19:04:53 +00:00
for(i=0; i<4; i++)
{
unsigned_4 value;
read_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
*A4_16(& xyzw, 3-i) = T2H_4(value);
}
* R5900 COP2 is now ready for testing. Let loose the dogs! Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses for TARGET_SKY. * r5900.igen (SQC2): Thinko.
1998-04-07 00:01:31 +00:00
return xyzw;
}
break;
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
default:
sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
coproc_num,coproc_reg,pr_addr(cia));
break;
}
return(value);
}
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
#endif /* TARGET_SKY */
/* end-sanitize-sky */
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
Move register definitions and macros out of interp.c and into sim-main.h
1997-10-16 03:50:48 +00:00
void
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
decode_coproc (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
unsigned int instruction)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
int coprocnum = ((instruction >> 26) & 3);
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
switch (coprocnum)
{
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case 0: /* standard CPU control and cache registers */
{
int code = ((instruction >> 21) & 0x1F);
/* R4000 Users Manual (second edition) lists the following CP0
instructions:
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
ERET Exception return (VR4100 = 01000010000000000000000000011000)
*/
if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
{
int rt = ((instruction >> 16) & 0x1F);
int rd = ((instruction >> 11) & 0x1F);
switch (rd) /* NOTEs: Standard CP0 registers */
{
/* 0 = Index R4000 VR4100 VR4300 */
/* 1 = Random R4000 VR4100 VR4300 */
/* 2 = EntryLo0 R4000 VR4100 VR4300 */
/* 3 = EntryLo1 R4000 VR4100 VR4300 */
/* 4 = Context R4000 VR4100 VR4300 */
/* 5 = PageMask R4000 VR4100 VR4300 */
/* 6 = Wired R4000 VR4100 VR4300 */
/* 8 = BadVAddr R4000 VR4100 VR4300 */
/* 9 = Count R4000 VR4100 VR4300 */
/* 10 = EntryHi R4000 VR4100 VR4300 */
/* 11 = Compare R4000 VR4100 VR4300 */
/* 12 = SR R4000 VR4100 VR4300 */
* Small TX39-only patch for ECC. Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): For TX39, add stub COP0 register #3, to allay warnings.
1998-06-01 16:29:43 +00:00
#ifdef SUBTARGET_R3900
case 3:
/* ignore */
break;
/* 3 = Config R3900 */
* Support for sky hardware interrupts. The sky-dma cannot trigger interrupts properly yet (jlemke TODO). Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): For TX39, add stub COP0 register #7, to allay warnings. (interrupt_event): Made non-static. start-sanitize-tx3904 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental interchange of configuration values for external vs. internal clock dividers. end-sanitize-tx3904 start-sanitize-sky * sky-device.c (sky_signal_interrupt): New function to generate interrupt event. * sky-device.h: Declare it. * sky-dma.c (check_int1): Call it. * sky-pke.c (pke_begin_interrupt_stall): Call it. end-sanitize-sky
1998-06-10 17:07:10 +00:00
case 7:
/* ignore */
break;
/* 3 = Cache R3900 */
* Small TX39-only patch for ECC. Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): For TX39, add stub COP0 register #3, to allay warnings.
1998-06-01 16:29:43 +00:00
#endif /* SUBTARGET_R3900 */
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
case 12:
if (code == 0x00)
GPR[rt] = SR;
else
SR = GPR[rt];
break;
/* 13 = Cause R4000 VR4100 VR4300 */
* interp.c (sim_engine_run): Reset the ZERO register to zero regardless of FEATURE_WARN_ZERO.
1997-07-02 18:13:00 +00:00
case 13:
if (code == 0x00)
GPR[rt] = CAUSE;
else
CAUSE = GPR[rt];
break;
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
/* 14 = EPC R4000 VR4100 VR4300 */
Implement ERET instruction. Add {signed,unsigned}_address type.
1998-04-21 04:30:27 +00:00
case 14:
if (code == 0x00)
GPR[rt] = (signed_word) (signed_address) EPC;
else
EPC = GPR[rt];
break;
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
/* 15 = PRId R4000 VR4100 VR4300 */
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
#ifdef SUBTARGET_R3900
/* 16 = Debug */
case 16:
if (code == 0x00)
GPR[rt] = Debug;
else
Debug = GPR[rt];
break;
#else
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
/* 16 = Config R4000 VR4100 VR4300 */
Allow reads/writes to C0_CONFIG register.
1997-11-20 09:17:06 +00:00
case 16:
if (code == 0x00)
GPR[rt] = C0_CONFIG;
else
C0_CONFIG = GPR[rt];
break;
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
#endif
#ifdef SUBTARGET_R3900
/* 17 = Debug */
case 17:
if (code == 0x00)
GPR[rt] = DEPC;
else
DEPC = GPR[rt];
break;
#else
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
/* 17 = LLAddr R4000 VR4100 VR4300 */
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
#endif
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
/* 18 = WatchLo R4000 VR4100 VR4300 */
/* 19 = WatchHi R4000 VR4100 VR4300 */
/* 20 = XContext R4000 VR4100 VR4300 */
/* 26 = PErr or ECC R4000 VR4100 VR4300 */
/* 27 = CacheErr R4000 VR4100 */
/* 28 = TagLo R4000 VR4100 VR4300 */
/* 29 = TagHi R4000 VR4100 VR4300 */
/* 30 = ErrorEPC R4000 VR4100 VR4300 */
GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
/* CPR[0,rd] = GPR[rt]; */
default:
if (code == 0x00)
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
else
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
}
}
else if (code == 0x10 && (instruction & 0x3f) == 0x18)
{
/* ERET */
if (SR & status_ERL)
{
/* Oops, not yet available */
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
PC = EPC;
SR &= ~status_ERL;
}
else
{
PC = EPC;
SR &= ~status_EXL;
}
}
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
else if (code == 0x10 && (instruction & 0x3f) == 0x10)
{
/* RFE */
* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
#ifdef SUBTARGET_R3900
/* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
/* shift IE/KU history bits right */
SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
/* TODO: CACHE register */
#endif /* SUBTARGET_R3900 */
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
}
else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
{
/* DERET */
Debug &= ~Debug_DM;
DELAYSLOT();
DSPC = DEPC;
}
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
else
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c, gencode.c: Some more (TODO) tidying.
1996-03-27 14:46:27 +00:00
/* TODO: When executing an ERET or RFE instruction we should
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
clear LLBIT, to ensure that any out-standing atomic
read/modify/write sequence fails. */
}
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
break;
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
case 2: /* co-processor 2 */
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
{
int handle = 0;
/* start-sanitize-sky */
* Oops, added #ifdef TARGET_SKY around R5900 COP2 implementation skeleton.
1998-03-29 22:53:31 +00:00
#ifdef TARGET_SKY
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
/* On the R5900, this refers to a "VU" vector co-processor. */
int i_25_21 = (instruction >> 21) & 0x1f;
int i_20_16 = (instruction >> 16) & 0x1f;
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
int i_20_6 = (instruction >> 6) & 0x7fff;
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
int i_15_11 = (instruction >> 11) & 0x1f;
int i_15_0 = instruction & 0xffff;
int i_10_1 = (instruction >> 1) & 0x3ff;
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
int i_10_0 = instruction & 0x7ff;
int i_10_6 = (instruction >> 6) & 0x1f;
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
int i_5_0 = instruction & 0x03f;
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
int interlock = instruction & 0x01;
/* setup for semantic.c-like actions below */
typedef unsigned_4 instruction_word;
int CIA = cia;
int NIA = cia + 4;
handle = 1;
/* test COP2 usability */
if(! (SR & status_CU2))
{
SignalException(CoProcessorUnusable,instruction);
/* NOTREACHED */
}
* Changes to make interp.c compile under mips64r5900-sky-elf target. Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Make COP2 branch code compile after igen signature changes.
1998-04-15 19:02:04 +00:00
#define MY_INDEX itable_COPz_NORMAL
#define MY_PREFIX COPz_NORMAL
#define MY_NAME "COPz_NORMAL"
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
/* classify & execute basic COP2 instructions */
if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */
{
address_word offset = EXTEND16(i_15_0) << 2;
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
}
else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */
{
address_word offset = EXTEND16(i_15_0) << 2;
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
else NULLIFY_NEXT_INSTRUCTION();
}
else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */
{
address_word offset = EXTEND16(i_15_0) << 2;
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
}
else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */
{
address_word offset = EXTEND16(i_15_0) << 2;
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
else NULLIFY_NEXT_INSTRUCTION();
}
else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
(i_25_21 == 0x01)) /* QMFC2 */
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
{
int rt = i_20_16;
int id = i_15_11;
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
/* interlock checking */
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* POLICY: never busy in macro mode */
while(vu0_busy() && interlock)
vu0_issue(sd);
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* perform VU register address */
if(i_25_21 == 0x01) /* QMFC2 */
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
{
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
unsigned_16 xyzw;
/* one word at a time, argh! */
read_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
read_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
read_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
read_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
For new IGEN simulators, rewrite checks validating correct use of the HI/LO registers. For old gencode simulator, delete all checks.
1998-04-21 01:17:58 +00:00
GPR[rt] = T2H_8(* A8_16(& xyzw, 1));
GPR1[rt] = T2H_8(* A8_16(& xyzw, 0));
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
}
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
else /* CFC2 */
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
{
unsigned_4 data;
/* enum + int calculation, argh! */
id = VU_REG_MST + 16 * id;
Added support for the VU insn D (debug) & T (trace) bits.
1998-06-04 20:50:55 +00:00
if (id >= VU_REG_CMSAR0)
read_vu_special_reg(&vu0_device, id, & data);
else
read_vu_misc_reg(&(vu0_device.regs), id, & data);
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
GPR[rt] = EXTEND32(T2H_4(data));
}
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
}
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
(i_25_21 == 0x05)) /* QMTC2 */
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
{
int rt = i_20_16;
int id = i_15_11;
* Adapted R5900 COP2 interface code to clarified micro-mode interlock behavior.
1998-04-16 19:27:55 +00:00
/* interlock checking: wait until M or E bits set */
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* POLICY: never busy in macro mode */
* Adapted R5900 COP2 interface code to clarified micro-mode interlock behavior.
1998-04-16 19:27:55 +00:00
while(vu0_busy() && interlock)
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
{
* Adapted R5900 COP2 interface code to clarified micro-mode interlock behavior.
1998-04-16 19:27:55 +00:00
if(vu0_micro_interlock_released())
{
vu0_micro_interlock_clear();
break;
}
vu0_issue(sd);
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
}
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* perform VU register address */
if(i_25_21 == 0x05) /* QMTC2 */
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
{
For new IGEN simulators, rewrite checks validating correct use of the HI/LO registers. For old gencode simulator, delete all checks.
1998-04-21 01:17:58 +00:00
unsigned_16 xyzw = U16_8(GPR1[rt], GPR[rt]);
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
xyzw = H2T_16(xyzw);
/* one word at a time, argh! */
write_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
write_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
write_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
write_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
}
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
else /* CTC2 */
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
{
unsigned_4 data = H2T_4(GPR[rt]);
/* enum + int calculation, argh! */
Added support for the VU insn D (debug) & T (trace) bits.
1998-06-04 20:50:55 +00:00
id = VU_REG_VI + 16 * id;
if (id >= VU_REG_CMSAR0)
write_vu_special_reg(&vu0_device, id, & data);
else
write_vu_misc_reg(&(vu0_device.regs), id, & data);
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
}
}
else if(i_10_0 == 0x3bf) /* VWAITQ */
{
while(vu0_q_busy())
vu0_issue(sd);
}
else if(i_5_0 == 0x38) /* VCALLMS */
{
unsigned_4 data = H2T_2(i_20_6);
while(vu0_busy())
vu0_issue(sd);
/* write to reserved CIA register to get VU0 moving */
* R5900 sky COP2 testing continuing. Today only small VCALLMS-related were found/fixed. [ChangeLog.sky] * sky-vu.c ({read,write}_vu_special_reg): Add CMSAR[01] as special registers for a VU. Behavior not as mandated. ({read,write}_vu_{misc,special}_reg): Create sim_io_error upon access to unknown register. Behavior not as mandated. * sky-vu.h (anonymous register numbering enum): Add CMSAR[01]. * sky-libvpe.c (indebug): Cache $ENV{'SKY_DEBUG'}. [ChangeLog] * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o. * interp.c (decode_coproc): Refer to VU CIA as a "special" register, not as a "misc" register. Aha. Add activity assertions after VCALLMS* instructions.
1998-04-08 22:22:58 +00:00
write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
ASSERT(vu0_busy());
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
}
else if(i_5_0 == 0x39) /* VCALLMSR */
{
unsigned_4 data;
while(vu0_busy())
vu0_issue(sd);
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
* R5900 sky COP2 testing continuing. Today only small VCALLMS-related were found/fixed. [ChangeLog.sky] * sky-vu.c ({read,write}_vu_special_reg): Add CMSAR[01] as special registers for a VU. Behavior not as mandated. ({read,write}_vu_{misc,special}_reg): Create sim_io_error upon access to unknown register. Behavior not as mandated. * sky-vu.h (anonymous register numbering enum): Add CMSAR[01]. * sky-libvpe.c (indebug): Cache $ENV{'SKY_DEBUG'}. [ChangeLog] * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o. * interp.c (decode_coproc): Refer to VU CIA as a "special" register, not as a "misc" register. Aha. Add activity assertions after VCALLMS* instructions.
1998-04-08 22:22:58 +00:00
read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* write to reserved CIA register to get VU0 moving */
* R5900 sky COP2 testing continuing. Today only small VCALLMS-related were found/fixed. [ChangeLog.sky] * sky-vu.c ({read,write}_vu_special_reg): Add CMSAR[01] as special registers for a VU. Behavior not as mandated. ({read,write}_vu_{misc,special}_reg): Create sim_io_error upon access to unknown register. Behavior not as mandated. * sky-vu.h (anonymous register numbering enum): Add CMSAR[01]. * sky-libvpe.c (indebug): Cache $ENV{'SKY_DEBUG'}. [ChangeLog] * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o. * interp.c (decode_coproc): Refer to VU CIA as a "special" register, not as a "misc" register. Aha. Add activity assertions after VCALLMS* instructions.
1998-04-08 22:22:58 +00:00
write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
ASSERT(vu0_busy());
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
}
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* handle all remaining UPPER VU instructions in one block */
else if((i_5_0 < 0x30) || /* VADDx .. VMINI */
(i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
{
unsigned_4 vu_upper, vu_lower;
vu_upper =
* R5900 COP2 sim testing in progress. The majority of instructions actually work! [ChangeLog.sky] * sky-vu.h (vu_device): Represent "macro instruction just stuffed into fetch buffer" condition with new "m" bit. Rename old "m" to "l". * sky-libvpe.c (indebug): Save snapshot of environment value; workaround for suspected memory corruption. (fetch_inst): Respect new "m" macro-instruction flag for reporting successful fetch to caller. (exec_inst): Disassemble instruction here instead of fetch time. Renamed old "m" -> "l" flag in VU state to track interlock release. (vpecallms_cycle): Call exec_inst only if fetch_inst did some work. * sky-vu.c (vu_attach, vu[01]_device): Revamped initialization to ensure complete clear of tail part of struct at attach time. (vu0_busy): Fix thinko. (vu0_macro_issue): Adapt to new "l" flag. (vu0_micro_interlock_released): Ditto. (write_vu_special_reg): Ditto. (read_vu_special_reg): Compute VBS0/VBS1 bits more explicitly. The other VU status bits are not yet computed. [ChangeLog] * interp.c (decode_coproc): Do not apply superfluous E (end) flag to upper code of generated VU instruction.
1998-04-07 22:47:53 +00:00
0x00000000 | /* bits 31 .. 25 */
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
(instruction & 0x01ffffff); /* bits 24 .. 0 */
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
vu_lower = 0x8000033c; /* NOP */
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* POLICY: never busy in macro mode */
while(vu0_busy())
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
vu0_issue(sd);
vu0_macro_issue(vu_upper, vu_lower);
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* POLICY: wait for completion of macro-instruction */
while(vu0_busy())
vu0_issue(sd);
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
}
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* handle all remaining LOWER VU instructions in one block */
else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */
(i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
{ /* N.B.: VWAITQ already covered by prior case */
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
unsigned_4 vu_upper, vu_lower;
* R5900 COP2 sim testing in progress. The majority of instructions actually work! [ChangeLog.sky] * sky-vu.h (vu_device): Represent "macro instruction just stuffed into fetch buffer" condition with new "m" bit. Rename old "m" to "l". * sky-libvpe.c (indebug): Save snapshot of environment value; workaround for suspected memory corruption. (fetch_inst): Respect new "m" macro-instruction flag for reporting successful fetch to caller. (exec_inst): Disassemble instruction here instead of fetch time. Renamed old "m" -> "l" flag in VU state to track interlock release. (vpecallms_cycle): Call exec_inst only if fetch_inst did some work. * sky-vu.c (vu_attach, vu[01]_device): Revamped initialization to ensure complete clear of tail part of struct at attach time. (vu0_busy): Fix thinko. (vu0_macro_issue): Adapt to new "l" flag. (vu0_micro_interlock_released): Ditto. (write_vu_special_reg): Ditto. (read_vu_special_reg): Compute VBS0/VBS1 bits more explicitly. The other VU status bits are not yet computed. [ChangeLog] * interp.c (decode_coproc): Do not apply superfluous E (end) flag to upper code of generated VU instruction.
1998-04-07 22:47:53 +00:00
vu_upper = 0x000002ff; /* NOP/NOP */
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
vu_lower =
* Fixed a one-character typo in COP2 instruction synthesis. [ChangeLog] Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Add proper 1000000 bit-string at top of VU lower instruction.
1998-04-13 20:31:29 +00:00
0x80000000 | /* bits 31 .. 25 */
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
(instruction & 0x01ffffff); /* bits 24 .. 0 */
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* POLICY: never busy in macro mode */
while(vu0_busy())
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
vu0_issue(sd);
vu0_macro_issue(vu_upper, vu_lower);
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* POLICY: wait for completion of macro-instruction */
while(vu0_busy())
vu0_issue(sd);
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
}
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
/* ... no other COP2 instructions ... */
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
else
{
* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
SignalException(ReservedInstruction, instruction);
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
/* NOTREACHED */
}
/* cleanup for semantic.c-like actions above */
PC = NIA;
* Changes to make interp.c compile under mips64r5900-sky-elf target. Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Make COP2 branch code compile after igen signature changes.
1998-04-15 19:02:04 +00:00
#undef MY_INDEX
#undef MY_PREFIX
#undef MY_NAME
* Oops, added #ifdef TARGET_SKY around R5900 COP2 implementation skeleton.
1998-03-29 22:53:31 +00:00
#endif /* TARGET_SKY */
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
/* end-sanitize-sky */
if(! handle)
{
* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05 16:40:03 +00:00
sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
instruction,pr_addr(cia));
}
}
break;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
case 1: /* should not occur (FPU co-processor) */
case 3: /* should not occur (FPU co-processor) */
SignalException(ReservedInstruction,instruction);
break;
o Fixes to repeated watchpoints o Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
return;
}
* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/*-- instruction simulation -------------------------------------------------*/
Separate r5900 specifoc and mips16 instructions. Add support for this to configure (vr5400 target only)
1997-10-27 07:55:24 +00:00
/* When the IGEN simulator is being built, the function below is be
replaced by a generated version. However, WITH_IGEN == 2 indicates
that the fubction below should be compiled but under a different
name (to allow backward compatibility) */
#if (WITH_IGEN != 1)
#if (WITH_IGEN > 1)
Add function to fetch 32bit instructions When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
void
igen: Fix SMP simulator generator support. Use the bfd-processor name in the sim-engine switch. Add nr_cpus argument to sim_engine_run. tic80, v850, d30v, mips, common: Update mips: Fill in bfd-processor field of model records so that they match ../bfd/archures.
1998-01-31 06:23:41 +00:00
old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
Add function to fetch 32bit instructions When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
#else
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
void
igen: Fix SMP simulator generator support. Use the bfd-processor name in the sim-engine switch. Add nr_cpus argument to sim_engine_run. tic80, v850, d30v, mips, common: Update mips: Fill in bfd-processor field of model records so that they match ../bfd/archures.
1998-01-31 06:23:41 +00:00
sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
Add function to fetch 32bit instructions When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
#endif
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
SIM_DESC sd;
int next_cpu_nr; /* ignore */
igen: Fix SMP simulator generator support. Use the bfd-processor name in the sim-engine switch. Add nr_cpus argument to sim_engine_run. tic80, v850, d30v, mips, common: Update mips: Fill in bfd-processor field of model records so that they match ../bfd/archures.
1998-01-31 06:23:41 +00:00
int nr_cpus; /* ignore */
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
int siggnal; /* ignore */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
{
mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
Watchpoint interface.
1997-05-21 06:54:13 +00:00
#if !defined(FASTSIM)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
unsigned int pipeline_count = 1;
Watchpoint interface.
1997-05-21 06:54:13 +00:00
#endif
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
Watchpoint interface.
1997-05-21 06:54:13 +00:00
if (STATE_MEMORY (sd) == NULL) {
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
printf("DBG: simulate() entered with no memory\n");
exit(1);
}
#endif /* DEBUG */
#if 0 /* Disabled to check that everything works OK */
/* The VR4300 seems to sign-extend the PC on its first
access. However, this may just be because it is currently
configured in 32bit mode. However... */
PC = SIGNEXTEND(PC,32);
#endif
/* main controlling loop */
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
while (1) {
IGEN likes to cache the current instruction address (CIA). Change the MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
/* vaddr is slowly being replaced with cia - current instruction
address */
address_word cia = (uword64)PC;
address_word vaddr = cia;
Add function to fetch 32bit instructions When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
address_word paddr;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
int cca;
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
unsigned int instruction; /* uword64? what's this used for? FIXME! */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
{
printf("DBG: state = 0x%08X :",state);
if (state & simHALTEX) printf(" simHALTEX");
if (state & simHALTIN) printf(" simHALTIN");
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("\n");
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
#endif /* DEBUG */
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
DSSTATE = (STATE & simDELAYSLOT);
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
if (dsstate)
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
IGEN likes to cache the current instruction address (CIA). Change the MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
/* Fetch the next instruction from the simulator memory: */
if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
For NEC 4100/4300 project * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
1996-12-10 19:39:55 +00:00
if ((vaddr & 1) == 0) {
/* Copy the action of the LW instruction */
unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
uword64 value;
unsigned int byte;
paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
For NEC 4100/4300 project * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
1996-12-10 19:39:55 +00:00
byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
} else {
/* Copy the action of the LH instruction */
unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
uword64 value;
unsigned int byte;
paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
| (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
For NEC 4100/4300 project * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
1996-12-10 19:39:55 +00:00
paddr & ~ (uword64) 1,
vaddr, isINSTRUCTION, isREAL);
byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
instruction = ((value >> (8 * byte)) & 0xFFFF);
}
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
} else {
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
exit(1);
}
#ifdef DEBUG
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
/* This is required by exception processing, to ensure that we can
cope with exceptions in the delay slots of branches that may
already have changed the PC. */
For NEC 4100/4300 project * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
1996-12-10 19:39:55 +00:00
if ((vaddr & 1) == 0)
PC += 4; /* increment ready for the next fetch */
else
PC += 2;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* NOTE: If we perform a delay slot change to the PC, this
increment is not requuired. However, it would make the
simulator more complicated to try and avoid this small hit. */
/* Currently this code provides a simple model. For more
complicated models we could perform exception status checks at
this point, and set the simSTOP state as required. This could
also include processing any hardware interrupts raised by any
I/O model attached to the simulator context.
Support for "asynchronous" I/O events within the simulated world
could be providing by managing a counter, and calling a I/O
specific handler when a particular threshold is reached. On most
architectures a decrement and check for zero operation is
usually quicker than an increment and compare. However, the
process of managing a known value decrement to zero, is higher
than the cost of using an explicit value UINT_MAX into the
future. Which system is used will depend on how complicated the
I/O model is, and how much it is likely to affect the simulator
bandwidth.
If events need to be scheduled further in the future than
UINT_MAX event ticks, then the I/O model should just provide its
own counter, triggered from the event system. */
/* MIPS pipeline ticks. To allow for future support where the
pipeline hit of individual instructions is known, this control
loop manages a "pipeline_count" variable. It is initialised to
1 (one), and will only be changed by the simulator engine when
executing an instruction. If the engine does not have access to
pipeline cycle count information then all instructions will be
treated as using a single cycle. NOTE: A standard system is not
provided by the default simulator because different MIPS
architectures have different cycle counts for the same
Watchpoint interface.
1997-05-21 06:54:13 +00:00
instructions.
[NOTE: pipeline_count has been replaced the event queue] */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
Allow reads/writes to C0_CONFIG register.
1997-11-20 09:17:06 +00:00
/* shuffle the floating point status pipeline state */
ENGINE_ISSUE_PREFIX_HOOK();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* NOTE: For multi-context simulation environments the "instruction"
variable should be local to this routine. */
/* Shorthand accesses for engine. Note: If we wanted to use global
variables (and a single-threaded simulator engine), then we can
create the actual variables with these names. */
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (!(STATE & simSKIPNEXT)) {
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* Include the simulator engine */
Rename generated file engine.c to oengine.c.
1997-10-16 03:39:13 +00:00
#include "oengine.c"
Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> * interp.c (sim_monitor): Improved monitor printf simulation. Tidied up simulator warnings, and added "--log" option for directing warning message output. * gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
#if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#error "Mismatch between run-time simulator code and simulation engine"
#endif
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
#if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
#error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
#endif
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
#if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
o Add support for configuring wordsize, fp hardware and target endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
#error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
#endif
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* For certain MIPS architectures, GPR[0] is hardwired to zero. We
should check for it being changed. It is better doing it here,
than within the simulator, since it will help keep the simulator
small. */
if (ZERO != 0) {
* interp.c (sim_engine_run): Reset the ZERO register to zero regardless of FEATURE_WARN_ZERO.
1997-07-02 18:13:00 +00:00
#if defined(WARN_ZERO)
Replace global IPC with function argument cia or current instruction address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
* interp.c (sim_engine_run): Reset the ZERO register to zero regardless of FEATURE_WARN_ZERO.
1997-07-02 18:13:00 +00:00
#endif /* WARN_ZERO */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
ZERO = 0; /* reset back to zero before next instruction */
}
} else /* simSKIPNEXT check */
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
STATE &= ~simSKIPNEXT;
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/* If the delay slot was active before the instruction is
executed, then update the PC to its new value: */
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
if (DSSTATE) {
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#ifdef DEBUG
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#endif /* DEBUG */
PC = DSPC;
* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1997-09-26 20:56:55 +00:00
CANCELDELAYSLOT();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
Rewrite the mipsI/II/III pending-slot code.
1998-02-02 13:49:17 +00:00
if (MIPSISA < 4)
PENDING_TICK();
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
#if !defined(FASTSIM)
Watchpoint interface.
1997-05-21 06:54:13 +00:00
if (sim_events_tickn (sd, pipeline_count))
{
/* cpu->cia = cia; */
sim_events_process (sd);
}
#else
Graft sim/common event and other code onto the mips simulator.
1997-05-19 13:30:30 +00:00
if (sim_events_tick (sd))
{
/* cpu->cia = cia; */
sim_events_process (sd);
}
Watchpoint interface.
1997-05-21 06:54:13 +00:00
#endif /* FASTSIM */
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
}
}
Separate r5900 specifoc and mips16 instructions. Add support for this to configure (vr5400 target only)
1997-10-27 07:55:24 +00:00
#endif
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
/* This code copied from gdb's utils.c. Would like to share this code,
but don't know of a common place where both could get to it. */
/* Temporary storage using circular buffer */
#define NUMCELLS 16
#define CELLSIZE 32
static char*
get_cell()
{
static char buf[NUMCELLS][CELLSIZE];
static int cell=0;
if (++cell>=NUMCELLS) cell=0;
return buf[cell];
}
/* Print routines to handle variable size regs, etc */
/* Eliminate warning from compiler on 32-bit systems */
static int thirty_two = 32;
char*
pr_addr(addr)
SIM_ADDR addr;
{
char *paddr_str=get_cell();
switch (sizeof(addr))
{
case 8:
Watchpoint interface.
1997-05-21 06:54:13 +00:00
sprintf(paddr_str,"%08lx%08lx",
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
(unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
break;
case 4:
Watchpoint interface.
1997-05-21 06:54:13 +00:00
sprintf(paddr_str,"%08lx",(unsigned long)addr);
* interp.c (sim_open): New SIM_DESC result. Argument is now in argv form. (other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
break;
case 2:
sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
break;
default:
sprintf(paddr_str,"%x",addr);
}
return paddr_str;
}
Cleanups to compile under FreeBSD
1997-04-17 06:05:19 +00:00
char*
pr_uword64(addr)
uword64 addr;
{
char *paddr_str=get_cell();
Watchpoint interface.
1997-05-21 06:54:13 +00:00
sprintf(paddr_str,"%08lx%08lx",
Cleanups to compile under FreeBSD
1997-04-17 06:05:19 +00:00
(unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
return paddr_str;
}
Rewrite the mipsI/II/III pending-slot code.
1998-02-02 13:49:17 +00:00
* gencode.c: Tidied instruction decoding, and added FP instruction support. * interp.c: Added dineroIII, and BSD profiling support. Also run-time FP handling. At the moment the options are still mostly build-time controlled, rather than run-time. Also work still needs to be done to remove (long long) usage (However this is trivial, just time-consuming). The out-standing instruction work to be done is in supporting round and trunc for FP operations, and providing better exception support.
1995-12-01 16:42:44 +00:00
/*---------------------------------------------------------------------------*/
/*> EOF interp.c <*/
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