any open file handles before exiting
* sky-gpuif.[c|h]: add disassembly on the fly code, log and log
file option support
* sky-gdb.[c|h] (sky_command_options_close()): new function, added
some body to the log and log file option sections
Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
register upon non-zero interrupt event level, clear upon zero
event value.
* dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
by passing zero event value.
(*_io_{read,write}_buffer): Endianness fixes.
* dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
(deliver_*_tick): Reduce sim event interval to 75% of count interval.
* interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
serial I/O and timer module at base address 0xFFFF0000.
It is not yet properly tested.
Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904tmr.c: New file - implements tx3904 timer.
* dv-tx3904{irc,cpu}.c: Mild reformatting.
* configure.in: Include tx3904tmr in hw_device list.
* configure: Rebuilt.
* interp.c (sim_open): Instantiate three timer instances.
Fix address typo of tx3904irc instance.
* Followup patch for SCEI PR 15853
* First check-in of TX3904 interrupt controller devices for ECC. [sanitized]
* First implementation of MIPS hardware interrupt emulation.
Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
modules. Recognize TX39 target with "mips*tx39" pattern.
* configure: Rebuilt.
* sim-main.h (*): Added many macros defining bits in
TX39 control registers.
(SignalInterrupt): Send actual PC instead of NULL.
(SignalNMIReset): New exception type.
* interp.c (board): New variable for future use to identify
a particular board being simulated.
(mips_option_handler,mips_options): Added "--board" option.
(interrupt_event): Send actual PC.
(sim_open): Make memory layout conditional on board setting.
(signal_exception): Initial implementation of hardware interrupt
handling. Accept another break instruction variant for simulator
exit.
(decode_coproc): Implement RFE instruction for TX39.
(mips.igen): Decode RFE instruction as such.
start-sanitize-tx3904
* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
* interp.c: Define "jmr3904" and "jmr3904debug" board types and
bbegin to implement memory map.
* dv-tx3904cpu.c: New file.
* dv-tx3904irc.c: New file.
end-sanitize-tx3904
[ChangeLog]
Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (decode_coproc): Add proper 1000000 bit-string at top
of VU lower instruction.
VCALLMS-related were found/fixed.
[ChangeLog.sky]
* sky-vu.c ({read,write}_vu_special_reg): Add CMSAR[01] as special
registers for a VU. Behavior not as mandated.
({read,write}_vu_{misc,special}_reg): Create sim_io_error upon
access to unknown register. Behavior not as mandated.
* sky-vu.h (anonymous register numbering enum): Add CMSAR[01].
* sky-libvpe.c (indebug): Cache $ENV{'SKY_DEBUG'}.
[ChangeLog]
* Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
* interp.c (decode_coproc): Refer to VU CIA as a "special"
register, not as a "misc" register. Aha. Add activity
assertions after VCALLMS* instructions.
work!
[ChangeLog.sky]
* sky-vu.h (vu_device): Represent "macro instruction just stuffed
into fetch buffer" condition with new "m" bit. Rename old "m" to
"l".
* sky-libvpe.c (indebug): Save snapshot of environment value;
workaround for suspected memory corruption.
(fetch_inst): Respect new "m" macro-instruction flag for reporting
successful fetch to caller.
(exec_inst): Disassemble instruction here instead of fetch time.
Renamed old "m" -> "l" flag in VU state to track interlock
release.
(vpecallms_cycle): Call exec_inst only if fetch_inst did some
work.
* sky-vu.c (vu_attach, vu[01]_device): Revamped initialization to
ensure complete clear of tail part of struct at attach time.
(vu0_busy): Fix thinko.
(vu0_macro_issue): Adapt to new "l" flag.
(vu0_micro_interlock_released): Ditto.
(write_vu_special_reg): Ditto.
(read_vu_special_reg): Compute VBS0/VBS1 bits more explicitly.
The other VU status bits are not yet computed.
[ChangeLog]
* interp.c (decode_coproc): Do not apply superfluous E (end) flag
to upper code of generated VU instruction.
masking facility for PATH3 transfers.
[ChangeLog.sky]
Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com>
* sky-libvpe.c (exec-inst): Added "M" bit detection for upper
instruction.
* sky-pke.c (pke_check_stall): Added more assertions.
(pke_code_mskpath3): Use new GPUIF M3P control register.
* sky-pke.h (VU[01]_CIA): New macros that give VU CIA
pseudo-register addresses.
* sky-vu.h (vu_device, VectorUnitState): Merged structs.
(VectorUnitState.mflag): New field.
(VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers.
* sky-vu.c (vu0_busy): New function.
(vu0_q_busy): New function.
(vu0_macro_issue): New function.
(vu0_micro_interlock_released): New function.
(vu0_busy_in_{micro,macro}_mode): Deleted stubs.
(vu0_macro_hazard_check): Deleted stubs.
(vu_attach): Adapted code to merged device & state struct.
(read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register.
[ChangeLog]
start-sanitize-sky
Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (*): Adapt code to merged VU device & state structs.
(decode_coproc): Execute COP2 each macroinstruction without
pipelining, by stepping VU to completion state. Adapted to
read_vu_*_reg style of register access.
* mips.igen ([SL]QC2): Removed these COP2 instructions.
* r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
* sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
end-sanitize-sky
into single PKE-style vu.[ch].
[ChangeLog]
Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
start-sanitize-sky
* Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
* interp.c (sim_{load,store}_register): Use new vu[01]_device
static to access VU registers.
(decode_coproc): Added skeleton of sky COP2 (VU) instruction
decoding. Work in progress.
* mips.igen (LDCzz, SDCzz): Removed *5900 case for this
overlapping/redundant bit pattern.
(LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
progress.
* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
status register.
end-sanitize-sky
* interp.c (cop_lq, cop_sq): New functions for future 128-bit
access to coprocessor registers.
* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
[ChangeLog.sky]
* sky-engine.c (engine_run): Adapted from vu[01] -> vu merge.
* sky-hardware.c (register_devices): Ditto
* sky-pke.c (pke_fifo_*): Made these functions private again, now
that the GPUIF code does not use them.
* sky-pke.h (pke_fifo_*): Removed newly private declarations.
* sky-vu.c (*): Major rework: merge of old sky-vu0.c and
sky-vu1.c. Management of two VU devices parallels two PKEs.
Work in progress.
* sky-vu.h (*): Other half of merge.
(vu_device): New struct, parallel to pke_device.
for sim/testsuite/sky:
* t-pke4.run: Removed test, since it succeeds yet returns a
non-zero exit code.
* Makefile.in (RUNOPTS): Removed --memory-size flag, made
unnecessary by sim/mips/interp.c changes.
(TESTS): Removed t-pke4.ok target.
* t-pke3.trc: Classified tests with [---] indicators, to match
items up with entries documented in testplan.sgml. Added numerous
additional tests. They assert behavior that assumes certain
favorable answers to PKE question set #6 to SCEI.
* t-pke1.trc: Added some [---] indicators.
for sim/mips:
* sky-pke.c (pke_issue): Revamped interrupt & stall code. Assume
that ER1/ER0/PIS bits are only set if not masked by ERR bits.
Signal PIS only if unmasked.
(pke_code_error): Signal ER1 only if unmasked.
(pke_pc_fifo): Signal ER0 only if unmasked.
(pke_code_unpack): Round up num_operands for last operand's
partial-word. Factor out "R" bit handling for better coverage
analysis. Fill upper words of a quadword with zeroes for Vn_m
UNPACK with n < 4.
* sky-device.c (device_error): Made function accept varargs.
* sky-device.h (device_error): Changed declaration to match.
* interp.c (sim_open): Made 0x0000 area memory be an alias of
the K0/K1 segments. Sanitized code.
little struct.
interp.c: Update. Also add floating point Max/Min functions.
mips.igen: Remove r5900 tag from any floating point instructions.
r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st).
r5400.igen: Tag mdmx functions as being mdmx specific.
update v850, tic80 and mips simulators.
IGEN - Prepend prefix to more generated symbols and macros
(idecode_issue, instruction_word).
IGEN - Add -Wnowith option to supress warnings about word size
inflicts in input files.
MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so
that a mips16 simulator built using IGEN can be compiled.
