2013-08-19 18:57:00 +00:00
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2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
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* mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
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* micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
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and OPTIONAL_MAPPED_REG.
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* mips-opc.c (decode_mips_operand): Likewise.
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* mips16-opc.c (decode_mips16_operand): Likewise.
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* mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
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2013-08-19 15:58:52 +00:00
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2013-08-19 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
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(PREFIX_EVEX_0F3A3F): Likewise.
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* i386-dis-evex.h (evex_table): Updated.
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2013-08-06 19:27:07 +00:00
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2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
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* mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
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VCLIPW.
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2013-08-05 16:11:07 +00:00
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2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
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Konrad Eisele <konrad@gaisler.com>
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* sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
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bfd_mach_sparc.
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* sparc-opc.c (MASK_LEON): Define.
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(v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
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(letandleon): New macro.
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(v9andleon): Likewise.
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(sparc_opc): Add leon.
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(umac): Enable for letandleon.
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(smac): Likewise.
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(casa): Enable for v9andleon.
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(cas): Likewise.
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(casl): Likewise.
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include/opcode/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Document new VU0 operand characters.
(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
(OP_REG_R5900_ACC): New mips_reg_operand_types.
(INSN2_VU0_CHANNEL_SUFFIX): New macro.
(mips_vu0_channel_mask): Declare.
opcodes/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(print_vu0_channel): New function.
(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(print_insn_args): Handle '#'.
(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
* mips-opc.c (mips_vu0_channel_mask): New constant.
(decode_mips_operand): Handle new VU0 operand types.
(VU0, VU0CH): New macros.
(mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
Use "+6" rather than "G" for QMFC2 and QMTC2.
gas/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
(RWARN): Bump to 0x8000000.
(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
(RTYPE_R5900_ACC): New register types.
(RTYPE_MASK): Include them.
(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
macros.
(reg_names): Include them.
(mips_parse_register_1): New function, split out from...
(mips_parse_register): ...here. Add a channels_ptr parameter.
Look for VU0 channel suffixes when nonnull.
(reg_lookup): Update the call to mips_parse_register.
(mips_parse_vu0_channels): New function.
(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
(mips_operand_token): Add a "channels" field to the union.
Extend the comment above "ch" to OT_DOUBLE_CHAR.
(mips_parse_base_start): Match -- and ++. Handle channel suffixes.
(mips_parse_argument_token): Handle channel suffixes here too.
(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
Handle '#' formats.
(md_begin): Register $vfN and $vfI registers.
(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(match_vu0_suffix_operand): New function.
(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
(mips_lookup_insn): New function.
(mips_ip): Use it. Allow "+K" operands to be elided at the end
of an instruction. Handle '#' sequences.
gas/testsuite/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
coprocessor registers.
* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
* gas/mips/mips.exp: Run them.
2013-08-04 07:31:39 +00:00
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2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
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Richard Sandiford <rdsandiford@googlemail.com>
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* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
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OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
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(print_vu0_channel): New function.
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(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
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(print_insn_args): Handle '#'.
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(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
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* mips-opc.c (mips_vu0_channel_mask): New constant.
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(decode_mips_operand): Handle new VU0 operand types.
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(VU0, VU0CH): New macros.
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(mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
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for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
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Use "+6" rather than "G" for QMFC2 and QMTC2.
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2013-08-03 10:49:48 +00:00
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2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
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* mips-formats.h (PCREL): Reorder parameters and update the definition
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to match new mips_pcrel_operand layout.
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(JUMP, JALX, BRANCH): Update accordingly.
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* mips16-opc.c (decode_mips16_operand): Likewise.
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2013-08-01 22:33:24 +00:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* micromips-opc.c (WR_s): Delete.
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include/opcode/
* mips.h (mips_decode_reg_operand): New function.
(INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
(INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
(INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
New macros.
(INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
(INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
(INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
(INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
(INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
(INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
(INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
(INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
(INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
macros to cover the gaps.
(INSN2_MOD_SP): Replace with...
(INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
(MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
(MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
(MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
(MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
Delete.
opcodes/
* mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
New macros.
(WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
(WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
(mips_builtin_opcodes): Use the new position-based read-write flags
instead of field-based ones. Use UDI for "udi..." instructions.
* mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
New macros.
(WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
(RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
(WR_SP, RD_16): New macros.
(RD_SP): Redefine as an INSN2_* flag.
(MOD_SP): Redefine in terms of RD_SP and WR_SP.
(mips16_opcodes): Use the new position-based read-write flags
instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
pinfo2 field.
* micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
New macros.
(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
(WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
(WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
(RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
(micromips_opcodes): Use the new position-based read-write flags
instead of field-based ones.
* mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
(print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
of field-based flags.
gas/
* config/tc-mips.c (MAX_OPERANDS): New macro.
(mips_operand_array): New structure.
(mips_operands, mips16_operands, micromips_operands): New arrays.
(micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map)
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map)
(micromips_to_32_reg_q_map): Delete.
(insn_operands, insn_opno, insn_extract_operand): New functions.
(validate_mips_insn): Take a mips_operand_array as argument and
use it to build up a list of operands. Extend to handle INSN_MACRO
and MIPS16.
(validate_mips16_insn): New function.
(validate_micromips_insn): Take a mips_operand_array as argument.
Handle INSN_MACRO.
(md_begin): Initialize mips_operands, mips16_operands and
micromips_operands. Call validate_mips_insn and
validate_micromips_insn for macro instructions too.
Call validate_mips16_insn for MIPS16 instructions.
(insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask):
New functions.
(gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use
them. Handle INSN_UDI.
(get_append_method): Use gpr_read_mask.
2013-08-01 20:55:25 +00:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
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New macros.
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(WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
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(WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
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(mips_builtin_opcodes): Use the new position-based read-write flags
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instead of field-based ones. Use UDI for "udi..." instructions.
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* mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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New macros.
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(WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
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(RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
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(WR_SP, RD_16): New macros.
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(RD_SP): Redefine as an INSN2_* flag.
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(MOD_SP): Redefine in terms of RD_SP and WR_SP.
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(mips16_opcodes): Use the new position-based read-write flags
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instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
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pinfo2 field.
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* micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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New macros.
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(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
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(WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
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(WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
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(RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
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(micromips_opcodes): Use the new position-based read-write flags
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instead of field-based ones.
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* mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
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(print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
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of field-based flags.
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2013-08-01 20:40:24 +00:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
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(WR_SP): Replace with...
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(MOD_SP): ...this.
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(mips16_opcodes): Update accordingly.
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* mips-dis.c (print_insn_mips16): Likewise.
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2013-08-01 20:35:11 +00:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips16-opc.c (mips16_opcodes): Reformat.
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2013-08-01 20:30:02 +00:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
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for operands that are hard-coded to $0.
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* micromips-opc.c (micromips_opcodes): Likewise.
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2013-08-01 20:25:30 +00:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
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for the single-operand forms of JALR and JALR.HB.
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* micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
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and JALRS.HB.
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2013-08-01 20:20:49 +00:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
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instructions. Fix them to use WR_MACC instead of WR_CC and
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add missing RD_MACCs.
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2013-08-01 07:13:21 +00:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
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2013-07-30 02:26:09 +00:00
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2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
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Add Intel AVX-512 support
binutils/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and
numeration in comments.
(dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to
dwarf table.
gas/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386-intel.c (O_zmmword_ptr): New.
(i386_types): Add zmmword.
(i386_intel_simplify_register): Allow regzmm.
(i386_intel_simplify): Handle zmmwords.
(i386_intel_operand): Handle RC/SAE, vector operations and
zmmwords.
* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
(struct RC_Operation): New.
(struct Mask_Operation): New.
(struct Broadcast_Operation): New.
(vex_prefix): Size of bytes increased to 4 to support EVEX
encoding.
(enum i386_error): Add new error codes: unsupported_broadcast,
broadcast_not_on_src_operand, broadcast_needed,
unsupported_masking, mask_not_on_destination, no_default_mask,
unsupported_rc_sae, rc_sae_operand_not_last_imm,
invalid_register_operand, try_vector_disp8.
(struct _i386_insn): Add new fields vrex, need_vrex, mask,
rounding, broadcast, memshift.
(struct RC_name): New.
(RC_NamesTable): New.
(evexlig): New.
(evexwig): New.
(extra_symbol_chars): Add '{'.
(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
(i386_operand_type): Add regzmm, regmask and vec_disp8.
(match_mem_size): Handle zmmwords.
(operand_type_match): Handle zmm-registers.
(mode_from_disp_size): Handle vec_disp8.
(fits_in_vec_disp8): New.
(md_begin): Handle {} properly.
(type_names): Add "rZMM", "Mask reg" and "Vector d8".
(build_vex_prefix): Handle vrex.
(build_evex_prefix): New.
(process_immext): Adjust to properly handle EVEX.
(md_assemble): Add EVEX encoding support.
(swap_2_operands): Correctly handle operands with masking,
broadcasting or RC/SAE.
(check_VecOperands): Support EVEX features.
(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
(match_template): Support regzmm and handle new error codes.
(process_suffix): Handle zmmwords and zmm-registers.
(check_byte_reg): Extend to zmm-registers.
(process_operands): Extend to zmm-registers.
(build_modrm_byte): Handle EVEX.
(output_insn): Adjust to properly handle EVEX case.
(disp_size): Handle vec_disp8.
(output_disp): Support compressed disp8*N evex feature.
(output_imm): Handle RC/SAE immediates properly.
(check_VecOperations): New.
(i386_immediate): Handle EVEX features.
(i386_index_check): Handle zmmwords and zmm-registers.
(RC_SAE_immediate): New.
(i386_att_operand): Handle EVEX features.
(parse_real_register): Add a check for ZMM/Mask registers.
(OPTION_MEVEXLIG): New.
(OPTION_MEVEXWIG): New.
(md_longopts): Add mevexlig and mevexwig.
(md_parse_option): Handle mevexlig and mevexwig options.
(md_show_usage): Add description for mevexlig and mevexwig.
* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
gas/testsuite/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/cfi/cfi-i386.s: Add tests for k0-k7.
* gas/cfi/cfi-i386.d: Change to reflect above mentioned changes.
* gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7.
* gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes.
* gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto.
* gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers.
* gas/i386/intel-regs.d: Change correspondingly.
* gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1.
* gas/i386/prefetch.d: Ditto.
* gas/i386/x86-64-prefetch-intel.d: Ditto.
* gas/i386/x86-64-prefetch.d: Ditto.
* gas/i386/avx512f-intel.d: New.
* gas/i386/avx512f-nondef.d: New.
* gas/i386/avx512f-nondef.s: New.
* gas/i386/avx512f-opts-intel.d: New.
* gas/i386/avx512f-opts.d: New.
* gas/i386/avx512f-opts.s: New.
* gas/i386/avx512f.d: New.
* gas/i386/avx512f.s: New.
* gas/i386/avx512cd-intel.d: New.
* gas/i386/avx512cd.d: New.
* gas/i386/avx512cd.s: New.
* gas/i386/avx512er-intel.d: New.
* gas/i386/avx512er.d: New.
* gas/i386/avx512er.s: New.
* gas/i386/avx512pf-intel.d: New.
* gas/i386/avx512pf.d: New.
* gas/i386/avx512pf.s: New.
* gas/i386/evex-lig.s: New.
* gas/i386/evex-lig256-intel.d: New.
* gas/i386/evex-lig256.d: New.
* gas/i386/evex-lig512-intel.d: New.
* gas/i386/evex-lig512.d: New.
* gas/i386/evex-wig.s: New.
* gas/i386/evex-wig1-intel.d: New.
* gas/i386/evex-wig1.d: New.
* gas/i386/inval-avx512f.l: New.
* gas/i386/inval-avx512f.s: New.
* gas/i386/x86-64-avx512f-intel.d: New.
* gas/i386/x86-64-avx512f-nondef.d: New.
* gas/i386/x86-64-avx512f-nondef.s: New.
* gas/i386/x86-64-avx512f-opts-intel.d: New.
* gas/i386/x86-64-avx512f-opts.d: New.
* gas/i386/x86-64-avx512f-opts.s: New.
* gas/i386/x86-64-avx512f.d: New.
* gas/i386/x86-64-avx512f.s: New.
* gas/i386/x86-64-avx512cd-intel.d: New.
* gas/i386/x86-64-avx512cd.d: New.
* gas/i386/x86-64-avx512cd.s: New.
* gas/i386/x86-64-avx512er-intel.d: New.
* gas/i386/x86-64-avx512er.d: New.
* gas/i386/x86-64-avx512er.s: New.
* gas/i386/x86-64-avx512pf-intel.d: New.
* gas/i386/x86-64-avx512pf.d: New.
* gas/i386/x86-64-avx512pf.s: New.
* gas/i386/x86-64-evex-lig.s: New.
* gas/i386/x86-64-evex-lig256-intel.d: New.
* gas/i386/x86-64-evex-lig256.d: New.
* gas/i386/x86-64-evex-lig512-intel.d: New.
* gas/i386/x86-64-evex-lig512.d: New.
* gas/i386/x86-64-evex-wig.s: New.
* gas/i386/x86-64-evex-wig1-intel.d: New.
* gas/i386/x86-64-evex-wig1.d: New.
* gas/i386/x86-64-inval-avx512f.l: New.
* gas/i386/x86-64-inval-avx512f.s: New.
* gas/i386/i386.exp: Run new AVX-512 tests.
opcodes/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis-evex.h: New.
* i386-dis.c (OP_Rounding): New.
(VPCMP_Fixup): New.
(OP_Mask): New.
(Rdq): New.
(XMxmmq): New.
(EXdScalarS): New.
(EXymm): New.
(EXEvexHalfBcstXmmq): New.
(EXxmm_mdq): New.
(EXEvexXGscat): New.
(EXEvexXNoBcst): New.
(VPCMP): New.
(EXxEVexR): New.
(EXxEVexS): New.
(XMask): New.
(MaskG): New.
(MaskE): New.
(MaskR): New.
(MaskVex): New.
(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
evex_rounding_mode, evex_sae_mode, mask_mode.
(USE_EVEX_TABLE): New.
(EVEX_TABLE): New.
(EVEX enum): New.
(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
REG_EVEX_0F38C7.
(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
MOD_EVEX_0F38C7_REG_6.
(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
PREFIX_EVEX_0F3A55.
(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0.
(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
(struct vex): Add fields evex, r, v, mask_register_specifier,
zeroing, ll, b.
(intel_names_xmm): Add upper 16 registers.
(att_names_xmm): Ditto.
(intel_names_ymm): Ditto.
(att_names_ymm): Ditto.
(names_zmm): New.
(intel_names_zmm): Ditto.
(att_names_zmm): Ditto.
(names_mask): Ditto.
(intel_names_mask): Ditto.
(att_names_mask): Ditto.
(names_rounding): Ditto.
(names_broadcast): Ditto.
(x86_64_table): Add escape to evex-table.
(reg_table): Include reg_table evex-entries from
i386-dis-evex.h. Fix prefetchwt1 instruction.
(prefix_table): Add entries for new instructions.
(vex_table): Ditto.
(vex_len_table): Ditto.
(vex_w_table): Ditto.
(mod_table): Ditto.
(get_valid_dis386): Properly handle new instructions.
(print_insn): Handle zmm and mask registers, print mask operand.
(intel_operand_size): Support EVEX, new modes and sizes.
(OP_E_register): Handle new modes.
(OP_E_memory): Ditto.
(OP_G): Ditto.
(OP_XMM): Ditto.
(OP_EX): Ditto.
(OP_VEX): Ditto.
* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
CpuAVX512PF and CpuVREX.
(operand_type_init): Add OPERAND_TYPE_REGZMM,
OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
StaticRounding, SAE, Disp8MemShift, NoDefMask.
(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
* i386-init.h: Regenerate.
* i386-opc.h (CpuAVX512F): New.
(CpuAVX512CD): New.
(CpuAVX512ER): New.
(CpuAVX512PF): New.
(CpuVREX): New.
(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
cpuavx512pf and cpuvrex fields.
(VecSIB): Add VecSIB512.
(EVex): New.
(Masking): New.
(VecESize): New.
(Broadcast): New.
(StaticRounding): New.
(SAE): New.
(Disp8MemShift): New.
(NoDefMask): New.
(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
staticrounding, sae, disp8memshift and nodefmask.
(RegZMM): New.
(Zmmword): Ditto.
(Vec_Disp8): Ditto.
(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
fields.
(RegVRex): New.
* i386-opc.tbl: Add AVX512 instructions.
* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
registers, mask registers.
* i386-tbl.h: Regenerate.
2013-07-26 17:20:25 +00:00
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2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
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Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Sergey Lega <sergey.s.lega@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* i386-dis-evex.h: New.
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* i386-dis.c (OP_Rounding): New.
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(VPCMP_Fixup): New.
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(OP_Mask): New.
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(Rdq): New.
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(XMxmmq): New.
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(EXdScalarS): New.
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(EXymm): New.
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(EXEvexHalfBcstXmmq): New.
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(EXxmm_mdq): New.
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(EXEvexXGscat): New.
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(EXEvexXNoBcst): New.
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(VPCMP): New.
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(EXxEVexR): New.
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(EXxEVexS): New.
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(XMask): New.
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(MaskG): New.
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(MaskE): New.
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(MaskR): New.
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(MaskVex): New.
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(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
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evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
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evex_rounding_mode, evex_sae_mode, mask_mode.
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(USE_EVEX_TABLE): New.
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(EVEX_TABLE): New.
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(EVEX enum): New.
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(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
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REG_EVEX_0F38C7.
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(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
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MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
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MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
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MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
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MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
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MOD_EVEX_0F38C7_REG_6.
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(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
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PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
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PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
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PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
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PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
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PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
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PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
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PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
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PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
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PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
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PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
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PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
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PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
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PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
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PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
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PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
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PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
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PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
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PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
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PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
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PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
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PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
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PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
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PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
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PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
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PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
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PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
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PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
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PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
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PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
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PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
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PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
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PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
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PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
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PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
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PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
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PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
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PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
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PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
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PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
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PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
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PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
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PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
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PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
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PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
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PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
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PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
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PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
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PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
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PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
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PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
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PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
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PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
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PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
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PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
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PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
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PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
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PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
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PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
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PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
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PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
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PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
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PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
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PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
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PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
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PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
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PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
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PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
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PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
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PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
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PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
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PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
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PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
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PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
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PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
|
|
|
|
|
|
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
|
|
|
|
|
|
PREFIX_EVEX_0F3A55.
|
|
|
|
|
|
(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
|
|
|
|
|
|
VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
|
|
|
|
|
|
VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
|
|
|
|
|
|
VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
|
|
|
|
|
|
VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
|
|
|
|
|
|
VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
|
|
|
|
|
|
VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
|
|
|
|
|
|
VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
|
|
|
|
|
|
VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
|
|
|
|
|
|
VEX_W_0F3A32_P_2_LEN_0.
|
|
|
|
|
|
(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
|
|
|
|
|
|
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
|
|
|
|
|
|
EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
|
|
|
|
|
|
EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
|
|
|
|
|
|
EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
|
|
|
|
|
|
EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
|
|
|
|
|
|
EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
|
|
|
|
|
|
EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
|
|
|
|
|
|
EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
|
|
|
|
|
|
EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
|
|
|
|
|
|
EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
|
|
|
|
|
|
EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
|
|
|
|
|
|
EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
|
|
|
|
|
|
EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
|
|
|
|
|
|
EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
|
|
|
|
|
|
EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
|
|
|
|
|
|
EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
|
|
|
|
|
|
EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
|
|
|
|
|
|
EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
|
|
|
|
|
|
EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
|
|
|
|
|
|
EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
|
|
|
|
|
|
EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
|
|
|
|
|
|
EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
|
|
|
|
|
|
EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
|
|
|
|
|
|
EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
|
|
|
|
|
|
EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
|
|
|
|
|
|
EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
|
|
|
|
|
|
EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
|
|
|
|
|
|
EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
|
|
|
|
|
|
EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
|
|
|
|
|
|
EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
|
|
|
|
|
|
EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
|
|
|
|
|
|
EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
|
|
|
|
|
|
EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
|
|
|
|
|
|
EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
|
|
|
|
|
|
EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
|
|
|
|
|
|
EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
|
|
|
|
|
|
EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
|
|
|
|
|
|
EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
|
|
|
|
|
|
EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
|
|
|
|
|
|
EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
|
|
|
|
|
|
EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
|
|
|
|
|
|
EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
|
|
|
|
|
|
EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
|
|
|
|
|
|
EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
|
|
|
|
|
|
EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
|
|
|
|
|
|
EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
|
|
|
|
|
|
EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
|
|
|
|
|
|
EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
|
|
|
|
|
|
EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
|
|
|
|
|
|
EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
|
|
|
|
|
|
EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
|
|
|
|
|
|
EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
|
|
|
|
|
|
EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
|
|
|
|
|
|
(struct vex): Add fields evex, r, v, mask_register_specifier,
|
|
|
|
|
|
zeroing, ll, b.
|
|
|
|
|
|
(intel_names_xmm): Add upper 16 registers.
|
|
|
|
|
|
(att_names_xmm): Ditto.
|
|
|
|
|
|
(intel_names_ymm): Ditto.
|
|
|
|
|
|
(att_names_ymm): Ditto.
|
|
|
|
|
|
(names_zmm): New.
|
|
|
|
|
|
(intel_names_zmm): Ditto.
|
|
|
|
|
|
(att_names_zmm): Ditto.
|
|
|
|
|
|
(names_mask): Ditto.
|
|
|
|
|
|
(intel_names_mask): Ditto.
|
|
|
|
|
|
(att_names_mask): Ditto.
|
|
|
|
|
|
(names_rounding): Ditto.
|
|
|
|
|
|
(names_broadcast): Ditto.
|
|
|
|
|
|
(x86_64_table): Add escape to evex-table.
|
|
|
|
|
|
(reg_table): Include reg_table evex-entries from
|
|
|
|
|
|
i386-dis-evex.h. Fix prefetchwt1 instruction.
|
|
|
|
|
|
(prefix_table): Add entries for new instructions.
|
|
|
|
|
|
(vex_table): Ditto.
|
|
|
|
|
|
(vex_len_table): Ditto.
|
|
|
|
|
|
(vex_w_table): Ditto.
|
|
|
|
|
|
(mod_table): Ditto.
|
|
|
|
|
|
(get_valid_dis386): Properly handle new instructions.
|
|
|
|
|
|
(print_insn): Handle zmm and mask registers, print mask operand.
|
|
|
|
|
|
(intel_operand_size): Support EVEX, new modes and sizes.
|
|
|
|
|
|
(OP_E_register): Handle new modes.
|
|
|
|
|
|
(OP_E_memory): Ditto.
|
|
|
|
|
|
(OP_G): Ditto.
|
|
|
|
|
|
(OP_XMM): Ditto.
|
|
|
|
|
|
(OP_EX): Ditto.
|
|
|
|
|
|
(OP_VEX): Ditto.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
|
|
|
|
|
|
CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
|
|
|
|
|
|
CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
|
|
|
|
|
|
CpuAVX512PF and CpuVREX.
|
|
|
|
|
|
(operand_type_init): Add OPERAND_TYPE_REGZMM,
|
|
|
|
|
|
OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
|
|
|
|
|
|
(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
|
|
|
|
|
|
StaticRounding, SAE, Disp8MemShift, NoDefMask.
|
|
|
|
|
|
(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-opc.h (CpuAVX512F): New.
|
|
|
|
|
|
(CpuAVX512CD): New.
|
|
|
|
|
|
(CpuAVX512ER): New.
|
|
|
|
|
|
(CpuAVX512PF): New.
|
|
|
|
|
|
(CpuVREX): New.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
|
|
|
|
|
|
cpuavx512pf and cpuvrex fields.
|
|
|
|
|
|
(VecSIB): Add VecSIB512.
|
|
|
|
|
|
(EVex): New.
|
|
|
|
|
|
(Masking): New.
|
|
|
|
|
|
(VecESize): New.
|
|
|
|
|
|
(Broadcast): New.
|
|
|
|
|
|
(StaticRounding): New.
|
|
|
|
|
|
(SAE): New.
|
|
|
|
|
|
(Disp8MemShift): New.
|
|
|
|
|
|
(NoDefMask): New.
|
|
|
|
|
|
(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
|
|
|
|
|
|
staticrounding, sae, disp8memshift and nodefmask.
|
|
|
|
|
|
(RegZMM): New.
|
|
|
|
|
|
(Zmmword): Ditto.
|
|
|
|
|
|
(Vec_Disp8): Ditto.
|
|
|
|
|
|
(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
|
|
|
|
|
|
fields.
|
|
|
|
|
|
(RegVRex): New.
|
|
|
|
|
|
* i386-opc.tbl: Add AVX512 instructions.
|
|
|
|
|
|
* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
|
|
|
|
|
|
registers, mask registers.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2013-07-25 19:11:39 +00:00
|
|
|
|
2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15220
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
|
|
|
|
|
|
Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
|
|
|
|
|
|
|
2013-07-25 16:16:35 +00:00
|
|
|
|
2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
|
|
|
|
|
|
PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
|
|
|
|
|
|
PREFIX_0F3ACC.
|
|
|
|
|
|
(prefix_table): Updated.
|
|
|
|
|
|
(three_byte_table): Likewise.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuSHA.
|
|
|
|
|
|
(i386_cpu_flags): Add cpusha.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-opc.h (CpuSHA): New.
|
|
|
|
|
|
(CpuUnused): Restored.
|
|
|
|
|
|
(i386_cpu_flags): Add cpusha.
|
|
|
|
|
|
* i386-opc.tbl: Add SHA instructions.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2013-07-24 15:47:25 +00:00
|
|
|
|
2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
|
|
|
|
|
|
Kirill Yukhin <kirill.yukhin@intel.com>
|
|
|
|
|
|
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (BND_Fixup): New.
|
|
|
|
|
|
(Ebnd): New.
|
|
|
|
|
|
(Ev_bnd): New.
|
|
|
|
|
|
(Gbnd): New.
|
|
|
|
|
|
(BND): New.
|
|
|
|
|
|
(v_bnd_mode): New.
|
|
|
|
|
|
(bnd_mode): New.
|
2013-07-25 16:09:09 +00:00
|
|
|
|
(MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
|
|
|
|
|
|
MOD_0F1B_PREFIX_1.
|
|
|
|
|
|
(PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
|
2013-07-24 15:47:25 +00:00
|
|
|
|
(dis tables): Replace XX with BND for near branch and call
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
(prefix_table): Add new entries.
|
|
|
|
|
|
(mod_table): Likewise.
|
|
|
|
|
|
(names_bnd): New.
|
|
|
|
|
|
(intel_names_bnd): New.
|
|
|
|
|
|
(att_names_bnd): New.
|
|
|
|
|
|
(BND_PREFIX): New.
|
|
|
|
|
|
(prefix_name): Handle BND_PREFIX.
|
|
|
|
|
|
(print_insn): Initialize names_bnd.
|
|
|
|
|
|
(intel_operand_size): Handle new modes.
|
|
|
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|
|
(OP_E_register): Likewise.
|
|
|
|
|
|
(OP_E_memory): Likewise.
|
|
|
|
|
|
(OP_G): Likewise.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CpuMPX.
|
|
|
|
|
|
(cpu_flags): Add CpuMPX.
|
|
|
|
|
|
(operand_type_init): Add RegBND.
|
|
|
|
|
|
(opcode_modifiers): Add BNDPrefixOk.
|
|
|
|
|
|
(operand_types): Add RegBND.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-opc.h (CpuMPX): New.
|
|
|
|
|
|
(CpuUnused): Comment out.
|
|
|
|
|
|
(i386_cpu_flags): Add cpumpx.
|
|
|
|
|
|
(BNDPrefixOk): New.
|
|
|
|
|
|
(i386_opcode_modifier): Add bndprefixok.
|
|
|
|
|
|
(RegBND): New.
|
|
|
|
|
|
(i386_operand_type): Add regbnd.
|
|
|
|
|
|
* i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
|
|
|
|
|
|
Add MPX instructions and bnd prefix.
|
|
|
|
|
|
* i386-reg.tbl: Add bnd0-bnd3 registers.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2013-07-17 08:06:11 +00:00
|
|
|
|
2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
|
|
|
|
|
|
ATTRIBUTE_UNUSED.
|
|
|
|
|
|
|
2013-07-14 14:25:57 +00:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
|
|
|
|
|
|
special rules.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
|
|
|
|
|
|
all fields. Reformat.
|
|
|
|
|
|
|
2013-07-14 13:36:51 +00:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips16-opc.c: Include mips-formats.h.
|
|
|
|
|
|
(reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
|
|
|
|
|
|
static arrays.
|
|
|
|
|
|
(decode_mips16_operand): New function.
|
|
|
|
|
|
* mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
|
|
|
|
|
|
(print_insn_arg): Handle OP_ENTRY_EXIT list.
|
|
|
|
|
|
Abort for OP_SAVE_RESTORE_LIST.
|
|
|
|
|
|
(print_mips16_insn_arg): Change interface. Use mips_operand
|
|
|
|
|
|
structures. Delete GET_OP_S. Move GET_OP definition to...
|
|
|
|
|
|
(print_insn_mips16): ...here. Call init_print_arg_state.
|
|
|
|
|
|
Update the call to print_mips16_insn_arg.
|
|
|
|
|
|
|
include/opcode/
* mips.h (mips_operand_type, mips_reg_operand_type): New enums.
(mips_operand, mips_int_operand, mips_mapped_int_operand)
(mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
(mips_pcrel_operand): New structures.
(mips_insert_operand, mips_extract_operand, mips_signed_operand)
(mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
(decode_mips_operand, decode_micromips_operand): Declare.
opcodes/
* mips-formats.h: New file.
* mips-opc.c: Include mips-formats.h.
(reg_0_map): New static array.
(decode_mips_operand): New function.
* micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
(reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
(reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
(int_c_map): New static arrays.
(decode_micromips_operand): New function.
* mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
(micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
(micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
(micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
(micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
(micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
(micromips_imm_b_map, micromips_imm_c_map): Delete.
(print_reg): New function.
(mips_print_arg_state): New structure.
(init_print_arg_state, print_insn_arg): New functions.
(print_insn_args): Change interface and use mips_operand structures.
Delete GET_OP_S. Move GET_OP definition to...
(print_insn_mips): ...here. Update the call to print_insn_args.
(print_insn_micromips): Use print_insn_args.
gas/
* config/tc-mips.c (validate_mips_insn): Move further up file.
Add insn_bits and decode_operand arguments. Use the mips_operand
fields to work out which bits an operand occupies. Detect double
definitions.
(validate_micromips_insn): Move further up file. Call into
validate_mips_insn.
2013-07-14 13:28:56 +00:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-formats.h: New file.
|
|
|
|
|
|
* mips-opc.c: Include mips-formats.h.
|
|
|
|
|
|
(reg_0_map): New static array.
|
|
|
|
|
|
(decode_mips_operand): New function.
|
|
|
|
|
|
* micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
|
|
|
|
|
|
(reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
|
|
|
|
|
|
(reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
|
|
|
|
|
|
(int_c_map): New static arrays.
|
|
|
|
|
|
(decode_micromips_operand): New function.
|
|
|
|
|
|
* mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
|
|
|
|
|
|
(micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
|
|
|
|
|
|
(micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
|
|
|
|
|
|
(micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
|
|
|
|
|
|
(micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
|
|
|
|
|
|
(micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
|
|
|
|
|
|
(micromips_imm_b_map, micromips_imm_c_map): Delete.
|
|
|
|
|
|
(print_reg): New function.
|
|
|
|
|
|
(mips_print_arg_state): New structure.
|
|
|
|
|
|
(init_print_arg_state, print_insn_arg): New functions.
|
|
|
|
|
|
(print_insn_args): Change interface and use mips_operand structures.
|
|
|
|
|
|
Delete GET_OP_S. Move GET_OP definition to...
|
|
|
|
|
|
(print_insn_mips): ...here. Update the call to print_insn_args.
|
|
|
|
|
|
(print_insn_micromips): Use print_insn_args.
|
|
|
|
|
|
|
2013-07-14 13:11:03 +00:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
|
|
|
|
|
|
in macros.
|
|
|
|
|
|
|
2013-07-14 13:07:50 +00:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
|
|
|
|
|
|
ADDA.S, MULA.S and SUBA.S.
|
|
|
|
|
|
|
2013-07-08 16:24:21 +00:00
|
|
|
|
2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/13572
|
|
|
|
|
|
* i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
include/opcode/
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
Rename to...
(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
(M_USD_AB): ...these.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
and SD A(B) macros up.
* micromips-opc.c (micromips_opcodes): Likewise.
gas/
* config/tc-mips.c (gprel16_reloc_p): New function.
(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
BFD_RELOC_UNUSED.
(offset_high_part, small_offset_p): New functions.
(nacro): Use them. Remove *_OB and *_DOB cases. For single-
register load and store macros, handle the 16-bit offset case first.
If a 16-bit offset is not suitable for the instruction we're
generating, load it into the temporary register using
ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
M_L_DAB code once the address has been constructed. For double load
and store macros, again handle the 16-bit offset case first.
If the second register cannot be accessed from the same high
part as the first, load it into AT using ADDRESS_ADDI_INSN.
Fix the handling of LD in cases where the first register is the
same as the base. Also handle the case where the offset is
not 16 bits and the second register cannot be accessed from the
same high part as the first. For unaligned loads and stores,
fuse the offbits == 12 and old "ab" handling. Apply this handling
whenever the second offset needs a different high part from the first.
Construct the offset using ADDRESS_ADDI_INSN where possible,
for offbits == 16 as well as offbits == 12. Use offset_reloc
when constructing the individual loads and stores.
(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
and offset_reloc before matching against a particular opcode.
Handle elided 'A' constants. Allow 'A' constants to use
relocation operators.
gas/testsuite/
* gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for
truncated constants.
* gas/mips/ldstla-32-shared.d: Likewise.
* gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding
16-bit constants to the base.
* gas/mips/micromips@mcu.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips.d, gas/mips/micromips-insn32.d,
gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise.
Allow the full 16-bit offset range to be used for SB, LB and LBU in
USH and ULH sequences. Fix the expected output for LD and SD when
the two LW and SW offsets need different high parts.
* gas/mips/eva.s: Test PREFE with relocation operators.
* gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit
constants. Update after eva.s change.
* gas/mips/micromips@eva.d: Likewise.
* gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s,
gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d,
gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s,
gas/mips/ulh-reloc.d: New tests.
* gas/mips/mips.exp: Run them.
2013-07-07 11:32:32 +00:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
|
|
|
|
|
|
and SD A(B) macros up.
|
|
|
|
|
|
* micromips-opc.c (micromips_opcodes): Likewise.
|
|
|
|
|
|
|
2013-07-07 10:27:32 +00:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips16-opc.c: Add entries for argumentless "entry" and "exit"
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
|
2013-07-07 10:15:09 +00:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
|
|
|
|
|
|
MDMX-like instructions.
|
|
|
|
|
|
* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
|
|
|
|
|
|
printing "Q" operands for INSN_5400 instructions.
|
|
|
|
|
|
|
2013-07-07 10:00:43 +00:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
|
|
|
|
|
|
"+S" for "cins".
|
|
|
|
|
|
* mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
|
|
|
|
|
|
Combine cases.
|
|
|
|
|
|
|
2013-07-07 09:50:43 +00:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
|
|
|
|
|
|
"jalx".
|
|
|
|
|
|
* mips16-opc.c (mips16_opcodes): Likewise.
|
|
|
|
|
|
* micromips-opc.c (micromips_opcodes): Likewise.
|
|
|
|
|
|
* mips-dis.c (print_insn_args, print_mips16_insn_arg)
|
|
|
|
|
|
(print_insn_mips16): Handle "+i".
|
|
|
|
|
|
(print_insn_micromips): Likewise. Conditionally preserve the
|
|
|
|
|
|
ISA bit for "a" but not for "+i".
|
|
|
|
|
|
|
2013-07-07 09:41:04 +00:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* micromips-opc.c (WR_mhi): Rename to..
|
|
|
|
|
|
(WR_mh): ...this.
|
|
|
|
|
|
(micromips_opcodes): Update "movep" entry accordingly. Replace
|
|
|
|
|
|
"mh,mi" with "mh".
|
|
|
|
|
|
* mips-dis.c (micromips_to_32_reg_h_map): Rename to...
|
|
|
|
|
|
(micromips_to_32_reg_h_map1): ...this.
|
|
|
|
|
|
(micromips_to_32_reg_i_map): Rename to...
|
|
|
|
|
|
(micromips_to_32_reg_h_map2): ...this.
|
|
|
|
|
|
(print_micromips_insn): Remove "mi" case. Print both registers
|
|
|
|
|
|
in the pair for "mh".
|
|
|
|
|
|
|
2013-07-07 09:32:55 +00:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
|
|
|
|
|
|
* micromips-opc.c (micromips_opcodes): Likewise.
|
|
|
|
|
|
* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
|
|
|
|
|
|
and "+T" handling. Check for a "0" suffix when deciding whether to
|
|
|
|
|
|
use coprocessor 0 names. In that case, also check for ",H" selectors.
|
|
|
|
|
|
|
2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
opcodes/
* s390-opc.c (J12_12, J24_24): New macros.
(INSTR_MII_UPI): Rename to INSTR_MII_UPP.
(MASK_MII_UPI): Rename to MASK_MII_UPP.
* s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
include/elf/
* s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL,
R_390_PC24DBL, and R_390_PLT24DBL.
gas/testsuite/
* gas/s390/zarch-zEC12.s: Change bprp second operand and add
variants requiring relocations.
* gas/s390/zarch-zEC12.d: Likewise.
gas/
* config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
relocs.
bfd/
* elf32-s390.c: Add new relocation definitions R_390_PC12DBL,
R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL.
(elf_s390_reloc_type_lookup, elf_s390_check_relocs)
(elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new
relocations.
* elf64-s390.c: See elf32-s390.c
* bfd-in2.h: Add new relocs to enum bfd_reloc_code_real.
* libbfd.h: Add new reloc strings.
2013-07-05 09:45:44 +00:00
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2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* s390-opc.c (J12_12, J24_24): New macros.
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(INSTR_MII_UPI): Rename to INSTR_MII_UPP.
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(MASK_MII_UPI): Rename to MASK_MII_UPP.
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* s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
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2013-07-04 01:42:08 +00:00
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2013-07-04 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
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2013-06-26 10:31:38 +00:00
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2013-06-26 Nick Clifton <nickc@redhat.com>
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* rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
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field when checking for type 2 nop.
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* rx-decode.c: Regenerate.
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bfd/
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype.
* elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member.
(STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros.
(MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise.
(MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise.
(micromips_insn32_o32_exec_plt0_entry): New variable.
(micromips_insn32_o32_exec_plt_entry): Likewise.
(_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode.
(mips_elf_estimate_stub_size): Likewise.
(_bfd_mips_elf_size_dynamic_sections): Likewise.
(_bfd_mips_elf_finish_dynamic_symbol): Likewise.
(mips_finish_exec_plt): Likewise.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_insn32): New function.
(_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT.
gas/
* config/tc-mips.c (mips_set_options): Add insn32 member.
(mips_opts): Initialize it.
(NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
(options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
(md_longopts): Add "minsn32" and "mno-insn32" options.
(is_size_valid): Handle insn32 mode.
(md_assemble): Pass instruction string down to macro.
(brk_fmt): Add second dimension and insn32 mode initializers.
(mfhl_fmt): Likewise.
(BRK_FMT, MFHL_FMT): Handle insn32 mode.
(macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
(macro_build_jalr, move_register): Handle insn32 mode.
(macro_build_branch_rs): Likewise.
(macro): Handle insn32 mode.
<M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
(mips_ip): Handle insn32 mode.
(md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
(s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
(mips_handle_align): Handle insn32 mode.
(md_show_usage): Add -minsn32 and -mno-insn32.
* doc/as.texinfo (Target MIPS options): Add -minsn32 and
-mno-insn32 options.
(-minsn32, -mno-insn32): New options.
* doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
options.
(MIPS assembly options): New node. Document .set insn32 and
.set noinsn32.
(MIPS-Dependent): List the new node.
gas/testsuite/
* gas/mips/micromips-insn32.d: New test.
* gas/mips/micromips-noinsn32.d: Likewise.
* gas/mips/micromips.l: Rename to...
* gas/mips/micromips-warn.l: ... this.
* gas/mips/micromips.d: Update accordingly.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New list test.
* gas/mips/micromips.s: Add conditionals.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
values.
ld/
* emultempl/mipself.em (insn32): New variable.
(mips_create_output_section_statements): Handle insn32 mode.
(PARSE_AND_LIST_PROLOGUE): New macro.
(PARSE_AND_LIST_LONGOPTS): Likewise.
(PARSE_AND_LIST_OPTIONS): Likewise.
* gen-doc.texi: Set MIPS.
* ld.texinfo: Likewise.
(Options specific to MIPS targets): New section.
(ld and MIPS family): New node.
(Top, Machine Dependent): List the new node.
opcodes/
* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
and "movep" macros.
2013-06-25 18:02:34 +00:00
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2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
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* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
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and "movep" macros.
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2013-06-24 23:55:46 +00:00
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2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-dis.c (is_mips16_plt_tail): New function.
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(print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
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word.
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(is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
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2013-06-21 15:01:57 +00:00
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2013-06-21 DJ Delorie <dj@redhat.com>
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* msp430-decode.opc: New.
|
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* msp430-decode.c: New/generated.
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* Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
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(MAINTAINER_CLEANFILES): Likewise.
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Add rule to build msp430-decode.c frommsp430decode.opc
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using the opc2c program.
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* Makefile.in: Regenerate.
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* configure.in: Add msp430-decode.lo to msp430 architecture files.
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* configure: Regenerate.
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2013-06-20 16:01:35 +00:00
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2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
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(SYMTAB_AVAILABLE): Removed.
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(#include "elf/aarch64.h): Ditto.
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2013-06-17 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Chao-Ying Fu <fu@mips.com>
gas/testsuite/
* gas/mips/mips.exp: Run new tests.
* gas/mips/eva.d: New.
* gas/mips/eva.s: New.
* gas/mips/micromips@eva.d: New.
gas/
* config/tc-mips.c (mips_set_options): Add ase_eva.
(mips_set_options mips_opts): Add ase_eva.
(file_ase_eva): Declare.
(ISA_SUPPORTS_EVA_ASE): Define.
(IS_SEXT_9BIT_NUM): Define.
(MIPS_CPU_ASE_EVA): Define.
(is_opcode_valid): Add support for ase_eva.
(macro_build): Likewise.
(macro): Likewise.
(validate_mips_insn): Likewise.
(validate_micromips_insn): Likewise.
(mips_ip): Likewise.
(options): Add OPTION_EVA and OPTION_NO_EVA.
(md_longopts): Add -meva and -mno-eva.
(md_parse_option): Process new options.
(mips_after_parse_args): Check for valid EVA combinations.
(s_mipsset): Likewise.
include/
* opcode/mips.h (OP_SH_EVAOFFSET): Define.
(OP_MASK_EVAOFFSET): Define.
(INSN_ASE_MASK): Delete.
(ASE_EVA): Define.
(M_CACHEE_AB, M_CACHEE_OB): New.
(M_LBE_OB, M_LBE_AB): New.
(M_LBUE_OB, M_LBUE_AB): New.
(M_LHE_OB, M_LHE_AB): New.
(M_LHUE_OB, M_LHUE_AB): New.
(M_LLE_AB, M_LLE_OB): New.
(M_LWE_OB, M_LWE_AB): New.
(M_LWLE_AB, M_LWLE_OB): New.
(M_LWRE_AB, M_LWRE_OB): New.
(M_PREFE_AB, M_PREFE_OB): New.
(M_SCE_AB, M_SCE_OB): New.
(M_SBE_OB, M_SBE_AB): New.
(M_SHE_OB, M_SHE_AB): New.
(M_SWE_OB, M_SWE_AB): New.
(M_SWLE_AB, M_SWLE_OB): New.
(M_SWRE_AB, M_SWRE_OB): New.
(MICROMIPSOP_SH_EVAOFFSET): Define.
(MICROMIPSOP_MASK_EVAOFFSET): Define.
opcodes/
* micromips-opc.c (EVA): Define.
(TLBINV): Define.
(micromips_opcodes): Add EVA opcodes.
* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
(print_insn_args): Handle EVA offsets.
(print_insn_micromips): Likewise.
* mips-opc.c (EVA): Define.
(TLBINV): Define.
(mips_builtin_opcodes): Add EVA opcodes.
2013-06-17 22:59:10 +00:00
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2013-06-17 Catherine Moore <clm@codesourcery.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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Chao-Ying Fu <fu@mips.com>
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* micromips-opc.c (EVA): Define.
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(TLBINV): Define.
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(micromips_opcodes): Add EVA opcodes.
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* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
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(print_insn_args): Handle EVA offsets.
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(print_insn_micromips): Likewise.
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* mips-opc.c (EVA): Define.
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(TLBINV): Define.
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(mips_builtin_opcodes): Add EVA opcodes.
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2013-06-17 11:51:13 +00:00
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2013-06-17 Alan Modra <amodra@gmail.com>
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* Makefile.am (mips-opc.lo): Add rules to create automatic
|
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dependency files. Pass archdefs.
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(micromips-opc.lo, mips16-opc.lo): Likewise.
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* Makefile.in: Regenerate.
|
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2013-06-14 19:57:10 +00:00
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2013-06-14 DJ Delorie <dj@redhat.com>
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* rx-decode.opc (rx_decode_opcode): Bit operations on
|
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registers are 32-bit operations, not 8-bit operations.
|
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* rx-decode.c: Regenerate.
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2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* micromips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
* mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
dmtgc0 to print cp0 names.
2013-06-13 21:01:44 +00:00
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2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
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* micromips-opc.c (IVIRT): New define.
|
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(IVIRT64): New define.
|
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(micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
|
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|
tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
|
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* mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
|
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|
dmtgc0 to print cp0 names.
|
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2013-06-10 01:04:42 +00:00
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2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
|
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* nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
|
|
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|
|
argument.
|
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|
|
gas/
2013-06-08 Catherine Moore <clm@codesourcery.com>
* config/tc-mips.c (is_opcode_valid): Build ASE mask.
(is_opcode_valid_16): Pass ase value to opcode_is_member.
(append_insn): Change INSN_xxxx to ASE_xxxx.
include/
2013-06-08 Catherine Moore <clm@codesourcery.com>
* opcode/mips.h (mips_opcode): Add ase field.
(INSN_ASE_MASK): Delete.
(INSN_DSP): Rename to ASE_DSP. Provide new value.
(INSN_DSPR2): Rename to ASE_DSPR2. Provide new value.
(INSN_MCU): Rename to ASE_MCU. Provide new value.
(INSN_MDMX): Rename to ASE_MDMX. Provide new value.
(INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value.
(INSN_MT): Rename to ASE_MT. Provide new value.
(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value.
(INSN_VIRT): Rename to ASE_VIRT. Provide new value.
(INSN_VIRT64): Rename to ASE_VIRT64. Provide new value.
(opcode_is_member): Add ase argument. Check ase.
opcodes/
2013-06-08 Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* micromips-opc.c (D32, D33, MC): Update definitions.
(micromips_opcodes): Initialize ase field.
* mips-dis.c (mips_arch_choice): Add ase field.
(mips_arch_choices): Initialize ase field.
(set_default_mips_dis_options): Declare and setup mips_ase.
* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
MT32, MC): Update definitions.
(mips_builtin_opcodes): Initialize ase field.
2013-06-08 10:22:55 +00:00
|
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|
2013-06-08 Catherine Moore <clm@codesourcery.com>
|
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Richard Sandiford <rdsandiford@googlemail.com>
|
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* micromips-opc.c (D32, D33, MC): Update definitions.
|
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|
|
(micromips_opcodes): Initialize ase field.
|
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* mips-dis.c (mips_arch_choice): Add ase field.
|
|
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|
(mips_arch_choices): Initialize ase field.
|
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(set_default_mips_dis_options): Declare and setup mips_ase.
|
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* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
|
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|
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MT32, MC): Update definitions.
|
|
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(mips_builtin_opcodes): Initialize ase field.
|
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|
2013-05-24 17:13:49 +00:00
|
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|
2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
|
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* s390-opc.txt (flogr): Require a register pair destination.
|
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2013-05-23 15:48:47 +00:00
|
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|
2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
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* s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
|
|
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|
|
instruction format.
|
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|
|
2013-05-22 18:08:26 +00:00
|
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|
|
2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
|
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|
* mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
|
|
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|
|
opcodes/
* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
XLS_MASK, PPCVSX2): New defines.
(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
<lxvx, stxvx>: New extended mnemonics.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
and clean up warning when using PRINT_OPCODE_TABLE.
gas/testsuite/
* gas/ppc/altivec2.d <bcdadd., bcdadd., vaddcuq, vaddecuq, vaddeuqm,
vaddudm, vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh,
vclzw, vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud.,
veqv, vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw,
vmuleuw, vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast,
vorc, vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd,
vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm,
vsubudm, vsubuqm, vupkhsw, vupklsw>: Add new tests.
* gas/ppc/altivec2.s: Likewise.
* gas/ppc/power8.d <bcdadd., bcdsub., bctar, bctarl, clrbhrb, fmrgew,
fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe, mfvsrd, mfvsrwz,
msgclrp, msgsndp, mtsle, mtvsrd, mtvsrwa, mtvsrwz, pbt., rfebb,
stqcx., stxsiwx, stxsspx, vaddcuq, vaddecuq, vaddeuqm, vaddudm,
vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh, vclzw,
vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv,
vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgow, vmulesw, vmuleuw,
vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc,
vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd,
vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm,
vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp, xscvdpspn, xscvspdpn,
xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp, xsmaddmsp, xsmsubasp,
xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp, xsnmsubasp, xsnmsubmsp,
xsresp, xsrsp, xsrsqrtesp, xssqrtsp, xssubsp, xxleqv, xxlnand,
xxlorc>: Add new tests.
* gas/ppc/power8.s Likewise.
* gas/ppc/vsx.d <lxvd2x, stxvd2x>: Add new tests.
* gas/ppc/vsx.s Likewise.
* gas/ppc/vsx2.d: New test file.
* gas/ppc/vsx2.s: Likewise.
* gas/ppc/ppc.exp: Run it.
2013-05-21 01:36:46 +00:00
|
|
|
|
2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
|
|
|
|
|
|
* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
|
|
|
|
|
|
XLS_MASK, PPCVSX2): New defines.
|
|
|
|
|
|
(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
|
|
|
|
|
|
fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
|
|
|
|
|
|
mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
|
|
|
|
|
|
mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
|
|
|
|
|
|
mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
|
|
|
|
|
|
vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
|
|
|
|
|
|
vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
|
|
|
|
|
|
vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
|
|
|
|
|
|
vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
|
|
|
|
|
|
vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
|
|
|
|
|
|
vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
|
|
|
|
|
|
vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
|
|
|
|
|
|
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
|
|
|
|
|
|
vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
|
|
|
|
|
|
xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
|
|
|
|
|
|
xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
|
|
|
|
|
|
xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
|
|
|
|
|
|
xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
|
|
|
|
|
|
<lxvx, stxvx>: New extended mnemonics.
|
|
|
|
|
|
|
2013-05-17 12:57:16 +00:00
|
|
|
|
2013-05-17 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ia64-raw.tbl: Replace non-ASCII char.
|
|
|
|
|
|
* ia64-waw.tbl: Likewise.
|
|
|
|
|
|
* ia64-asmtab.c: Regenerate.
|
|
|
|
|
|
|
2013-05-15 05:06:23 +00:00
|
|
|
|
2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2013-05-13 22:28:27 +00:00
|
|
|
|
2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Relax the range
|
|
|
|
|
|
check from [0, 255] to [-128, 255].
|
|
|
|
|
|
|
binutils/ChangeLog:
* doc/binutils.texi: Document -Mvirt disassembler option.
gas/ChangeLog:
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
(mips_opts): Update for the new field.
(file_ase_virt): New variable.
(ISA_SUPPORTS_VIRT_ASE): New macro.
(ISA_SUPPORTS_VIRT64_ASE): New macro.
(MIPS_CPU_ASE_VIRT): New define.
(is_opcode_valid): Handle ase_virt.
(macro_build): Handle "+J".
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
(md_longopts): Add mvirt and mnovirt
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
(mips_after_parse_args): Handle ase_virt field.
(s_mipsset): Handle "virt" and "novirt".
(mips_elf_final_processing): Add a comment about virt ASE might need a new flag.
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
* doc/c-mips.texi: Document -mvirt and -mno-virt.
Document ".set virt" and ".set novirt".
gas/testsuite/ChangeLog:
* gas/mips/mips.exp: Run virt and virt64 testcases.
* gas/mips/virt.d: New file.
* gas/mips/virt.s: New file.
* gas/mips/virt64.d: New file.
* gas/mips/virt64.s: New file.
include/opcode/ChangeLog:
* mips.h (OP_MASK_CODE10): Correct definition.
(OP_SH_CODE10): Likewise.
Add a comment that "+J" is used now for OP_*CODE10.
(INSN_ASE_MASK): Update.
(INSN_VIRT): New macro.
(INSN_VIRT64): New macro
opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 .
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
2013-05-10 01:08:48 +00:00
|
|
|
|
2013-05-09 Andrew Pinski <apinski@cavium.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
|
|
|
|
|
|
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
|
|
|
|
|
|
(parse_mips_dis_option): Handle the virt option.
|
|
|
|
|
|
(print_insn_args): Handle "+J".
|
|
|
|
|
|
(print_mips_disassembler_options): Print out message about virt64.
|
|
|
|
|
|
* mips-opc.c (IVIRT): New define.
|
|
|
|
|
|
(IVIRT64): New define.
|
|
|
|
|
|
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
|
|
|
|
|
|
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
|
|
|
|
|
|
Move rfe to the bottom as it conflicts with tlbgp.
|
|
|
|
|
|
|
2013-05-09 04:32:55 +00:00
|
|
|
|
2013-05-09 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (extract_vlesi): Properly sign extend.
|
|
|
|
|
|
(extract_vlensi): Likewise. Comment reason for setting invalid.
|
|
|
|
|
|
|
2013-05-02 21:06:15 +00:00
|
|
|
|
2013-05-02 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* msp430-dis.c: Add support for MSP430X instructions.
|
|
|
|
|
|
|
2013-04-24 20:51:58 +00:00
|
|
|
|
2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
|
|
|
|
|
|
to "eccinj".
|
|
|
|
|
|
|
2013-04-17 14:09:49 +00:00
|
|
|
|
2013-04-17 Wei-chen Wang <cole945@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/15369
|
|
|
|
|
|
* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
|
|
|
|
|
|
of CGEN_CPU_ENDIAN.
|
|
|
|
|
|
(hash_insns_list): Likewise.
|
|
|
|
|
|
|
2013-04-10 19:16:45 +00:00
|
|
|
|
2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
|
|
|
|
|
|
warning workaround.
|
|
|
|
|
|
|
2013-04-08 15:48:38 +00:00
|
|
|
|
2013-04-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-06 22:22:03 +00:00
|
|
|
|
2013-04-06 David S. Miller <davem@davemloft.net>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
|
|
|
|
|
|
of an opcode, prefer the one with F_PREFERRED set.
|
|
|
|
|
|
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
|
|
|
|
|
|
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
|
|
|
|
|
|
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
|
|
|
|
|
|
mark existing mnenomics as aliases. Add "cc" suffix to edge
|
|
|
|
|
|
instructions generating condition codes, mark existing mnenomics
|
|
|
|
|
|
as aliases. Add "fp" prefix to VIS compare instructions, mark
|
|
|
|
|
|
existing mnenomics as aliases.
|
|
|
|
|
|
|
2013-04-03 14:42:10 +00:00
|
|
|
|
2013-04-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
|
|
|
|
|
|
destination address by subtracting the operand from the current
|
|
|
|
|
|
address.
|
|
|
|
|
|
* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
|
|
|
|
|
|
a positive value in the insn.
|
|
|
|
|
|
(extract_u16_loop): Do not negate the returned value.
|
|
|
|
|
|
(D16_LOOP): Add V850_INVERSE_PCREL flag.
|
|
|
|
|
|
|
|
|
|
|
|
(ceilf.sw): Remove duplicate entry.
|
|
|
|
|
|
(cvtf.hs): New entry.
|
|
|
|
|
|
(cvtf.sh): Likewise.
|
|
|
|
|
|
(fmaf.s): Likewise.
|
|
|
|
|
|
(fmsf.s): Likewise.
|
|
|
|
|
|
(fnmaf.s): Likewise.
|
|
|
|
|
|
(fnmsf.s): Likewise.
|
|
|
|
|
|
(maddf.s): Restrict to E3V5 architectures.
|
|
|
|
|
|
(msubf.s): Likewise.
|
|
|
|
|
|
(nmaddf.s): Likewise.
|
|
|
|
|
|
(nmsubf.s): Likewise.
|
|
|
|
|
|
|
2013-03-27 18:49:10 +00:00
|
|
|
|
2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (get_sib): Add the sizeflag argument. Properly
|
|
|
|
|
|
check address mode.
|
|
|
|
|
|
(print_insn): Pass sizeflag to get_sib.
|
|
|
|
|
|
|
2013-03-27 11:43:37 +00:00
|
|
|
|
2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/15068
|
|
|
|
|
|
* tic6x-dis.c: Add support for displaying 16-bit insns.
|
|
|
|
|
|
|
2013-03-20 16:36:34 +00:00
|
|
|
|
2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15095
|
|
|
|
|
|
* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
|
|
|
|
|
|
individual msb and lsb halves in src1 & src2 fields. Discard the
|
|
|
|
|
|
src1 (lsb) value and only use src2 (msb), discarding bit 0, to
|
|
|
|
|
|
follow what Ti SDK does in that case as any value in the src1
|
|
|
|
|
|
field yields the same output with SDK disassembler.
|
|
|
|
|
|
|
2013-03-12 15:19:23 +00:00
|
|
|
|
2013-03-12 Michael Eager <eager@eagercon.com>
|
|
|
|
|
|
|
2013-03-20 16:36:34 +00:00
|
|
|
|
* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
|
2013-03-12 15:19:23 +00:00
|
|
|
|
|
2013-03-12 02:41:26 +00:00
|
|
|
|
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
|
|
|
|
|
|
|
2013-03-12 02:20:08 +00:00
|
|
|
|
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
|
|
|
|
|
|
|
2013-03-12 01:41:41 +00:00
|
|
|
|
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
|
|
|
|
|
|
|
2013-03-11 11:09:33 +00:00
|
|
|
|
2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
|
|
|
|
|
|
(thumb32_opcodes): Likewise.
|
|
|
|
|
|
(print_insn_thumb32): Handle 'S' control char.
|
|
|
|
|
|
|
2013-03-08 17:25:12 +00:00
|
|
|
|
2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* lm32-desc.c: Regenerate.
|
|
|
|
|
|
|
2013-03-02 01:57:48 +00:00
|
|
|
|
2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-reg.tbl (riz): Add RegRex64.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2013-02-28 19:18:40 +00:00
|
|
|
|
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
|
|
|
|
|
|
(aarch64_feature_crc): New static.
|
|
|
|
|
|
(CRC): New macro.
|
|
|
|
|
|
(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
|
|
|
|
|
|
crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
|
|
|
|
|
|
* aarch64-asm-2.c: Re-generate.
|
|
|
|
|
|
* aarch64-dis-2.c: Ditto.
|
|
|
|
|
|
* aarch64-opc-2.c: Ditto.
|
|
|
|
|
|
|
2013-02-27 03:00:44 +00:00
|
|
|
|
2013-02-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rl78-decode.opc (rl78_decode_opcode): Fix typo.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
|
2013-02-25 18:41:06 +00:00
|
|
|
|
2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rl78-decode.opc: Fix encoding of DIVWU insn.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
|
2013-02-19 19:10:31 +00:00
|
|
|
|
2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15159
|
|
|
|
|
|
* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuSMAP.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (CpuSMAP): New.
|
|
|
|
|
|
(i386_cpu_flags): Add cpusmap.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add clac and stac.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2013-02-15 14:54:28 +00:00
|
|
|
|
2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* metag-dis.c: Initialize outf->bytes_per_chunk to 4
|
|
|
|
|
|
which also makes the disassembler output be in little
|
|
|
|
|
|
endian like it should be.
|
|
|
|
|
|
|
2013-02-14 18:12:51 +00:00
|
|
|
|
2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
|
|
|
|
|
|
fields to NULL.
|
|
|
|
|
|
(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
|
|
|
|
|
|
|
2013-02-13 19:36:10 +00:00
|
|
|
|
2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
|
2013-02-13 17:09:09 +00:00
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (is_compressed_mode_p): Only match symbols from the
|
|
|
|
|
|
section disassembled.
|
|
|
|
|
|
|
2013-02-11 10:15:52 +00:00
|
|
|
|
2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c: Update strht pattern.
|
|
|
|
|
|
|
gas/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
(macro): Use it. Assert that trunc.w.s is not used for r5900.
opcodes/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
single-float. Disable ll, lld, sc and scd for EE. Disable the
trunc.w.s macro for EE.
gas/testsuite/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/24k-triple-stores-2.d, gas/mips/24k-triple-stores-2.s,
gas/mips/micromips@24k-triple-stores-2.d: Move "sc" tests to...
* gas/mips/24k-triple-stores-2-llsc.d,
gas/mips/24k-triple-stores-2-llsc.s,
gas/mips/micromips@24k-triple-stores-2-llsc.d: ...these new tests.
* gas/mips/r5900-full.d, gas/mips/r5900-full.s: Verify that the
MIPS ISA level can be upgraded to support ll, sc, lld and scd.
* gas/mips/l_d-single.d, gas/mips/s_d-single.d,
gas/mips/r5900-nollsc.l, gas/mips/r5900-nollsc.s: New tests.
* gas/mips/mips.exp: Update accordingly. Add "nollsc" to r5900
properties.
2013-02-09 10:24:20 +00:00
|
|
|
|
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
|
|
|
|
|
|
single-float. Disable ll, lld, sc and scd for EE. Disable the
|
|
|
|
|
|
trunc.w.s macro for EE.
|
|
|
|
|
|
|
2013-02-06 23:22:26 +00:00
|
|
|
|
2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
|
|
|
|
|
|
Andrew Jenner <andrew@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
Based on patches from Altera Corporation.
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
|
|
|
|
|
|
nios2-opc.c.
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
* configure.in: Add case for bfd_nios2_arch.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
* disassemble.c (ARCH_nios2): Define.
|
|
|
|
|
|
(disassembler): Add case for bfd_arch_nios2.
|
|
|
|
|
|
* nios2-dis.c: New file.
|
|
|
|
|
|
* nios2-opc.c: New file.
|
|
|
|
|
|
|
2013-02-04 06:04:33 +00:00
|
|
|
|
2013-02-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
* rx-decode.c: Regenerate.
|
|
|
|
|
|
|
include/opcode/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
opcodes/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
* aarch64-asm.c (convert_xtl_to_shll): New function.
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_xtl_to_shll.
* aarch64-dis.c (convert_shll_to_xtl): New function.
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_shll_to_xtl.
* aarch64-gen.c: Update copyright year.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Re-generate.
* aarch64-opc-2.c: Re-generate.
gas/testsuite/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/alias.s: Add new tests.
* gas/aarch64/alias.d: Update.
* gas/aarch64/no-aliases.d: Update.
2013-01-30 15:43:32 +00:00
|
|
|
|
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
|
|
|
|
|
|
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
|
|
|
|
|
|
* aarch64-asm.c (convert_xtl_to_shll): New function.
|
|
|
|
|
|
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
|
|
|
|
|
|
calling convert_xtl_to_shll.
|
|
|
|
|
|
* aarch64-dis.c (convert_shll_to_xtl): New function.
|
|
|
|
|
|
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
|
|
|
|
|
|
calling convert_shll_to_xtl.
|
|
|
|
|
|
* aarch64-gen.c: Update copyright year.
|
|
|
|
|
|
* aarch64-asm-2.c: Re-generate.
|
|
|
|
|
|
* aarch64-dis-2.c: Re-generate.
|
|
|
|
|
|
* aarch64-opc-2.c: Re-generate.
|
|
|
|
|
|
|
2013-01-24 11:14:05 +00:00
|
|
|
|
2013-01-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* v850-dis.c: Add support for e3v5 architecture.
|
|
|
|
|
|
* v850-opc.c: Likewise.
|
|
|
|
|
|
|
2013-01-17 16:09:44 +00:00
|
|
|
|
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): For
|
2013-01-24 11:14:05 +00:00
|
|
|
|
AARCH64_MOD_LSL, move the range check on the shift amount before the
|
2013-01-17 16:09:44 +00:00
|
|
|
|
alignment check; change to call set_sft_amount_out_of_range_error
|
|
|
|
|
|
instead of set_imm_out_of_range_error.
|
|
|
|
|
|
* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
|
|
|
|
|
|
(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
|
|
|
|
|
|
8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
|
|
|
|
|
|
SIMD_IMM_SFT.
|
|
|
|
|
|
|
2013-01-16 22:11:05 +00:00
|
|
|
|
2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2013-01-15 08:45:45 +00:00
|
|
|
|
2013-01-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
|
|
|
|
|
|
values.
|
|
|
|
|
|
* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
|
|
|
|
|
|
|
2013-01-14 11:22:06 +00:00
|
|
|
|
2013-01-14 Will Newton <will.newton@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* metag-dis.c (REG_WIDTH): Increase to 64.
|
|
|
|
|
|
|
include/opcode/
* ppc.h (PPC_OPCODE_POWER8): New define.
(PPC_OPCODE_HTM): Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
(SH6): Update.
<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
gas/
* doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* config/tc-ppc.c (md_show_usage): Likewise.
(ppc_handle_align): Handle power8's group ending nop.
gas/testsuite/
* gas/ppc/htm.d: New test.
* gas/ppc/htm.s: Likewise.
* gas/ppc/power8.d: Likewise.
* gas/ppc/power8.s: Likewise.
* gas/ppc/ppc.exp: Run them.
2013-01-11 02:25:36 +00:00
|
|
|
|
2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
|
|
|
|
|
|
* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
|
|
|
|
|
|
XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
|
|
|
|
|
|
(SH6): Update.
|
|
|
|
|
|
<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
|
|
|
|
|
|
"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
|
|
|
|
|
|
"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
|
|
|
|
|
|
<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
|
|
|
|
|
|
|
2013-01-10 09:49:22 +00:00
|
|
|
|
2013-01-10 Will Newton <will.newton@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Add Meta.
|
|
|
|
|
|
* configure.in: Add Meta.
|
|
|
|
|
|
* disassemble.c: Add Meta support.
|
|
|
|
|
|
* metag-dis.c: New file.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2013-01-07 15:09:07 +00:00
|
|
|
|
2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
|
|
|
|
|
|
(match_opcode): Rename to cr16_match_opcode.
|
|
|
|
|
|
|
2013-01-04 17:22:53 +00:00
|
|
|
|
2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c: Add names for CP0 registers of r5900.
|
|
|
|
|
|
* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
|
|
|
|
|
|
instructions sq and lq.
|
|
|
|
|
|
Add support for MIPS r5900 CPU.
|
|
|
|
|
|
Add support for 128 bit MMI (Multimedia Instructions).
|
|
|
|
|
|
Add support for EE instructions (Emotion Engine).
|
|
|
|
|
|
Disable unsupported floating point instructions (64 bit and
|
|
|
|
|
|
undefined compare operations).
|
|
|
|
|
|
Enable instructions of MIPS ISA IV which are supported by r5900.
|
|
|
|
|
|
Disable 64 bit co processor instructions.
|
|
|
|
|
|
Disable 64 bit multiplication and division instructions.
|
|
|
|
|
|
Disable instructions for co-processor 2 and 3, because these are
|
|
|
|
|
|
not supported (preparation for later VU0 support (Vector Unit)).
|
|
|
|
|
|
Disable cvt.w.s because this behaves like trunc.w.s and the
|
|
|
|
|
|
correct execution can't be ensured on r5900.
|
|
|
|
|
|
Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
|
|
|
|
|
|
will confuse less developers and compilers.
|
|
|
|
|
|
|
2013-01-04 13:32:06 +00:00
|
|
|
|
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
2013-01-04 14:59:33 +00:00
|
|
|
|
* aarch64-opc.c (aarch64_print_operand): Change to print
|
|
|
|
|
|
AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
|
|
|
|
|
|
in comment.
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
|
|
|
|
|
|
from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
|
|
|
|
|
|
OP_MOV_IMM_WIDE.
|
|
|
|
|
|
|
|
|
|
|
|
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
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PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
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2013-01-04 13:32:06 +00:00
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2013-01-02 17:15:38 +00:00
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2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (process_copyright): Update copyright year to 2013.
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2013-01-02 13:13:36 +00:00
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2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
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2012-12-17 16:56:12 +00:00
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2013-01-02 13:13:36 +00:00
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* cr16-dis.c (match_opcode,make_instruction): Remove static
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declaration.
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(dwordU,wordU): Moved typedefs to opcode/cr16.h
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(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
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2012-12-17 16:56:12 +00:00
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2013-01-02 13:13:36 +00:00
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For older changes see ChangeLog-2012
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1999-05-03 07:29:11 +00:00
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2013-01-02 13:13:36 +00:00
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Copyright (C) 2013 Free Software Foundation, Inc.
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2012-12-10 12:48:03 +00:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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1999-05-03 07:29:11 +00:00
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Local Variables:
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2001-01-11 19:01:42 +00:00
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mode: change-log
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left-margin: 8
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fill-column: 74
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1999-05-03 07:29:11 +00:00
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version-control: never
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End:
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