2013-01-17 16:09:44 +00:00
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2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
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* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
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* aarch64-opc.c (operand_general_constraint_met_p): For
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AARCH64_MOD_LSL, move the range check on the shift amount before the
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alignment check; change to call set_sft_amount_out_of_range_error
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instead of set_imm_out_of_range_error.
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* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
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(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
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8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
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SIMD_IMM_SFT.
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2013-01-16 22:11:05 +00:00
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2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2013-01-15 08:45:45 +00:00
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2013-01-15 Nick Clifton <nickc@redhat.com>
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* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
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values.
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* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
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2013-01-14 11:22:06 +00:00
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2013-01-14 Will Newton <will.newton@imgtec.com>
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* metag-dis.c (REG_WIDTH): Increase to 64.
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include/opcode/
* ppc.h (PPC_OPCODE_POWER8): New define.
(PPC_OPCODE_HTM): Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
(SH6): Update.
<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
gas/
* doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* config/tc-ppc.c (md_show_usage): Likewise.
(ppc_handle_align): Handle power8's group ending nop.
gas/testsuite/
* gas/ppc/htm.d: New test.
* gas/ppc/htm.s: Likewise.
* gas/ppc/power8.d: Likewise.
* gas/ppc/power8.s: Likewise.
* gas/ppc/ppc.exp: Run them.
2013-01-11 02:25:36 +00:00
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2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
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* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
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XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
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(SH6): Update.
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<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
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"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
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"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
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<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
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2013-01-10 09:49:22 +00:00
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2013-01-10 Will Newton <will.newton@imgtec.com>
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* Makefile.am: Add Meta.
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* configure.in: Add Meta.
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* disassemble.c: Add Meta support.
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* metag-dis.c: New file.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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2013-01-07 15:09:07 +00:00
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2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
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* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
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(match_opcode): Rename to cr16_match_opcode.
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2013-01-04 17:22:53 +00:00
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2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
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* mips-dis.c: Add names for CP0 registers of r5900.
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* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
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instructions sq and lq.
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Add support for MIPS r5900 CPU.
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Add support for 128 bit MMI (Multimedia Instructions).
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Add support for EE instructions (Emotion Engine).
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Disable unsupported floating point instructions (64 bit and
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undefined compare operations).
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Enable instructions of MIPS ISA IV which are supported by r5900.
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Disable 64 bit co processor instructions.
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Disable 64 bit multiplication and division instructions.
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Disable instructions for co-processor 2 and 3, because these are
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not supported (preparation for later VU0 support (Vector Unit)).
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Disable cvt.w.s because this behaves like trunc.w.s and the
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correct execution can't be ensured on r5900.
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Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
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will confuse less developers and compilers.
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2013-01-04 13:32:06 +00:00
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2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
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2013-01-04 14:59:33 +00:00
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* aarch64-opc.c (aarch64_print_operand): Change to print
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AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
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in comment.
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* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
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from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
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OP_MOV_IMM_WIDE.
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2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
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PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
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2013-01-04 13:32:06 +00:00
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2013-01-02 17:15:38 +00:00
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2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (process_copyright): Update copyright year to 2013.
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2013-01-02 13:13:36 +00:00
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2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
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2012-12-17 16:56:12 +00:00
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2013-01-02 13:13:36 +00:00
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* cr16-dis.c (match_opcode,make_instruction): Remove static
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declaration.
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(dwordU,wordU): Moved typedefs to opcode/cr16.h
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(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
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2012-12-17 16:56:12 +00:00
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2013-01-02 13:13:36 +00:00
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For older changes see ChangeLog-2012
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1999-05-03 07:29:11 +00:00
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2013-01-02 13:13:36 +00:00
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Copyright (C) 2013 Free Software Foundation, Inc.
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2012-12-10 12:48:03 +00:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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1999-05-03 07:29:11 +00:00
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Local Variables:
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2001-01-11 19:01:42 +00:00
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mode: change-log
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left-margin: 8
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fill-column: 74
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1999-05-03 07:29:11 +00:00
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version-control: never
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End:
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