2013-06-26 10:31:38 +00:00
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2013-06-26 Nick Clifton <nickc@redhat.com>
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* rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
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field when checking for type 2 nop.
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* rx-decode.c: Regenerate.
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bfd/
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype.
* elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member.
(STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros.
(MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise.
(MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise.
(micromips_insn32_o32_exec_plt0_entry): New variable.
(micromips_insn32_o32_exec_plt_entry): Likewise.
(_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode.
(mips_elf_estimate_stub_size): Likewise.
(_bfd_mips_elf_size_dynamic_sections): Likewise.
(_bfd_mips_elf_finish_dynamic_symbol): Likewise.
(mips_finish_exec_plt): Likewise.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_insn32): New function.
(_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT.
gas/
* config/tc-mips.c (mips_set_options): Add insn32 member.
(mips_opts): Initialize it.
(NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
(options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
(md_longopts): Add "minsn32" and "mno-insn32" options.
(is_size_valid): Handle insn32 mode.
(md_assemble): Pass instruction string down to macro.
(brk_fmt): Add second dimension and insn32 mode initializers.
(mfhl_fmt): Likewise.
(BRK_FMT, MFHL_FMT): Handle insn32 mode.
(macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
(macro_build_jalr, move_register): Handle insn32 mode.
(macro_build_branch_rs): Likewise.
(macro): Handle insn32 mode.
<M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
(mips_ip): Handle insn32 mode.
(md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
(s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
(mips_handle_align): Handle insn32 mode.
(md_show_usage): Add -minsn32 and -mno-insn32.
* doc/as.texinfo (Target MIPS options): Add -minsn32 and
-mno-insn32 options.
(-minsn32, -mno-insn32): New options.
* doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
options.
(MIPS assembly options): New node. Document .set insn32 and
.set noinsn32.
(MIPS-Dependent): List the new node.
gas/testsuite/
* gas/mips/micromips-insn32.d: New test.
* gas/mips/micromips-noinsn32.d: Likewise.
* gas/mips/micromips.l: Rename to...
* gas/mips/micromips-warn.l: ... this.
* gas/mips/micromips.d: Update accordingly.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New list test.
* gas/mips/micromips.s: Add conditionals.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
values.
ld/
* emultempl/mipself.em (insn32): New variable.
(mips_create_output_section_statements): Handle insn32 mode.
(PARSE_AND_LIST_PROLOGUE): New macro.
(PARSE_AND_LIST_LONGOPTS): Likewise.
(PARSE_AND_LIST_OPTIONS): Likewise.
* gen-doc.texi: Set MIPS.
* ld.texinfo: Likewise.
(Options specific to MIPS targets): New section.
(ld and MIPS family): New node.
(Top, Machine Dependent): List the new node.
opcodes/
* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
and "movep" macros.
2013-06-25 18:02:34 +00:00
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2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
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* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
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and "movep" macros.
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2013-06-24 23:55:46 +00:00
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2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-dis.c (is_mips16_plt_tail): New function.
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(print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
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word.
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(is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
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2013-06-21 15:01:57 +00:00
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2013-06-21 DJ Delorie <dj@redhat.com>
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* msp430-decode.opc: New.
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* msp430-decode.c: New/generated.
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* Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
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(MAINTAINER_CLEANFILES): Likewise.
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Add rule to build msp430-decode.c frommsp430decode.opc
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using the opc2c program.
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* Makefile.in: Regenerate.
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* configure.in: Add msp430-decode.lo to msp430 architecture files.
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* configure: Regenerate.
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2013-06-20 16:01:35 +00:00
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2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
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(SYMTAB_AVAILABLE): Removed.
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(#include "elf/aarch64.h): Ditto.
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2013-06-17 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Chao-Ying Fu <fu@mips.com>
gas/testsuite/
* gas/mips/mips.exp: Run new tests.
* gas/mips/eva.d: New.
* gas/mips/eva.s: New.
* gas/mips/micromips@eva.d: New.
gas/
* config/tc-mips.c (mips_set_options): Add ase_eva.
(mips_set_options mips_opts): Add ase_eva.
(file_ase_eva): Declare.
(ISA_SUPPORTS_EVA_ASE): Define.
(IS_SEXT_9BIT_NUM): Define.
(MIPS_CPU_ASE_EVA): Define.
(is_opcode_valid): Add support for ase_eva.
(macro_build): Likewise.
(macro): Likewise.
(validate_mips_insn): Likewise.
(validate_micromips_insn): Likewise.
(mips_ip): Likewise.
(options): Add OPTION_EVA and OPTION_NO_EVA.
(md_longopts): Add -meva and -mno-eva.
(md_parse_option): Process new options.
(mips_after_parse_args): Check for valid EVA combinations.
(s_mipsset): Likewise.
include/
* opcode/mips.h (OP_SH_EVAOFFSET): Define.
(OP_MASK_EVAOFFSET): Define.
(INSN_ASE_MASK): Delete.
(ASE_EVA): Define.
(M_CACHEE_AB, M_CACHEE_OB): New.
(M_LBE_OB, M_LBE_AB): New.
(M_LBUE_OB, M_LBUE_AB): New.
(M_LHE_OB, M_LHE_AB): New.
(M_LHUE_OB, M_LHUE_AB): New.
(M_LLE_AB, M_LLE_OB): New.
(M_LWE_OB, M_LWE_AB): New.
(M_LWLE_AB, M_LWLE_OB): New.
(M_LWRE_AB, M_LWRE_OB): New.
(M_PREFE_AB, M_PREFE_OB): New.
(M_SCE_AB, M_SCE_OB): New.
(M_SBE_OB, M_SBE_AB): New.
(M_SHE_OB, M_SHE_AB): New.
(M_SWE_OB, M_SWE_AB): New.
(M_SWLE_AB, M_SWLE_OB): New.
(M_SWRE_AB, M_SWRE_OB): New.
(MICROMIPSOP_SH_EVAOFFSET): Define.
(MICROMIPSOP_MASK_EVAOFFSET): Define.
opcodes/
* micromips-opc.c (EVA): Define.
(TLBINV): Define.
(micromips_opcodes): Add EVA opcodes.
* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
(print_insn_args): Handle EVA offsets.
(print_insn_micromips): Likewise.
* mips-opc.c (EVA): Define.
(TLBINV): Define.
(mips_builtin_opcodes): Add EVA opcodes.
2013-06-17 22:59:10 +00:00
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2013-06-17 Catherine Moore <clm@codesourcery.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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Chao-Ying Fu <fu@mips.com>
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* micromips-opc.c (EVA): Define.
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(TLBINV): Define.
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(micromips_opcodes): Add EVA opcodes.
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* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
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(print_insn_args): Handle EVA offsets.
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(print_insn_micromips): Likewise.
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* mips-opc.c (EVA): Define.
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(TLBINV): Define.
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(mips_builtin_opcodes): Add EVA opcodes.
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2013-06-17 11:51:13 +00:00
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2013-06-17 Alan Modra <amodra@gmail.com>
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* Makefile.am (mips-opc.lo): Add rules to create automatic
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dependency files. Pass archdefs.
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(micromips-opc.lo, mips16-opc.lo): Likewise.
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* Makefile.in: Regenerate.
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2013-06-14 19:57:10 +00:00
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2013-06-14 DJ Delorie <dj@redhat.com>
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* rx-decode.opc (rx_decode_opcode): Bit operations on
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registers are 32-bit operations, not 8-bit operations.
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* rx-decode.c: Regenerate.
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2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* micromips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
* mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
dmtgc0 to print cp0 names.
2013-06-13 21:01:44 +00:00
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2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
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* micromips-opc.c (IVIRT): New define.
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(IVIRT64): New define.
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(micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
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tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
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* mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
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dmtgc0 to print cp0 names.
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2013-06-10 01:04:42 +00:00
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2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
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* nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
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argument.
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gas/
2013-06-08 Catherine Moore <clm@codesourcery.com>
* config/tc-mips.c (is_opcode_valid): Build ASE mask.
(is_opcode_valid_16): Pass ase value to opcode_is_member.
(append_insn): Change INSN_xxxx to ASE_xxxx.
include/
2013-06-08 Catherine Moore <clm@codesourcery.com>
* opcode/mips.h (mips_opcode): Add ase field.
(INSN_ASE_MASK): Delete.
(INSN_DSP): Rename to ASE_DSP. Provide new value.
(INSN_DSPR2): Rename to ASE_DSPR2. Provide new value.
(INSN_MCU): Rename to ASE_MCU. Provide new value.
(INSN_MDMX): Rename to ASE_MDMX. Provide new value.
(INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value.
(INSN_MT): Rename to ASE_MT. Provide new value.
(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value.
(INSN_VIRT): Rename to ASE_VIRT. Provide new value.
(INSN_VIRT64): Rename to ASE_VIRT64. Provide new value.
(opcode_is_member): Add ase argument. Check ase.
opcodes/
2013-06-08 Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* micromips-opc.c (D32, D33, MC): Update definitions.
(micromips_opcodes): Initialize ase field.
* mips-dis.c (mips_arch_choice): Add ase field.
(mips_arch_choices): Initialize ase field.
(set_default_mips_dis_options): Declare and setup mips_ase.
* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
MT32, MC): Update definitions.
(mips_builtin_opcodes): Initialize ase field.
2013-06-08 10:22:55 +00:00
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2013-06-08 Catherine Moore <clm@codesourcery.com>
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Richard Sandiford <rdsandiford@googlemail.com>
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* micromips-opc.c (D32, D33, MC): Update definitions.
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(micromips_opcodes): Initialize ase field.
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* mips-dis.c (mips_arch_choice): Add ase field.
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(mips_arch_choices): Initialize ase field.
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(set_default_mips_dis_options): Declare and setup mips_ase.
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* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
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MT32, MC): Update definitions.
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(mips_builtin_opcodes): Initialize ase field.
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2013-05-24 17:13:49 +00:00
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2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
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* s390-opc.txt (flogr): Require a register pair destination.
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2013-05-23 15:48:47 +00:00
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2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
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instruction format.
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2013-05-22 18:08:26 +00:00
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2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
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* mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
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opcodes/
* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
XLS_MASK, PPCVSX2): New defines.
(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
<lxvx, stxvx>: New extended mnemonics.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
and clean up warning when using PRINT_OPCODE_TABLE.
gas/testsuite/
* gas/ppc/altivec2.d <bcdadd., bcdadd., vaddcuq, vaddecuq, vaddeuqm,
vaddudm, vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh,
vclzw, vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud.,
veqv, vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw,
vmuleuw, vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast,
vorc, vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd,
vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm,
vsubudm, vsubuqm, vupkhsw, vupklsw>: Add new tests.
* gas/ppc/altivec2.s: Likewise.
* gas/ppc/power8.d <bcdadd., bcdsub., bctar, bctarl, clrbhrb, fmrgew,
fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe, mfvsrd, mfvsrwz,
msgclrp, msgsndp, mtsle, mtvsrd, mtvsrwa, mtvsrwz, pbt., rfebb,
stqcx., stxsiwx, stxsspx, vaddcuq, vaddecuq, vaddeuqm, vaddudm,
vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh, vclzw,
vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv,
vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgow, vmulesw, vmuleuw,
vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc,
vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd,
vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm,
vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp, xscvdpspn, xscvspdpn,
xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp, xsmaddmsp, xsmsubasp,
xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp, xsnmsubasp, xsnmsubmsp,
xsresp, xsrsp, xsrsqrtesp, xssqrtsp, xssubsp, xxleqv, xxlnand,
xxlorc>: Add new tests.
* gas/ppc/power8.s Likewise.
* gas/ppc/vsx.d <lxvd2x, stxvd2x>: Add new tests.
* gas/ppc/vsx.s Likewise.
* gas/ppc/vsx2.d: New test file.
* gas/ppc/vsx2.s: Likewise.
* gas/ppc/ppc.exp: Run it.
2013-05-21 01:36:46 +00:00
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2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
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* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
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XLS_MASK, PPCVSX2): New defines.
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(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
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fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
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mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
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mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
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mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
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vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
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vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
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vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
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vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
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vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
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vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
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vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
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vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
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vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
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xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
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xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
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xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
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xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
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<lxvx, stxvx>: New extended mnemonics.
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2013-05-17 12:57:16 +00:00
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2013-05-17 Alan Modra <amodra@gmail.com>
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* ia64-raw.tbl: Replace non-ASCII char.
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* ia64-waw.tbl: Likewise.
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* ia64-asmtab.c: Regenerate.
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2013-05-15 05:06:23 +00:00
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2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
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* i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
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* i386-init.h: Regenerated.
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2013-05-13 22:28:27 +00:00
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2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
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* aarch64-opc.c (operand_general_constraint_met_p): Relax the range
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check from [0, 255] to [-128, 255].
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binutils/ChangeLog:
* doc/binutils.texi: Document -Mvirt disassembler option.
gas/ChangeLog:
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
(mips_opts): Update for the new field.
(file_ase_virt): New variable.
(ISA_SUPPORTS_VIRT_ASE): New macro.
(ISA_SUPPORTS_VIRT64_ASE): New macro.
(MIPS_CPU_ASE_VIRT): New define.
(is_opcode_valid): Handle ase_virt.
(macro_build): Handle "+J".
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
(md_longopts): Add mvirt and mnovirt
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
(mips_after_parse_args): Handle ase_virt field.
(s_mipsset): Handle "virt" and "novirt".
(mips_elf_final_processing): Add a comment about virt ASE might need a new flag.
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
* doc/c-mips.texi: Document -mvirt and -mno-virt.
Document ".set virt" and ".set novirt".
gas/testsuite/ChangeLog:
* gas/mips/mips.exp: Run virt and virt64 testcases.
* gas/mips/virt.d: New file.
* gas/mips/virt.s: New file.
* gas/mips/virt64.d: New file.
* gas/mips/virt64.s: New file.
include/opcode/ChangeLog:
* mips.h (OP_MASK_CODE10): Correct definition.
(OP_SH_CODE10): Likewise.
Add a comment that "+J" is used now for OP_*CODE10.
(INSN_ASE_MASK): Update.
(INSN_VIRT): New macro.
(INSN_VIRT64): New macro
opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 .
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
2013-05-10 01:08:48 +00:00
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2013-05-09 Andrew Pinski <apinski@cavium.com>
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* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
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Add INSN_VIRT and INSN_VIRT64 to mips64r2.
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(parse_mips_dis_option): Handle the virt option.
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(print_insn_args): Handle "+J".
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(print_mips_disassembler_options): Print out message about virt64.
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* mips-opc.c (IVIRT): New define.
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(IVIRT64): New define.
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(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
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tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
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Move rfe to the bottom as it conflicts with tlbgp.
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2013-05-09 04:32:55 +00:00
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2013-05-09 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (extract_vlesi): Properly sign extend.
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(extract_vlensi): Likewise. Comment reason for setting invalid.
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2013-05-02 21:06:15 +00:00
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2013-05-02 Nick Clifton <nickc@redhat.com>
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* msp430-dis.c: Add support for MSP430X instructions.
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2013-04-24 20:51:58 +00:00
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2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
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* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
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to "eccinj".
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2013-04-17 14:09:49 +00:00
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2013-04-17 Wei-chen Wang <cole945@gmail.com>
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PR binutils/15369
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* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
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of CGEN_CPU_ENDIAN.
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(hash_insns_list): Likewise.
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2013-04-10 19:16:45 +00:00
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2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
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* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
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warning workaround.
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2013-04-08 15:48:38 +00:00
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2013-04-08 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
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* i386-tbl.h: Re-generate.
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Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-06 22:22:03 +00:00
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2013-04-06 David S. Miller <davem@davemloft.net>
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* sparc-dis.c (compare_opcodes): When encountering multiple aliases
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of an opcode, prefer the one with F_PREFERRED set.
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* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
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lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
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ops. Make 64-bit VIS logical ops have "d" suffix in their names,
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mark existing mnenomics as aliases. Add "cc" suffix to edge
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instructions generating condition codes, mark existing mnenomics
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as aliases. Add "fp" prefix to VIS compare instructions, mark
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existing mnenomics as aliases.
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2013-04-03 14:42:10 +00:00
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2013-04-03 Nick Clifton <nickc@redhat.com>
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* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
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destination address by subtracting the operand from the current
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address.
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* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
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a positive value in the insn.
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(extract_u16_loop): Do not negate the returned value.
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(D16_LOOP): Add V850_INVERSE_PCREL flag.
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(ceilf.sw): Remove duplicate entry.
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(cvtf.hs): New entry.
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(cvtf.sh): Likewise.
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(fmaf.s): Likewise.
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(fmsf.s): Likewise.
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(fnmaf.s): Likewise.
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(fnmsf.s): Likewise.
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(maddf.s): Restrict to E3V5 architectures.
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(msubf.s): Likewise.
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(nmaddf.s): Likewise.
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(nmsubf.s): Likewise.
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2013-03-27 18:49:10 +00:00
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2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (get_sib): Add the sizeflag argument. Properly
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check address mode.
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(print_insn): Pass sizeflag to get_sib.
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2013-03-27 11:43:37 +00:00
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2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
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PR binutils/15068
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* tic6x-dis.c: Add support for displaying 16-bit insns.
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2013-03-20 16:36:34 +00:00
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2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
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PR gas/15095
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* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
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individual msb and lsb halves in src1 & src2 fields. Discard the
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src1 (lsb) value and only use src2 (msb), discarding bit 0, to
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follow what Ti SDK does in that case as any value in the src1
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field yields the same output with SDK disassembler.
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2013-03-12 15:19:23 +00:00
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2013-03-12 Michael Eager <eager@eagercon.com>
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2013-03-20 16:36:34 +00:00
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* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
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2013-03-12 15:19:23 +00:00
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2013-03-12 02:41:26 +00:00
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2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
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2013-03-12 02:20:08 +00:00
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2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
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2013-03-12 01:41:41 +00:00
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2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
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2013-03-11 11:09:33 +00:00
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2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
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(thumb32_opcodes): Likewise.
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(print_insn_thumb32): Handle 'S' control char.
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2013-03-08 17:25:12 +00:00
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2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
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* lm32-desc.c: Regenerate.
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2013-03-02 01:57:48 +00:00
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2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
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* i386-reg.tbl (riz): Add RegRex64.
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* i386-tbl.h: Regenerated.
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2013-02-28 19:18:40 +00:00
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2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
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(aarch64_feature_crc): New static.
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(CRC): New macro.
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(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
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crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
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* aarch64-asm-2.c: Re-generate.
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* aarch64-dis-2.c: Ditto.
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* aarch64-opc-2.c: Ditto.
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2013-02-27 03:00:44 +00:00
|
|
|
|
2013-02-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rl78-decode.opc (rl78_decode_opcode): Fix typo.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
|
2013-02-25 18:41:06 +00:00
|
|
|
|
2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rl78-decode.opc: Fix encoding of DIVWU insn.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
|
2013-02-19 19:10:31 +00:00
|
|
|
|
2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15159
|
|
|
|
|
|
* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuSMAP.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (CpuSMAP): New.
|
|
|
|
|
|
(i386_cpu_flags): Add cpusmap.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add clac and stac.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2013-02-15 14:54:28 +00:00
|
|
|
|
2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* metag-dis.c: Initialize outf->bytes_per_chunk to 4
|
|
|
|
|
|
which also makes the disassembler output be in little
|
|
|
|
|
|
endian like it should be.
|
|
|
|
|
|
|
2013-02-14 18:12:51 +00:00
|
|
|
|
2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
|
|
|
|
|
|
fields to NULL.
|
|
|
|
|
|
(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
|
|
|
|
|
|
|
2013-02-13 19:36:10 +00:00
|
|
|
|
2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
|
2013-02-13 17:09:09 +00:00
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (is_compressed_mode_p): Only match symbols from the
|
|
|
|
|
|
section disassembled.
|
|
|
|
|
|
|
2013-02-11 10:15:52 +00:00
|
|
|
|
2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c: Update strht pattern.
|
|
|
|
|
|
|
gas/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
(macro): Use it. Assert that trunc.w.s is not used for r5900.
opcodes/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
single-float. Disable ll, lld, sc and scd for EE. Disable the
trunc.w.s macro for EE.
gas/testsuite/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/24k-triple-stores-2.d, gas/mips/24k-triple-stores-2.s,
gas/mips/micromips@24k-triple-stores-2.d: Move "sc" tests to...
* gas/mips/24k-triple-stores-2-llsc.d,
gas/mips/24k-triple-stores-2-llsc.s,
gas/mips/micromips@24k-triple-stores-2-llsc.d: ...these new tests.
* gas/mips/r5900-full.d, gas/mips/r5900-full.s: Verify that the
MIPS ISA level can be upgraded to support ll, sc, lld and scd.
* gas/mips/l_d-single.d, gas/mips/s_d-single.d,
gas/mips/r5900-nollsc.l, gas/mips/r5900-nollsc.s: New tests.
* gas/mips/mips.exp: Update accordingly. Add "nollsc" to r5900
properties.
2013-02-09 10:24:20 +00:00
|
|
|
|
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
|
|
|
|
|
|
single-float. Disable ll, lld, sc and scd for EE. Disable the
|
|
|
|
|
|
trunc.w.s macro for EE.
|
|
|
|
|
|
|
2013-02-06 23:22:26 +00:00
|
|
|
|
2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
|
|
|
|
|
|
Andrew Jenner <andrew@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
Based on patches from Altera Corporation.
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
|
|
|
|
|
|
nios2-opc.c.
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
* configure.in: Add case for bfd_nios2_arch.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
* disassemble.c (ARCH_nios2): Define.
|
|
|
|
|
|
(disassembler): Add case for bfd_arch_nios2.
|
|
|
|
|
|
* nios2-dis.c: New file.
|
|
|
|
|
|
* nios2-opc.c: New file.
|
|
|
|
|
|
|
2013-02-04 06:04:33 +00:00
|
|
|
|
2013-02-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
* rx-decode.c: Regenerate.
|
|
|
|
|
|
|
include/opcode/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
opcodes/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
* aarch64-asm.c (convert_xtl_to_shll): New function.
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_xtl_to_shll.
* aarch64-dis.c (convert_shll_to_xtl): New function.
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_shll_to_xtl.
* aarch64-gen.c: Update copyright year.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Re-generate.
* aarch64-opc-2.c: Re-generate.
gas/testsuite/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/alias.s: Add new tests.
* gas/aarch64/alias.d: Update.
* gas/aarch64/no-aliases.d: Update.
2013-01-30 15:43:32 +00:00
|
|
|
|
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
|
|
|
|
|
|
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
|
|
|
|
|
|
* aarch64-asm.c (convert_xtl_to_shll): New function.
|
|
|
|
|
|
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
|
|
|
|
|
|
calling convert_xtl_to_shll.
|
|
|
|
|
|
* aarch64-dis.c (convert_shll_to_xtl): New function.
|
|
|
|
|
|
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
|
|
|
|
|
|
calling convert_shll_to_xtl.
|
|
|
|
|
|
* aarch64-gen.c: Update copyright year.
|
|
|
|
|
|
* aarch64-asm-2.c: Re-generate.
|
|
|
|
|
|
* aarch64-dis-2.c: Re-generate.
|
|
|
|
|
|
* aarch64-opc-2.c: Re-generate.
|
|
|
|
|
|
|
2013-01-24 11:14:05 +00:00
|
|
|
|
2013-01-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* v850-dis.c: Add support for e3v5 architecture.
|
|
|
|
|
|
* v850-opc.c: Likewise.
|
|
|
|
|
|
|
2013-01-17 16:09:44 +00:00
|
|
|
|
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): For
|
2013-01-24 11:14:05 +00:00
|
|
|
|
AARCH64_MOD_LSL, move the range check on the shift amount before the
|
2013-01-17 16:09:44 +00:00
|
|
|
|
alignment check; change to call set_sft_amount_out_of_range_error
|
|
|
|
|
|
instead of set_imm_out_of_range_error.
|
|
|
|
|
|
* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
|
|
|
|
|
|
(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
|
|
|
|
|
|
8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
|
|
|
|
|
|
SIMD_IMM_SFT.
|
|
|
|
|
|
|
2013-01-16 22:11:05 +00:00
|
|
|
|
2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2013-01-15 08:45:45 +00:00
|
|
|
|
2013-01-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
|
|
|
|
|
|
values.
|
|
|
|
|
|
* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
|
|
|
|
|
|
|
2013-01-14 11:22:06 +00:00
|
|
|
|
2013-01-14 Will Newton <will.newton@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* metag-dis.c (REG_WIDTH): Increase to 64.
|
|
|
|
|
|
|
include/opcode/
* ppc.h (PPC_OPCODE_POWER8): New define.
(PPC_OPCODE_HTM): Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
(SH6): Update.
<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
gas/
* doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* config/tc-ppc.c (md_show_usage): Likewise.
(ppc_handle_align): Handle power8's group ending nop.
gas/testsuite/
* gas/ppc/htm.d: New test.
* gas/ppc/htm.s: Likewise.
* gas/ppc/power8.d: Likewise.
* gas/ppc/power8.s: Likewise.
* gas/ppc/ppc.exp: Run them.
2013-01-11 02:25:36 +00:00
|
|
|
|
2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
|
|
|
|
|
|
* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
|
|
|
|
|
|
XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
|
|
|
|
|
|
(SH6): Update.
|
|
|
|
|
|
<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
|
|
|
|
|
|
"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
|
|
|
|
|
|
"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
|
|
|
|
|
|
<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
|
|
|
|
|
|
|
2013-01-10 09:49:22 +00:00
|
|
|
|
2013-01-10 Will Newton <will.newton@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Add Meta.
|
|
|
|
|
|
* configure.in: Add Meta.
|
|
|
|
|
|
* disassemble.c: Add Meta support.
|
|
|
|
|
|
* metag-dis.c: New file.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2013-01-07 15:09:07 +00:00
|
|
|
|
2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
|
|
|
|
|
|
(match_opcode): Rename to cr16_match_opcode.
|
|
|
|
|
|
|
2013-01-04 17:22:53 +00:00
|
|
|
|
2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c: Add names for CP0 registers of r5900.
|
|
|
|
|
|
* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
|
|
|
|
|
|
instructions sq and lq.
|
|
|
|
|
|
Add support for MIPS r5900 CPU.
|
|
|
|
|
|
Add support for 128 bit MMI (Multimedia Instructions).
|
|
|
|
|
|
Add support for EE instructions (Emotion Engine).
|
|
|
|
|
|
Disable unsupported floating point instructions (64 bit and
|
|
|
|
|
|
undefined compare operations).
|
|
|
|
|
|
Enable instructions of MIPS ISA IV which are supported by r5900.
|
|
|
|
|
|
Disable 64 bit co processor instructions.
|
|
|
|
|
|
Disable 64 bit multiplication and division instructions.
|
|
|
|
|
|
Disable instructions for co-processor 2 and 3, because these are
|
|
|
|
|
|
not supported (preparation for later VU0 support (Vector Unit)).
|
|
|
|
|
|
Disable cvt.w.s because this behaves like trunc.w.s and the
|
|
|
|
|
|
correct execution can't be ensured on r5900.
|
|
|
|
|
|
Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
|
|
|
|
|
|
will confuse less developers and compilers.
|
|
|
|
|
|
|
2013-01-04 13:32:06 +00:00
|
|
|
|
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
2013-01-04 14:59:33 +00:00
|
|
|
|
* aarch64-opc.c (aarch64_print_operand): Change to print
|
|
|
|
|
|
AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
|
|
|
|
|
|
in comment.
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
|
|
|
|
|
|
from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
|
|
|
|
|
|
OP_MOV_IMM_WIDE.
|
|
|
|
|
|
|
|
|
|
|
|
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
|
|
|
|
|
|
PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
|
2013-01-04 13:32:06 +00:00
|
|
|
|
|
2013-01-02 17:15:38 +00:00
|
|
|
|
2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (process_copyright): Update copyright year to 2013.
|
|
|
|
|
|
|
2013-01-02 13:13:36 +00:00
|
|
|
|
2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
|
2012-12-17 16:56:12 +00:00
|
|
|
|
|
2013-01-02 13:13:36 +00:00
|
|
|
|
* cr16-dis.c (match_opcode,make_instruction): Remove static
|
|
|
|
|
|
declaration.
|
|
|
|
|
|
(dwordU,wordU): Moved typedefs to opcode/cr16.h
|
|
|
|
|
|
(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
|
2012-12-17 16:56:12 +00:00
|
|
|
|
|
2013-01-02 13:13:36 +00:00
|
|
|
|
For older changes see ChangeLog-2012
|
1999-05-03 07:29:11 +00:00
|
|
|
|
|
2013-01-02 13:13:36 +00:00
|
|
|
|
Copyright (C) 2013 Free Software Foundation, Inc.
|
2012-12-10 12:48:03 +00:00
|
|
|
|
|
|
|
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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1999-05-03 07:29:11 +00:00
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Local Variables:
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2001-01-11 19:01:42 +00:00
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mode: change-log
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left-margin: 8
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fill-column: 74
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1999-05-03 07:29:11 +00:00
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version-control: never
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End:
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