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Author SHA1 Message Date
Joern Rennecke
3c7ad09f36 sh-opc.h (sh_table): Remove ftst/nan. 
Fixes gcc/13330.
 1997-11-12 00:02:37 +00:00
Ken Raeburn
cfca14e759 make vr5400 disassembly work; fix bugs in some vr5400 insns 1997-11-03 18:28:35 +00:00
Gavin Romig-Koch
fe9cb9d8dd Correct tx49 sanitation. 1997-11-02 23:55:21 +00:00
Gavin Romig-Koch
0cca41d47a * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp): 
Add tx49 insns and configury.
 1997-10-29 20:33:43 +00:00
Ken Raeburn
a0539c6102 * mips-opc.c (ffc, ffs): Fix mask. 1997-10-28 23:03:12 +00:00
Michael Meissner
8357d96073 Add eit_vb, int_s, and int_m control registers 1997-10-28 21:36:04 +00:00
Ken Raeburn
a3066d9ac8 Duh. Check in the vr5400 stuff from the directory that doesn't have 
it sanitized out this time...
 1997-10-28 03:44:27 +00:00
Ken Raeburn
581c03af3e added vr5400 stuff, fixed "not" mask 1997-10-28 03:42:29 +00:00
Nick Clifton
04789fe9ab Removed C++ ism 1997-10-23 21:53:56 +00:00
Richard Henderson
81dac216f9 * sparc-opc.c: Add wr & rd for v9a asr's. 
* sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's.
        (v9a_asr_reg_names): New variable.
        Patch from David Miller <davem@vger.rutgers.edu>.
 1997-10-23 00:32:49 +00:00
Richard Henderson
36e75fe3ec * sparc-opc.c (v9notv9a): New insn type. 
(IMPDEP): Move to the end to not conflict with edge8 et al.
        Patch from David Miller <davem@vger.rutgers.edu>.
 1997-10-23 00:17:25 +00:00
Gavin Romig-Koch
d7727fe96b opcodes/mips-opc.c (bnezl,beqzl): Mark these as also tx39. 1997-10-17 17:26:45 +00:00
Gavin Romig-Koch
b7dd310d55 opcodes/mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1. 1997-10-16 16:03:22 +00:00
Nick Clifton
3516c09c60 New dummy function for symbol_at_address_func field of disassemble_info 
structure.
Add code to use this field in v850 disassembly.
 1997-10-14 23:09:59 +00:00
Nick Clifton
5ff4668dea Fixed bug extracting displacement from a JR instruction. 1997-10-10 23:41:43 +00:00
Gavin Romig-Koch
80ae705d30 opcodes/mips-opc.c: Three op mult is not an ISA insn. 1997-10-08 03:46:38 +00:00
Gavin Romig-Koch
b0326e92a5 opcodes/mips-opc.c: Fix formatting. 1997-10-08 03:42:27 +00:00
Nick Clifton
43d759900d Use symbolic names rather than numbers for higher value system registers. 1997-10-02 20:34:06 +00:00
Nick Clifton
404d6e4fd1 Fixed disassembler to use processor type when decoding instructions. 1997-10-02 00:01:10 +00:00
Ian Lance Taylor
2e2ef09d24 * configure.in: Use a diversion to set enable_shared before the 
arguments are parsed.
	* configure: Rebuild.
 1997-10-01 18:11:48 +00:00
Ian Lance Taylor
f849a33ee3 * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire. 1997-09-24 23:03:55 +00:00
Ian Lance Taylor
8ebe0ec1bb * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32. 1997-09-24 17:41:04 +00:00
Ian Lance Taylor
d97a8f952c * m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr 
for mcf5200.
 1997-09-24 17:09:48 +00:00
Ian Lance Taylor
805c3d70bd * configure.in: Call AC_CHECK_TOOL before AM_PROG_LIBTOOL. 
* aclocal.m4: Rebuild with new libtool.
	* configure: Rebuild.
 1997-09-24 15:30:03 +00:00
Nick Clifton
ae6ecba5b4 Fixed sanitization bugs. 1997-09-21 17:44:16 +00:00
Nick Clifton
d345d88340 Removed v850eq sanitization. 1997-09-20 23:13:05 +00:00
Andrew Cagney
1379884be1 Correct ordering of args for cmov insn. 1997-09-19 02:16:41 +00:00
David Edelsohn
6d70d47fb7 * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr. 1997-09-18 18:23:30 +00:00
Felix Lee
3e906c081a sanitization fixes. typoes, missing fences, "start" instead of "end", etc. 1997-09-18 06:03:52 +00:00
Felix Lee
e1625ed217 v850 files that weren't being removed if !keep-v850 1997-09-18 01:33:24 +00:00
Nick Clifton
714229c39a Further rearrangements of the opcodes. 1997-09-16 22:15:48 +00:00
Ken Raeburn
e9fa596ff2 * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change. (PR 13051) 1997-09-16 21:31:03 +00:00
Nick Clifton
1a1ec983c0 Entries in v850_opcodes reordered to put same named entries adjacent to each other. 1997-09-16 16:47:05 +00:00
Gavin Romig-Koch
d9a52316c1 * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret. 
* mips16-opc.c: Added mips16 sdbbp.
 1997-09-16 14:07:50 +00:00
Nick Clifton
9bbbb61220 Add initialisation of the processors field of the v850_opcode structure. 1997-09-16 01:29:02 +00:00
Ken Raeburn
d51bcb7064 merge from d30v-970225-branch 1997-09-15 18:26:17 +00:00
Andrew Cagney
9c82b2b805 Fix v850 sanitization. 1997-09-15 08:14:11 +00:00
Peter Schauer
f8c35bc3b0 * ChangeLog: Fix misspelled `end-sanitize-r5900' for Jun 26 
ChangeLog entry.
 1997-09-13 15:02:36 +00:00
Peter Schauer
b72b716cc8 * ChangeLog: Fix duplicate `start-sanitize-r5900' around 
Jul 28 ChangeLog entry.
 1997-09-13 14:46:36 +00:00
Nick Clifton
d0fd63cb8f Improved display of register lists. 1997-09-12 18:41:26 +00:00
David Edelsohn
44457cbcc2 * sparc-opc.c (sparc_opcodes): Fix assembler args to 
fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s,
	fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s,
	fandnot1s, fandnot2s.
 1997-09-12 00:41:47 +00:00
David Edelsohn
22a25680ba * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq. 1997-09-09 17:08:01 +00:00
David Edelsohn
3fb84577f9 * cgen-asm.c (cgen_parse_address): New argument resultp. 
All callers updated.
	* m32r-asm.c (parse_h_hi16): Right shift numbers by 16.
 1997-09-08 21:07:42 +00:00
Nick Clifton
010916c2e6 Removed v850 sanitization. 1997-09-03 22:19:11 +00:00
Jeff Law
9d53ae4faf * mn10200.h (INITIALIZE_TRAMPOLINE): PC relative instructions are 
relative to the next instruction, not the current instruction.
pr13171.
 1997-09-03 00:39:49 +00:00
Nick Clifton
1f302a3bd9 Removed use of V850_OPERNAD_ADJUST_SHORT_MEMORY. 
Fixed several operand patterns.
 1997-09-02 22:40:39 +00:00
Joern Rennecke
bf5ac1b8ed SH4 assembler extensions. 1997-08-29 19:03:06 +00:00
David Edelsohn
affdd42e25 Remove arc sanitization. 1997-08-28 18:19:21 +00:00
Nick Clifton
33e2f5278c Made immediate parameter of MOVHI be unsigned 1997-08-26 16:40:28 +00:00
Chris Provenzano
a3515171ce Rebuilt configure with latest devo autoconf for NT support. 1997-08-25 22:58:36 +00:00
Nick Clifton
d87a154282 Updated from specs in HDD-tool-0611 document. 1997-08-22 17:35:24 +00:00
Nick Clifton
0c51939934 Moved divh opcodes next to each other. 1997-08-21 18:09:20 +00:00
Nick Clifton
ab11a82c2d Add support for v850e and v850eq targets. 1997-08-18 18:12:54 +00:00
Ian Lance Taylor
cfb9ba14c3 fix v850 sanitization 1997-08-15 15:44:07 +00:00
David Edelsohn
2b0c643b8d Remove ARC sanitization. 1997-08-15 12:20:57 +00:00
Nick Clifton
3ff7258ec3 Tidied up sanitization 1997-08-14 19:42:22 +00:00
Nick Clifton
f61b671ddd Add support for v850E and v850EQ instructions. 1997-08-14 01:55:51 +00:00
Ian Lance Taylor
2f403ada9f * configure.in: Set enable_shared before AM_PROG_LIBTOOL. 
* acinclude.m4: Just include acinclude.m4 from BFD.
	* aclocal.m4, configure: Rebuild.
 1997-08-01 17:03:25 +00:00
Ian Lance Taylor
a3d2e13be9 sanitize Makefile.am 1997-08-01 15:56:29 +00:00
Ian Lance Taylor
1daed53f64 * Makefile.am: New file, based on old Makefile.in. 
* acconfig.h: New file.
	* acinclude.m4: New file.
	* stamp-h.in: New file.
	* configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL.
	Removed shared library handling; now handled by libtool.  Replace
	AC_CONFIG_HEADER with AM_CONFIG_HEADER.  Call AM_MAINTAINER_MODE,
	AM_CYGWIN32, and AM_EXEEXT.  Replace AC_PROG_INSTALL with
	AM_PROG_INSTALL.  Change all .o files to .lo.  Remove stamp-h
	handling in AC_OUTPUT.
	* dep-in.sed: Change .o to .lo.
	* Makefile.in: Now built with automake.
	* aclocal.m4: Now built with aclocal.
	* config.in, configure: Rebuild.
 1997-08-01 01:49:13 +00:00
Jeff Law
fea90b62c1 * mips-opc.c: Fix typo/thinko in "eret" instruction. 1997-07-29 03:48:51 +00:00
Andrew Cagney
6546a590b4 Fix MTSA opcode encoding. 1997-07-28 13:45:45 +00:00
David Edelsohn
8deb997b30 * sparc-opc.c (sparc_opcodes): Make array const. 
* sparc-dis.c (sorted_opcodes): New static local.
	(struct opcode_hash): `opcode' is pointer to const element.
	(build_hash): First arg is now table of sorted pointers.
	(print_insn_sparc): Sort opcodes by sorting table of pointers.
	(compare_opcodes): Update.
 1997-07-24 22:21:05 +00:00
David Edelsohn
3f9382002f * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns. 1997-07-24 20:05:46 +00:00
David Edelsohn
0d7c678ec1 * cgen-opc.c: #include <ctype.h>. 
(hash_keyword_name): New arg `case_sensitive_p'.  Callers updated.
	Handle case insensitive hashing.
	(hash_keyword_value): Change type of `value' to unsigned int.
 1997-07-15 20:02:47 +00:00
Jeff Law
4bb0ae107d * mips-opc.c (mips_builtin_opcodes): If an insn uses single 
precision FP, mark it as such.  Likewise for double precision
        FP.  Mark ISA1 insns.  Consolidate duplicate opcodes where
        possible.
        (mips_builtin_opcodes): Remove non-existant r5900 instructions
toshiba_5900 stuff
 1997-07-11 16:13:42 +00:00
Jeff Law
d0efa46b2d * mips-opc.c (mips_builtin_opcodes): Add "pinteh", "pexeh" and 
"pexew" as synonyms for "pintoh", "pexoh", "pexow".

pr12399.
 1997-06-30 15:06:50 +00:00
Felix Lee
9fd0d551fc * ppc-opc.c (extract_nsi): make unsigned expression signed before 
negating it.
	(UNUSED): remove one level of parens, so MSVC doesn't choke on
 	nesting depth when all the macros are expanded.
 1997-06-25 22:35:14 +00:00
Ian Lance Taylor
3d116ccd46 * sparc-opc.c: The fcmp v9a instructions take an integer register 
as a destination, not a floating point register.  From Christian
	Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE>.
 1997-06-17 21:03:18 +00:00
Ian Lance Taylor
2896b00885 * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@() 
syntax.  From Roman Hodek
	<rnhodek@faui22c.informatik.uni-erlangen.de>.
 1997-06-16 18:31:32 +00:00
Ian Lance Taylor
0a185c4899 * i386-dis.c (twobyte_has_modrm): Fix pand. 1997-06-16 18:14:13 +00:00
Ian Lance Taylor
eedca9daa9 Mon Jun 16 14:08:38 1997 Michael Taylor <mbt@mit.edu> 
* i386-dis.c (dis386_twobyte): Fix pand and pandn.
 1997-06-16 18:09:28 +00:00
Ian Lance Taylor
a5f269e919 Tue Jun 10 11:26:47 1997 H.J. Lu <hjl@gnu.ai.mit.edu> 
* arm-dis.c: Add prototypes for arm_decode_shift and
	print_insn_arm.
 1997-06-10 15:27:52 +00:00
Ian Lance Taylor
f0b796d00a Tue May 27 11:02:08 1997 Alan Modra <alan@spri.levels.unisa.edu.au> 
* i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl
	to pushS/popS for segment regs and byte constant so that
	pushw/popw printed when in 16 bit data mode.

	* i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to
	print cbtw, cwtd in 16 bit data mode.
	* i386-dis.c (putop): extra case W to support above.

	* i386-dis.c (print_insn_x86): print addr32 prefix when given
	address size prefix in 16 bit address mode.
 1997-05-27 15:05:40 +00:00
Ian Lance Taylor
54a93a7266 * sh-dis.c: Reindent. Rename local variable fprintf to 
fprintf_fn.
 1997-05-23 20:52:06 +00:00
David Edelsohn
0b852861f3 * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2. 1997-05-22 21:06:57 +00:00
Gavin Romig-Koch
e17449bcfd Move mips INSN_ISA subfield into new membership field. 1997-05-20 15:29:25 +00:00
Ian Lance Taylor
d72ace420d * i386-dis.c: (dis386_twobyte): Add MMX instructions. 
(twobyte_has_modrm): Likewise.
	(grps): Likewise.
	(OP_MMX, OP_EM, OP_MS): New static functions.
 1997-05-05 21:19:09 +00:00
Ian Lance Taylor
41b96d55e8 * i386-dis.c: Revert patch of April 4. The output now matches 
what gcc generates.
 1997-05-05 18:30:06 +00:00
David Edelsohn
cb6301058d * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead 
of $simm16.
 1997-05-02 19:49:19 +00:00
David Edelsohn
9c1858b400 * cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h. 
Delete string{,s}.h support.
 1997-04-14 00:52:36 +00:00
David Edelsohn
a394e3262f * cgen-asm.c (cgen_parse_operand_fn): New global. 
(cgen_parse_{{,un}signed_integer,address}): Update call to
	cgen_parse_operand_fn.
	(cgen_init_parse_operand): New function.
	* m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed
	from cgen_asm_init_parse.
	(m32r_cgen_assemble_insn): New operand `errmsg'.
	Delete call to as_bad, return error message to caller.
	(m32r_cgen_asm_hash_keywords): #if 0 out.
 1997-04-10 23:39:51 +00:00
David Edelsohn
5b3b8cb071 * cgen-asm.c (cgen_asm_parse_operand_fn): New global. 
(cgen_parse_{{,un}signed_integer,address}): Update call to
	cgen_asm_parse_operand_fn.
	* m32r-asm.c (parse_insn_normal): Delete call to cgen_asm_init_parse.
	(m32r_cgen_assemble_insn): New operand `errmsg'.
	Delete call to as_bad, return error message to caller.
	(m32r_cgen_asm_hash_keywords): #if 0 out.
 1997-04-10 21:58:28 +00:00
Ian Lance Taylor
47332446f5 Wed Apr 9 12:05:25 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> 
* m68k-dis.c (print_insn_arg) [case 'd']: Print as address register,
	not data register.
	[case 'J']: Fix typo in register name.
 1997-04-09 16:10:45 +00:00
Ian Lance Taylor
b4aa23f244 * configure.in: Substitute SHLIB_LIBS. 
* configure: Rebuild.
	* Makefile.in (SHLIB_LIBS): New variable.
	($(SHLIB)): Use $(SHLIB_LIBS).
 1997-04-07 21:01:00 +00:00
David Edelsohn
21b4ac1768 * cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation. 1997-04-07 19:45:47 +00:00
David Edelsohn
70bb1aa163 * cgen-opc.c (hash_keyword_name): Improve algorithm. 1997-04-07 19:27:12 +00:00
David Edelsohn
e4ba4112e3 * disassemble.c (disassembler): Handle m32r. 1997-04-07 18:46:21 +00:00
Ian Lance Taylor
e358a062c9 * configure.in: Correct file names for bfd_mn10[23]00_arch. 
* configure: Rebuild.
 1997-04-05 00:57:46 +00:00
David Edelsohn
35855192ab Add cgen, m32r files. 1997-04-04 21:07:29 +00:00
David Edelsohn
9c03036a8f * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files. 
* cgen-asm.c, cgen-dis.c, cgen-opc.c: New files.
	* Makefile.in (CFILES): Add them.
	(ALL_MACHINES): Add them.
	(dependencies): Regenerate.
	* configure.in (cgen_files): New variable.
	(bfd_m32r_arch): Add entry.
	* configure: Regenerate.
 1997-04-04 21:07:02 +00:00
Ian Lance Taylor
bb6dafe912 * Makefile.in: Rebuild dependencies. 1997-04-04 19:36:26 +00:00
Ian Lance Taylor
71cc7ceb3c * d10v-dis.c: Include "ansidecl.h" before "opcode/d10v.h". 1997-04-04 19:25:29 +00:00
Ian Lance Taylor
fdb6ae6818 * i386-dis.c (float_reg): Swap fsubrp and fsubp. Swap fdivrp and 
fdivp.
 1997-04-04 19:05:12 +00:00
Ian Lance Taylor
bef474032d * Branched binutils 2.8. 1997-04-03 18:23:17 +00:00
Ian Lance Taylor
28e8de4165 * m10200-dis.c: Rename from mn10200-dis.c. 
* m10200-opc.c: Rename from mn10200-opc.c.
	* m10300-dis.c: Rename from mn10300-dis.c
	* m10300-opc.c: Rename from mn10300-opc.c.
	* Makefile.in: Update accordingly.
 1997-04-02 21:07:39 +00:00
Ian Lance Taylor
d02305b214 * mips16-opc.c: Add mul and dmul macros. 
PR 11982.
 1997-04-02 17:25:03 +00:00
Ian Lance Taylor
77090cfa9d Tue Apr 1 16:27:45 1997 Klaus Kaempf <kkaempf@progis.de> 
* makefile.vms: Update CFLAGS, add clean target.
 1997-04-01 21:28:15 +00:00
Ian Lance Taylor
af65db5730 * configure.in: Add stdlib.h to AC_CHECK_HEADERS list. 
* configure, config.in: Rebuild.
	* sysdep.h: Include <stdlib.h> if it exists.
	* sparc-dis.c: Include <stdio.h> and "sysdep.h".  Don't include
	<string.h>.
	* Makefile.in: Rebuild dependencies.
 1997-03-28 17:11:55 +00:00
Ian Lance Taylor
88a257cbfb * ppc-opc.c: Add PPC 403 instructions and extended opcodes. From 
Andrew Bray <andy@madhouse.demon.co.uk>.
 1997-03-28 17:07:47 +00:00
Ian Lance Taylor
a21e1e96be * mips-opc.c: Add cast when setting mips_opcodes. 1997-03-27 19:25:01 +00:00
Ian Lance Taylor
b8306c6b3d * sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s. 
The documented instructions are bf/s and bt/s.
 1997-03-24 19:59:06 +00:00
Ian Lance Taylor
9ab49ef840 * mips-opc.c: Add dctr and dctw. 1997-03-24 18:32:03 +00:00
Martin Hunt
b7f7f20702 Sun Mar 23 18:08:10 1997 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d30v-dis.c (print_insn): Change the way signed constants
	are displayed.
 1997-03-24 02:24:51 +00:00
Ian Lance Taylor
f76db60bbb * Makefile.in (BFD_H): New variable. 
(HFILES): New variable.
	(CFILES): Add all C files.
	(.dep, .dep1, dep.sed, dep, dep-in): New targets.
	Delete old dependencies, and build new ones.
	* dep-in.sed: New file.
 1997-03-21 19:39:26 +00:00
Ian Lance Taylor
9b07de4901 Thu Mar 20 19:03:30 1997 Philippe De Muyter <phdm@info.ucl.ac.be> 
* m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}.
 1997-03-21 00:04:16 +00:00
J.T. Conklin
3b12e2d3c8 * m68k-opc.c (m68k_opcodes): Provide coldfire division module 
instructions.
 1997-03-19 14:56:05 +00:00
Jeff Law
91ce33a152 Tweak "syscall" opcode. 1997-03-18 23:16:44 +00:00
Jeff Law
4e4dd8765f * mn10200-opc.c: Change "trap" to "syscall". 
* mn10300-opc.c: Add new "syscall" instruction.
Cleanups for beta release.
 1997-03-18 21:20:29 +00:00
J.T. Conklin
437579d508 * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and 
mulul insns on the coldfire.
 1997-03-17 16:50:51 +00:00
Ian Lance Taylor
6784be526f * arm-dis.c (print_insn_arm): Don't print instruction bytes. 
(print_insn_big_arm): Set bytes_per_chunk and display_endian.
	(print_insn_little_arm): Likewise.
 1997-03-15 22:15:00 +00:00
Ian Lance Taylor
b6fab42bc2 Based on patches from H.J. Lu <hjl@lucon.org>: 
* i386-dis.c (fetch_data): Add prototype.
	* m68k-dis.c (fetch_data): Add prototype.
	(dummy_print_address): Add prototype.  Make static.
	* ppc-opc.c (valid_bo): Add prototype.
	* sparc-dis.c (build_hash_table): Add prototype.
	(is_delayed_branch, compute_arch_mask): Add prototypes.
	(print_insn_sparc): Make several local variables const.
	(compare_opcodes): Change arguments to const PTR.  Add prototype.
	* sparc-opc.c (arg): Change name field to be const.
	(lookup_name, lookup_value): Add prototypes.  Change table and
	name parameters to be const.
	(sparc_encode_asi): Change name parameter to be const.
	(sparc_encode_membar, sparc_encode_prefetch): Likewise.
	(sparc_encode_sparclet_cpreg): Likewise.
	(sparc_decode_asi): Change return type to be const.
	(sparc_decode_membar, sparc_decode_prefetch): Likewise.
	(sparc_decode_sparclet_cpreg): Likewise.
 1997-03-14 20:21:19 +00:00
Jeff Law
a98a3061a6 Update copyrights. 1997-03-07 16:11:48 +00:00
Jeff Law
24e9036af3 update copyrights. 1997-03-07 01:20:29 +00:00
Jeff Law
c654d69e03 * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these 
as relaxable.
For the relaxing assembler.
 1997-03-06 23:52:48 +00:00
J.T. Conklin
c5e5b13f9b * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on 
the mc68000.
 1997-03-03 15:49:49 +00:00
Jim Wilson
a3c5b9a4a1 Correct d10v sanitization errors. 1997-03-03 00:35:40 +00:00
Ian Lance Taylor
0270516b96 Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be> 
* m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction.
 1997-02-27 19:06:15 +00:00
Michael Meissner
dcbf6f077f Deal with 64 bit instruction sizes on the tic80 1997-02-27 16:37:37 +00:00
Michael Meissner
6757ae582b Define r25 1997-02-26 21:59:58 +00:00
Ian Lance Taylor
2ef564d268 Wed Feb 26 13:38:30 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> 
* m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use
	floatformat_to_double to make portable.
	(print_insn_arg): Use NEXTEXTEND macro when extracting extended
	precision float.
 1997-02-26 18:53:18 +00:00
Fred Fish
17990badfc * tic80-opc.c (LSI_SCALED): Renamed from this ... 
(OFF_SL_BR_SCALED): ... to this, and added the flag
	TIC80_OPERAND_BASEREL to the flags word.
	(tic80_opcodes): Replace all occurances of LSI_SCALED with
	OFF_SL_BR_SCALED.
 1997-02-24 21:46:54 +00:00
Ian Lance Taylor
8a974fdc24 update copyrights 1997-02-23 23:05:35 +00:00
Dawn Perchik
a2768484d9 * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3. 
Change mips_opcodes from const array to a pointer,
	and change bfd_mips_num_opcodes from const int to int,
	so that we can increase the size of the mips opcodes table
	dynamically.
 1997-02-23 22:26:01 +00:00
Fred Fish
c7583da0b6 * tic80-opc.c (tic80_predefined_symbols): Revert change to 
store BITNUM values in the table in one's complement form
	to match behavior when assembler is given a raw numeric
	value for a BITNUM operand.
	* tic80-dis.c (print_operand_bitnum): Ditto.
 1997-02-23 04:06:51 +00:00
Martin Hunt
4fe23bdd06 Fri Feb 21 16:31:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d30v-opc.c: Removed references to FLAG_X.
 1997-02-22 00:32:23 +00:00
Michael Meissner
b934926eac Since d10v is public now, remove all sanitization statements 1997-02-20 17:00:14 +00:00
Michael Meissner
c6c7035cfb Since d10v is public now, remove all sanitization statements 1997-02-20 16:05:18 +00:00
Ian Lance Taylor
7adf26304e * Makefile.in: Add dependencies on ../bfd/bfd.h as required. 1997-02-19 19:52:17 +00:00
Martin Hunt
b2e3f8442a Tue Feb 18 17:43:43 1997 Martin M. Hunt <hunt@pizza.cygnus.com> 
* Makefile.in: Added d30v object files.
	* configure: (bfd_d30v_arch) Rebuilt.
	* configure.in: (bfd_d30v_arch) Added new case.
	* d30v-dis.c: New file.
	* d30v-opc.c: New file.
	* disassemble.c (disassembler) Add entry for d30v.
 1997-02-19 01:53:26 +00:00
Fred Fish
49d1bbbef2 * tic80-opc.c (tic80_predefined_symbols): Add symbolic 
representations for the floating point BITNUM values.
 1997-02-18 23:34:35 +00:00
Gavin Romig-Koch
1d339e4849 fixes bugs caused by adding 5900 1997-02-14 18:57:43 +00:00
Ian Lance Taylor
246c54580e Thu Feb 13 21:56:51 1997 Klaus Kaempf <kkaempf@progis.de> 
* makefile.vms: Remove 8 bit characters.  Update to latest
	gcc release.
 1997-02-14 02:57:52 +00:00
Ian Lance Taylor
03514bc871 Thu Feb 13 20:41:22 1997 Philippe De Muyter <phdm@info.ucl.ac.be> 
* m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction.
 1997-02-14 01:43:14 +00:00
Jeff Law
9bd0068fc8 * mn10200-opc.c (IMM16_PCREL): This is a signed operand. 
(IMM24_PCREL): Likewise.
Fixes bugs exposed by disassembler testsuite.
 1997-02-13 23:31:53 +00:00
Ian Lance Taylor
6617b927da * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base 
address for an extended PC relative instruction that is not a
	branch.
 1997-02-13 18:29:25 +00:00
Ian Lance Taylor
d1c52e5b5c Wed Feb 12 12:27:40 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> 
* m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and
	bytes_per_line.
 1997-02-12 17:28:14 +00:00
Fred Fish
e2773136e0 * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'. 
(tic80_opcodes): Sort entries so that long immediate forms
	come after short immediate forms, making it easier for
	assembler to select the right one for a given operand.
 1997-02-11 23:48:15 +00:00
Ian Lance Taylor
2ea116f49b * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and 
display_endian.
	(print_insn_mips16): Likewise.
 1997-02-11 20:46:14 +00:00
Gavin Romig-Koch
276c2d7dc8 Add r5900 1997-02-11 13:26:34 +00:00
Fred Fish
c37555c141 * tic80-opc.c (tic80_symbol_to_value): Changed to accept 
a symbol class that restricts translation to just that
	class (general register, condition code, etc).
 1997-02-10 17:16:28 +00:00
Fred Fish
cceb79baa8 * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E, 
and REG_DEST_E for register operands that have to be
	an even numbered register.  Add REG_FPA for operands that
	are one of the floating point accumulator registers.
	Add TIC80_OPERAND_MASK to flags for ENDMASK operand.
	(tic80_opcodes): Change entries that need even numbered
	register operands to use the new operand table entries.
	Add "or" entries that are identical to "or.tt" entries.
 1997-02-07 00:38:44 +00:00
Ian Lance Taylor
0d52464ce4 * mips16-opc.c: Add new cases of exit instruction for 
disassembler.
	* mips-dis.c (print_mips16_insn_arg): Display floating point
	registers in operands of exit instruction.  Print `$' before
	register names in operands of entry and exit instructions.
 1997-02-05 16:14:26 +00:00
Fred Fish
6cb5b585c5 * tic80-opc.c (tic80_predefined_symbols): Table of name/value 
pairs for all predefined symbols recognized by the assembler.
	Also used by the disassembling routines.
	(tic80_symbol_to_value): New function.
	(tic80_value_to_symbol): New function.
	* tic80-dis.c (print_operand_control_register,
 	print_operand_condition_code, print_operand_bitnum):
	Remove private tables and use tic80_value_to_symbol function.
 1997-01-30 21:16:46 +00:00
Martin Hunt
f28d34be74 Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-dis.c (print_operand): Change address printing
	to correctly handle PC wrapping.  Fixes PR11490.
 1997-01-30 19:33:11 +00:00
Jeff Law
c9f649022e * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative 
branchs relaxable.
 1997-01-29 16:40:15 +00:00
Ian Lance Taylor
20d4301801 * mips-dis.c (print_insn_mips16): Set insn_info information. 
(print_mips16_insn_arg): Likewise.
 1997-01-28 21:49:18 +00:00
Ian Lance Taylor
c4f19df2ef * mips-dis.c (print_insn_mips16): Better handling of an extend 
opcode followed by an instruction which can not be extended.
 1997-01-28 20:58:28 +00:00
J.T. Conklin
071ad7f0e0 * m68k-opc.c (m68k_opcodes): Changed operand specifier for the 
coldfire moveb instruction to not allow an address register as
destination.  Although the documentation does not indicate that
this is invalid, experiments uncovered unexpected behavior.
Added a comment explaining the situation.  Thanks to Andreas
Schwab for pointing this out to me.
 1997-01-24 20:14:26 +00:00
Fred Fish
1eb54bb463 * tic80-opc.c (tic80_opcodes): Expand comment to note that the 
entries are presorted so that entries with the same mnemonic are
	adjacent to each other in the table.  Sort the entries for each
	instruction so that this is true.
 1997-01-23 03:17:45 +00:00
Ian Lance Taylor
84be8dcf9e Mon Jan 20 12:48:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> 
* m68k-dis.c: Include <libiberty.h>.
	(print_insn_m68k): Sort the opcode table on the most significant
	nibble of the opcode.
 1997-01-20 17:50:34 +00:00
Fred Fish
68c7761c42 * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd", 
"vsub", "vst", "xnor", and "xor" instructions.
      (V_a1): Renamed from V_a, msb of accumulator reg number.
      (V_a0): Add macro, lsb of accumulator reg number.
 1997-01-19 22:24:21 +00:00
Fred Fish
8fdffbc4b3 * tic80-dis.c (print_insn_tic80): Broke excessively long 
function up into several smaller ones and arranged for
        the instruction printing function to be callable recursively
        to print vector instructions that have both a load and a
        math instruction packed into a single opcode.
        * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
        to explain why it comes after the other vector opcodes.
 1997-01-19 18:33:10 +00:00
J.T. Conklin
c49bbc27db fix operand mask in the "moveml" entries for the coldfire. 1997-01-18 00:37:30 +00:00
J.T. Conklin
a3d4e445d2 From the coldfire branch: 
* m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
	move insns to handle immediate operands.

From Andreas Schwab:

        * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
 1997-01-18 00:27:23 +00:00
Fred Fish
c977d8fb7b * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V): 
New macros for building vector instruction opcodes.
	(tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and
	FMT_LI, which were unused.  The field is now a flags field.
	Remove some opcodes that are possible, but illegal, such
	as long immediate instructions with doubles for immediate
	values.  Add "vadd" and "vld" instructions.
 1997-01-17 04:00:56 +00:00
Fred Fish
5fdeceb477 * tic80-opc.c (tic80_operands): Reorder some table entries to make 
the order more logical.  Move the shift alias instructions ("rotl",
	"shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be
 	interspersed with the regular sr.x and sl.x instructions.  Add
	and test new instruction opcodes for "sl", "sli", "sr", "sri", "st",
 	"sub", "subu", "swcr", and "trap".
 1997-01-16 02:10:17 +00:00
Fred Fish
003df61759 * tic80-dis.c (print_insn_tic80): Print floating point operands 
as floats.
      * tic80-opc.c (SPFI): Add single precision floating point
      immediate operand type.
      (ROTATE): Add rotate operand type for shifts.
      (ENDMASK): Add for shifts.
      (n): Macro for the 'n' bit.
      (i): Macro for the 'i' bit.
      (PD): Macro for the 'PD' field.
      (P2): Macro for the 'P2' field.
      (P1): Macro for the 'P1' field.
      (tic80_operands): Add entries for "exts", "extu", "fadd",
      "fcmp", and "fdiv".
 1997-01-13 23:05:49 +00:00
Jeff Law
1b8a127fe7 Fix copyright. 1997-01-06 22:14:13 +00:00
Jeff Law
09171e3fe6 * mn10200-dis.c (disassemble): Mask off unwanted bits after 
adding in current address for pc-relative operands.
Fixes disassembly of backwards 24bit pc-relative addressese.
 1997-01-06 22:13:39 +00:00
Fred Fish
50965d0ec2 * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit. 
(print_insn_tic80): If R_SCALED then print ":s" modifier for operand.
	* tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
	changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
	(SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
	REG_BASE_M_SI, REG_BASE_M_LI respectively.
	(REG_SCALED, LSI_SCALED): New operand types.
	(E): New macro for 'E' bit at bit 27.
	(tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap
	opcodes, including the various size flavors (b,h,w,d) for
	the direct load and store instructions.
 1997-01-06 18:04:38 +00:00
Fred Fish
937fe72232 * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit 
in an instruction.
	* tic80-dis.c (print_insn_tic80): Change comma and paren handling.
  	Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
	* tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands.
	(F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New	bit-twiddlers.
	(MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
	masks with "MASK_* & ~M_*" to get the M bit reset.
	(tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
 1997-01-05 19:29:42 +00:00
Fred Fish
1f8c8c60a1 * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE 
correctly.  Add support for printing TIC80_OPERAND_BITNUM and
	TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic
	form.
	* tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM,
	CC, SICR, and LICR table entries.
	(tic80_opcodes): Add and test "nop", "br", "bbo", "bbz",
	"bcnd", and "brcr" opcodes.
 1997-01-05 02:10:14 +00:00
Fred Fish
872dc6f0bc * ppc-opc.c (powerpc_operands): Make comment match the 
actual fields (no shift field).
	* sparc-opc.c (sparc_opcodes): Document why this cannot be "const".

	* tic80-dis.c (print_insn_tic80): Replace abort stub with a
	partial implementation, work in progress.
	* tic80-opc.c (tic80_operands): Begin construction operands table.
	(tic80_opcodes): Continue populating opcodes table and start
	filling in the operand indices.
	(tic80_num_opcodes): Add this.
 1997-01-04 01:39:30 +00:00
Ian Lance Taylor
a3ecb49f4b * m68k-opc.c: Add #B case for moveq. 1997-01-03 17:14:30 +00:00
Jeff Law
bc83032148 * mn10300-dis.c (disassemble): Make sure all variables are initialized 
before they are used.
Fixes various weird disassembly problems.
 1997-01-02 19:21:36 +00:00
Jeff Law
160cca6457 * v850-opc.c (v850_opcodes): Put curly-braces around operands 
for "breakpoint" instruction.
Fixes random assembler failures for hp-x-v850 toolchain.
 1996-12-31 21:20:00 +00:00
Ian Lance Taylor
1a4752c664 * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE. 
(dep): Use ALL_CFLAGS rather than CFLAGS.
 1996-12-31 20:38:45 +00:00
Michael Meissner
0068e79cc5 Set V850_OPERAND_ADJUST_SHORT_MEMORY flag on sst.{h,w}/sld.{h,w} instructions 1996-12-31 20:11:39 +00:00
Ken Raeburn
f204f75257 End tic80 sanitization regions with "end-sanitize-tic80", not 
with "start-sanitize-tic80".
 1996-12-31 17:51:22 +00:00
Fred Fish
39620b712c * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency. 
(tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in.
 1996-12-31 00:09:59 +00:00
Ian Lance Taylor
ea6c562019 * mips16-opc.c: Add "abs". 1996-12-30 16:38:24 +00:00
Fred Fish
a79d0193ec * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o. 
* disassemble.c (ARCH_tic80): Define if ARCH_all is defined.
	(disassembler): Add bfd_arch_tic80 support to set disassemble
 	to print_insn_tic80.
	* tic80-dis.c (print_insn_tic80): Add stub.
 1996-12-29 18:01:29 +00:00
Fred Fish
6357e7f68e (Laying groundwork (that will be incrementally fleshed out) for TIc80 support) 
* configure.in (arch in $selarchs): Add bfd_tic80_arch entry.
	* configure: Regenerate with autoconf.
	* tic80-dis.c: Add file.
	* tic80-opc.c: Add file.
 1996-12-28 05:36:52 +00:00
Martin Hunt
b5baebe405 Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (pre_defined_registers):  Add cr[0-15], dpc, dpsw, link.
 1996-12-20 22:32:16 +00:00
Jeff Law
e098bae8e7 * mn10200-opc.c (mn10200_operands): Add SIMM16N. 
(mn10200_opcodes): Use it for some logicals and btst insns.
        Add "break" and "trap" instructions.
 1996-12-18 17:12:16 +00:00
Jeff Law
374cb3020b * mn10300-opc.c (mn10300_opcodes): Add "break" instruction. 
For gdb.
 1996-12-16 22:28:24 +00:00
Jeff Law
d21f1eae7d * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)". 1996-12-16 20:05:07 +00:00
Ian Lance Taylor
39e5bea281 * mips-dis.c (print_mips16_insn_arg): The base address of a PC 
relative load or add now depends upon whether the instruction is
	in a delay slot.
 1996-12-15 03:37:08 +00:00
Jeff Law
c6b62ad1d7 * mn10200-dis.c: Finish writing disassembler. 
* mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn".
        Fix mask for "jmp (an)".
mn10200 disassembler works!
 1996-12-12 08:09:27 +00:00
Jeff Law
77955104ba * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently 
handle endianness issues for mn10300.
 1996-12-11 17:34:15 +00:00
Jeff Law
532700fc31 * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)". 
Yoshihiro Adachi sez the manual was wrong for this insn.
 1996-12-11 16:29:02 +00:00
Jeff Law
7bfc95d917 * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2 
instruction.  Fix opcode field for "movb (imm24),dn".
Stuff found by the testsuite.
 1996-12-10 20:34:14 +00:00
Jeff Law
0888b4a38a * mn10200-opc.c (mn10200_operands): Fix insertion position 
for DI operand.
Found by gas testsuite.
 1996-12-10 19:13:07 +00:00
Jeff Law
781766e7e1 * mn10200-opc.c: Create mn10200 opcode table. 
* mn10200-dis.c: Flesh out mn10200 disassembler.  Not ready,
        but moving along nicely.
Checkpointing today's mn10200 work.
 1996-12-09 23:48:15 +00:00
Peter Schauer
b65415a446 * Makefile.in (ALL_MACHINES): Add mips16-opc.o. 1996-12-08 12:35:28 +00:00
J.T. Conklin
6827a1c758 * m68k-opc.c (m68k_opcodes): Revert change to use < and > 
specifiers for fmovem* instructions.
 1996-12-07 00:54:51 +00:00
Jeff Law
4db788a664 * mn10300-dis.c (disassemble): Remove '$' register prefixing. 1996-12-06 22:40:31 +00:00
Ian Lance Taylor
34212ec3f6 * mips16-opc.c: Change opcode for entry/exit to avoid conflicting 
with dsrl.
 1996-12-06 22:35:01 +00:00
Jeff Law
8329699005 * mn10300-opc.c: Add some comments explaining the various 
operands and such.

        * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
 1996-12-06 22:04:12 +00:00
J.T. Conklin
e72d5a50f9 * m68k-dis.c (print_insn_arg): Handle new < and > operand 
specifiers.
* m68k-opc.c (m68k_opcodes): Simplify table by using < and >
operand specifiers in fmovm* instructions.
 1996-12-05 20:12:47 +00:00
Ian Lance Taylor
70eb6bdd65 * ppc-opc.c (insert_li): Give an error if the offset has the two 
least significant bits set.
PR 11201.
 1996-12-04 19:53:09 +00:00
Jeff Law
069279b34a * mn10300-dis.c (disasemble): Finish conversion to '$' as 
register prefix.
Fixes improper disassembly of movm instructions.
 1996-11-26 23:04:02 +00:00
Ian Lance Taylor
0e809bba05 * configure: Rebuild with autoconf 2.12. 1996-11-26 21:59:23 +00:00
Jeff Law
23b01150f5 * mn10300-opc.c (mn10300_opcodes): Fix mask field for 
mov am,(imm32,sp).
Found during initial simulator work.
 1996-11-26 20:28:34 +00:00
Ian Lance Taylor
8d67dc3077 Add support for mips16 (16 bit MIPS implementation): 
* mips16-opc.c: New file.
	* mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
	(mips16_reg_names): New static array.
	(print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
	after seeing a 16 bit symbol.
	(print_insn_little_mips): Likewise.
	(print_insn_mips16): New static function.
	(print_mips16_insn_arg): New static function.
	* mips-opc.c: Add jalx instruction.
	* Makefile.in (mips16-opc.o): New target.
	* configure.in: Use mips16-opc.o for bfd_mips_arch.
	* configure: Rebuild.
 1996-11-26 15:59:18 +00:00
J.T. Conklin
520e44a15a * m68k-opc.c (m68k_opcodes): Simplify table by using < and > 
operand specifiers in *save, *restore and movem* instructions.
 1996-11-26 03:24:55 +00:00
J.T. Conklin
da34628ad8 * m68k-opc.c (m68k-opcodes): Fix move and movem instructions for 
the coldfire.
 1996-11-26 01:54:16 +00:00
J.T. Conklin
0dd19a8f36 * m68k-opc.c (m68k-opcodes): Fix many forms of the move 
instruction for the coldfire.
 1996-11-26 00:17:17 +00:00
J.T. Conklin
09d205d155 * m68k-opc.c (m68k-opcodes): The coldfire (mcf5200) can only use 
register operands for immediate arithmetic, not, neg, negx, and
set according to condition instructions.
 1996-11-25 22:33:46 +00:00
J.T. Conklin
1852237cf4 * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage 
specifier of the effective-address operand in immediate forms of
arithmetic instructions.  The specifier for the immediate operand
notes how and where the constant will be stored.
 1996-11-25 21:39:55 +00:00
Jeff Law
731c7b4bb8 * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc" 
opcode.
 1996-11-25 19:46:21 +00:00
Jeff Law
76783aa31c * mn10300-dis.c (disassemble): Use '$' instead of '%' for 
register prefix.
It's easier for the assembler...
 1996-11-25 18:46:06 +00:00
Jeff Law
11cd057a41 * mn10300-dis.c (disassemble): Prefix registers with '%'. 1996-11-25 18:21:08 +00:00
Jeff Law
f0e98103c5 * mn10300-dis.c (disassemble): Handle register lists. 
More disassembler stuff.
 1996-11-20 18:39:48 +00:00
Jeff Law
f039819018 * mn10300-opc.c: Fix handling of register list operand for 
"call", "ret", and "rets" instructions.
Stuff noticed while working on disasembler.
 1996-11-20 18:32:44 +00:00
Jeff Law
aa9c04cd55 * mn10300-dis.c (disassemble): Print PC-relative and memory 
addresses symbolically if possible.
        * mn10300-opc.c: Distinguish between absolute memory addresses,
        pc-relative offsets & random immediates.
More disassembler work.
 1996-11-20 18:02:31 +00:00
Jeff Law
f497f3ae7c * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte 
in 7 byte insns.
        (disassemble): Handle SPLIT and EXTENDED operands.
 1996-11-20 17:36:31 +00:00
Jeff Law
d91028d2c7 * mn10300-dis.c: Rough cut at printing some operands. 1996-11-20 00:55:22 +00:00
Jeff Law
4aa92185f8 * mn10300-dis.c: Start working on disassembler support. 
* mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.
Selects opcodes & consumes bytes.  Breaks badly if given data instead of
code.  No operands yet.
 1996-11-19 23:59:27 +00:00
Jeff Law
99246e03f9 * mn10300-opc.c (mn10300_operands): Add "REGS" for a register 
list.
        (mn10300_opcodes): Use REGS for register list in "movm" instructions.
 1996-11-19 20:32:31 +00:00
Michael Meissner
b337f8691f Add3 sets the carry 1996-11-18 20:21:55 +00:00
Jeff Law
54dfaf0a65 * mn10300-opc.c (mn10300_opcodes): Demand parens around 
register argument is calls and jmp instructions.
Found trying to build libgcc2 for the mn10300 :-)
 1996-11-15 20:43:44 +00:00
Jeff Law
f2ab9a7505 * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and 
getx operand.  Fix opcode for mulqu imm,dn.
Fix bugs exposed by gas testsuite (extended instructions).
 1996-11-07 07:26:25 +00:00
Jeff Law
26433754cc * mn10300-opc.c (mn10300_operands): Hijack "bits" field 
in MN10300_OPERAND_SPLIT operands for how many bits
        appear in the basic insn word.  Add IMM32_HIGH24,
        IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
        (mn10300_opcodes): Use new operands as needed.
Support for everything in the basic instruction manual (yippie!)
 1996-11-06 21:58:21 +00:00
Jeff Law
64ce06688d * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8 
for bset, bclr, btst instructions.
        (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.
For btst, bclr & bset.
 1996-11-06 21:18:27 +00:00
Jeff Law
fdef41f30b * mn10300-opc.c (mn10300_operands): Remove many redundant 
operands.  Update opcode table as appropriate.
        (IMM32): Add MN10300_OPERAND_SPLIT flag.
        (mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
Cleaning up a little.
Attempting to insert most 32bit operands.
And a bug found by assembler testsuite.
 1996-11-06 20:44:58 +00:00
Jeff Law
bb5e141ab4 * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2 
operands (for indexed load/stores).  Fix bitpos for DI
        operand.  Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
        few instructions that insert immediates/displacements in the
        middle of the instruction.  Add IMM8E for 8 bit immediate in
        the extended part of an instruction.
        (mn10300_operands): Use new opcodes as appropriate.
Opcode table changes so we can correctly insert everything except
32bit operands.
 1996-11-05 20:29:31 +00:00
Martin Hunt
733861650a Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_opcodes): Declare the trap instruction
 	sequential so the assembler never parallelizes it with
	other instructions.
 1996-11-05 18:34:19 +00:00
Jeff Law
e85c140a27 * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for 
a data/address register that appears in register field 0
        and register field 1.
        (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN

Hacking Matsushita again.  Yippie!
 1996-11-04 19:51:31 +00:00
Ian Lance Taylor
03e9562378 Fri Nov 1 10:29:11 1996 Richard Henderson <rth@tamu.edu> 
* alpha-dis.c (print_insn_alpha): Use new NOPAL mask for
	standard disassembly.

	* alpha-opc.c (alpha_operands): Rearrange flags slot.
	(alpha_opcodes): Add new BWX, CIX, and MAX instructions.
	Recategorize PALcode instructions.
 1996-11-01 18:30:43 +00:00
Jeff Law
7d2759fc5b * v850-opc.c (v850_opcodes): Add relaxing "jbr". 1996-10-30 23:52:31 +00:00
Ian Lance Taylor
b56c3d6cee * mips-dis.c (_print_insn_mips): Don't print a trailing tab if 
there are no operand types.
 1996-10-29 21:31:22 +00:00
Jeff Law
244558e354 * v850-opc.c (D9_RELAX): Renamed from D9, all references 
changed.
        (v850_operands): Make sure D22 immediately follows D9_RELAX.
 1996-10-29 19:25:35 +00:00
Jeff Law
0f02ae6e5a * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for 
"bCC"instructions).
Because quantum's code uses jnz, jcc, etc etc etc.
 1996-10-24 23:55:11 +00:00
Ian Lance Taylor
4f6d7c2c30 * mips-dis.c (_print_insn_mips): Use a tab between the instruction 
and the arguments.
 1996-10-24 21:21:37 +00:00
Ian Lance Taylor
de145351e8 * ppc-opc.c (PPCPWR2): Define. 
(powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating
	it.
 1996-10-23 03:34:07 +00:00
Jeff Law
63dc694d29 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode 
field for movhu instruction.
Bug found by gas testsuite.

        * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
        cast value to "long" not "signed long" to keep hpux10
        compiler quiet.
Found in an attempt to build the v850 on hpux10 with the HP
compiler.
 1996-10-11 22:06:47 +00:00
Jeff Law
02d4ad193b * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field 
for mov (abs16),DN.
Bug found by gas testsuite.  Matsushita.
 1996-10-10 21:42:01 +00:00
Jeff Law
ba8ed10c7e * mn10300-opc.c (FMT*): Remove definitions. 
Moved into opcode/mn10300.h
 1996-10-10 20:31:06 +00:00
Jeff Law
1e5ddd3be4 * mn10300-opc.c (mn10300_opcodes): Fix destination register 
for shift-by-register opcodes.
Bug found by testsuite.
 1996-10-10 19:08:46 +00:00
Jeff Law
36b34aa4a9 * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM 
into [AD][MN][01] for encoding the position of the register
        in the opcode.
Matsushita.
 1996-10-10 16:28:14 +00:00
Jeff Law
344d6417bb * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, 
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
Matsushita.
 1996-10-09 17:20:59 +00:00
Jeff Law
db22905430 * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. 
Fix various typos.  Add "PAREN" operand.
        (MEM, MEM2): Define.
        (mn10300_opcodes): Surround all memory addresses with "PAREN"
        operands.  Fix several typos.
Should parse all opcodes in the instruction specification, except the
"user extension instructions".
 1996-10-08 21:09:57 +00:00
Jeff Law
06b796584d * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's 
changes.
Matsushita.
 1996-10-08 17:56:40 +00:00
Jeff Law
5ab7bce62d * mn10300-opc.c (FMT_XX): Renumber starting at one. 
(mn10300_operands): Rough cut.  Enough to parse "mov" instructions
        at this time.
        (mn10300_opcodes): Break opcode format out into its own field.
        Update many operand fields to deal with signed vs unsigned
        issues.  Fix one or two typos in the "mov" instruction
        opcode, mask and/or operand fields.
Checkpointing today's work.  Matsushita.
 1996-10-07 22:52:18 +00:00
Ian Lance Taylor
6ba7ecd4eb Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> 
* m68k-opc.c (plusha): Prefer encoding for m68040up, in case
	m68851 wasn't reset.
 1996-10-07 15:41:56 +00:00
Jeff Law
99777c0bfb * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for 
all opcodes.  Very rough cut at operands for all opcodes.
Matsushita.
 1996-10-04 22:02:43 +00:00
Jeff Law
cd8a9026b9 * mn10300-opc.c (mn10300_opcodes): Start fleshing out the 
opcode table.
Checkpointint 10300 work.
 1996-10-04 19:20:19 +00:00
Ian Lance Taylor
6c9370db2a * Makefile.in (ALL_MACHINES): Add mn10200-dis.o, mn10200-opc.o, 
mn10300-dis.o, and mn10300-opc.o.
Also add d10v and v850 files, with appropriate sanitization.
 1996-10-03 21:17:46 +00:00
Jeff Law
ae1b99e42d Grrr. The mn10200 and mn10300 are _not_ similar enough to easily support 
with a single generic configuration.  So break them up into two different
configurations.  See the individual ChangeLogs for additional detail.
 1996-10-03 16:42:22 +00:00
Jason Molenda
42b4add910 * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. 1996-10-03 06:58:15 +00:00
Jeff Law
e7c50ceffd * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita 
MN10x00 processors.
        * disassemble (ARCH_mn10x00): Define.
        (disassembler): Handle bfd_arch_mn10x00.
        * configure.in: Recognize bfd_mn10x00_arch.
        * configure: Rebuilt.
Continue stubbing out for Matsushita work.
 1996-10-03 05:31:01 +00:00
Jeff Law
072b27ea5e Add missing copyright. 1996-10-03 04:48:16 +00:00
Ian Lance Taylor
a5cb84dd6f * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses 
accordingly.  Don't declare functions using op_rtn.
Remove ANSI C constructs.
 1996-10-01 14:50:19 +00:00
Ian Lance Taylor
800bda836e * mips-opc.c: Add a case for "div" and "divu" with two registers 
and a destination of $0.
PR 10654.
 1996-09-17 16:07:41 +00:00
Fred Fish
d7deed257c * mips-dis.c (print_insn_arg): Add prototype. 
(_print_insn_mips): Ditto.
 1996-09-11 04:26:58 +00:00
Ian Lance Taylor
30b1724cc8 * mips-dis.c (print_insn_arg): Print condition code registers as 
$fccN.
 1996-09-09 18:27:10 +00:00
Jeff Law
eb5c28e173 * v850-dis.c (disassemble): Make static. Provide prototype. 1996-09-03 18:05:25 +00:00
Ian Lance Taylor
44789bee66 whoops--typo 1996-09-02 16:41:29 +00:00