* m10200-dis.c: Rename from mn10200-dis.c.
* m10200-opc.c: Rename from mn10200-opc.c. * m10300-dis.c: Rename from mn10300-dis.c * m10300-opc.c: Rename from mn10300-opc.c. * Makefile.in: Update accordingly.
This commit is contained in:
Ian Lance Taylor
parent
e46ea72de6
commit
28e8de4165
5 changed files with 4 additions and 1391 deletions
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@ -86,10 +86,10 @@ makefile.vms
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mips-dis.c
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mips-opc.c
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mips16-opc.c
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mn10200-dis.c
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mn10200-opc.c
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mn10300-dis.c
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mn10300-opc.c
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m10200-dis.c
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m10200-opc.c
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m10300-dis.c
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m10300-opc.c
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mpw-config.in
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mpw-make.sed
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ns32k-dis.c
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@ -1,334 +0,0 @@
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/* Disassemble MN10200 instructions.
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Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "ansidecl.h"
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#include "opcode/mn10200.h"
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#include "dis-asm.h"
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static void disassemble PARAMS ((bfd_vma, struct disassemble_info *,
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unsigned long insn, unsigned long,
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unsigned int));
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int
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print_insn_mn10200 (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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int status;
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bfd_byte buffer[4];
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unsigned long insn, extension;
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unsigned int consume;
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/* First figure out how big the opcode is. */
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status = (*info->read_memory_func) (memaddr, buffer, 1, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = *(unsigned char *) buffer;
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/* These are one byte insns. */
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if ((insn & 0xf0) == 0x00
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|| (insn & 0xf0) == 0x10
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|| (insn & 0xf0) == 0x20
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|| (insn & 0xf0) == 0x30
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|| ((insn & 0xf0) == 0x80
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&& (insn & 0x0c) >> 2 != (insn & 0x03))
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|| (insn & 0xf0) == 0x90
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|| (insn & 0xf0) == 0xa0
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|| (insn & 0xf0) == 0xb0
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|| (insn & 0xff) == 0xeb
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|| (insn & 0xff) == 0xf6
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|| (insn & 0xff) == 0xfe)
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{
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extension = 0;
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consume = 1;
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}
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/* These are two byte insns. */
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else if ((insn & 0xf0) == 0x40
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|| (insn & 0xf0) == 0x50
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|| (insn & 0xf0) == 0x60
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|| (insn & 0xf0) == 0x70
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|| (insn & 0xf0) == 0x80
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|| (insn & 0xfc) == 0xd0
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|| (insn & 0xfc) == 0xd4
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|| (insn & 0xfc) == 0xd8
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|| (insn & 0xfc) == 0xe0
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|| (insn & 0xfc) == 0xe4
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|| (insn & 0xff) == 0xe8
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|| (insn & 0xff) == 0xe9
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|| (insn & 0xff) == 0xea
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|| (insn & 0xff) == 0xf0
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|| (insn & 0xff) == 0xf1
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|| (insn & 0xff) == 0xf2
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|| (insn & 0xff) == 0xf3)
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{
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status = (*info->read_memory_func) (memaddr, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getb16 (buffer);
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consume = 2;
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}
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/* These are three byte insns with a 16bit operand in little
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endian form. */
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else if ((insn & 0xf0) == 0xc0
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|| (insn & 0xfc) == 0xdc
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|| (insn & 0xfc) == 0xec
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|| (insn & 0xff) == 0xf8
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|| (insn & 0xff) == 0xf9
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|| (insn & 0xff) == 0xfa
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|| (insn & 0xff) == 0xfb
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|| (insn & 0xff) == 0xfc
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|| (insn & 0xff) == 0xfd)
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{
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status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn <<= 16;
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insn |= bfd_getl16 (buffer);
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extension = 0;
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consume = 3;
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}
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/* These are three byte insns too, but we don't have to mess with
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endianness stuff. */
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else if ((insn & 0xff) == 0xf5)
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{
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status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn <<= 16;
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insn |= bfd_getb16 (buffer);
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extension = 0;
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consume = 3;
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}
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/* These are four byte insns. */
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else if ((insn & 0xff) == 0xf7)
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{
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status = (*info->read_memory_func) (memaddr, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getb16 (buffer);
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insn <<= 16;
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status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn |= bfd_getl16 (buffer);
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extension = 0;
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consume = 4;
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}
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/* These are five byte insns. */
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else if ((insn & 0xff) == 0xf4)
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{
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status = (*info->read_memory_func) (memaddr, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getb16 (buffer);
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insn <<= 16;
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status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn |= *(unsigned char *)buffer << 8;
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status = (*info->read_memory_func) (memaddr + 3, buffer, 1, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn |= *(unsigned char *)buffer;
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status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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extension = *(unsigned char *)buffer;
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consume = 5;
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}
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else
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return -1;
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disassemble (memaddr, info, insn, extension, consume);
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return consume;
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}
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static void
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disassemble (memaddr, info, insn, extension, size)
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bfd_vma memaddr;
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struct disassemble_info *info;
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unsigned long insn;
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unsigned long extension;
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unsigned int size;
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{
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struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes;
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const struct mn10200_operand *operand;
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int match = 0;
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/* Find the opcode. */
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while (op->name)
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{
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int mysize, extra_shift;
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if (op->format == FMT_1)
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mysize = 1;
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else if (op->format == FMT_2
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|| op->format == FMT_4)
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mysize = 2;
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else if (op->format == FMT_3
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|| op->format == FMT_5)
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mysize = 3;
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else if (op->format == FMT_6)
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mysize = 4;
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else if (op->format == FMT_7)
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mysize = 5;
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else
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abort ();
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if (op->format == FMT_2 || op->format == FMT_5)
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extra_shift = 8;
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else if (op->format == FMT_3
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|| op->format == FMT_6
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|| op->format == FMT_7)
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extra_shift = 16;
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else
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extra_shift = 0;
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if ((op->mask & insn) == op->opcode
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&& size == mysize)
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{
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const unsigned char *opindex_ptr;
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unsigned int nocomma;
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int paren = 0;
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match = 1;
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(*info->fprintf_func) (info->stream, "%s\t", op->name);
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/* Now print the operands. */
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for (opindex_ptr = op->operands, nocomma = 1;
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*opindex_ptr != 0;
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opindex_ptr++)
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{
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unsigned long value;
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operand = &mn10200_operands[*opindex_ptr];
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if ((operand->flags & MN10200_OPERAND_EXTENDED) != 0)
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{
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value = (insn & 0xffff) << 8;
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value |= extension;
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}
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else
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{
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value = ((insn >> (operand->shift))
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& ((1 << operand->bits) - 1));
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}
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if ((operand->flags & MN10200_OPERAND_SIGNED) != 0)
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value = ((long)(value << (32 - operand->bits))
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>> (32 - operand->bits));
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if (!nocomma
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&& (!paren
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|| ((operand->flags & MN10200_OPERAND_PAREN) == 0)))
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(*info->fprintf_func) (info->stream, ",");
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nocomma = 0;
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if ((operand->flags & MN10200_OPERAND_DREG) != 0)
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{
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value = ((insn >> (operand->shift + extra_shift))
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& ((1 << operand->bits) - 1));
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(*info->fprintf_func) (info->stream, "d%d", value);
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}
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else if ((operand->flags & MN10200_OPERAND_AREG) != 0)
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{
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value = ((insn >> (operand->shift + extra_shift))
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& ((1 << operand->bits) - 1));
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(*info->fprintf_func) (info->stream, "a%d", value);
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}
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else if ((operand->flags & MN10200_OPERAND_PSW) != 0)
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(*info->fprintf_func) (info->stream, "psw");
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else if ((operand->flags & MN10200_OPERAND_MDR) != 0)
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(*info->fprintf_func) (info->stream, "mdr");
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else if ((operand->flags & MN10200_OPERAND_PAREN) != 0)
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{
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if (paren)
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(*info->fprintf_func) (info->stream, ")");
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else
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{
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(*info->fprintf_func) (info->stream, "(");
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nocomma = 1;
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}
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paren = !paren;
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}
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else if ((operand->flags & MN10200_OPERAND_PCREL) != 0)
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(*info->print_address_func) ((value + memaddr) & 0xffffff, info);
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else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0)
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(*info->print_address_func) (value, info);
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else
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(*info->fprintf_func) (info->stream, "%d", value);
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}
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/* All done. */
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break;
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}
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op++;
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}
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if (!match)
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{
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(*info->fprintf_func) (info->stream, "unknown\t0x%04x", insn);
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}
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}
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@ -1,539 +0,0 @@
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/* Disassemble MN10300 instructions.
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Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
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(at your option) any later version.
|
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|
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This program is distributed in the hope that it will be useful,
|
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but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
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#include <stdio.h>
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#include "ansidecl.h"
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#include "opcode/mn10300.h"
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#include "dis-asm.h"
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static void disassemble PARAMS ((bfd_vma, struct disassemble_info *,
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unsigned long insn, unsigned int));
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int
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print_insn_mn10300 (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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int status;
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bfd_byte buffer[4];
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unsigned long insn;
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unsigned int consume;
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|
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/* First figure out how big the opcode is. */
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status = (*info->read_memory_func) (memaddr, buffer, 1, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = *(unsigned char *) buffer;
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/* These are one byte insns. */
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if ((insn & 0xf3) == 0x00
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|| (insn & 0xf0) == 0x10
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|| (insn & 0xfc) == 0x3c
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|| (insn & 0xf3) == 0x41
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|| (insn & 0xf3) == 0x40
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|| (insn & 0xfc) == 0x50
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|| (insn & 0xfc) == 0x54
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|| (insn & 0xf0) == 0x60
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|| (insn & 0xf0) == 0x70
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|| ((insn & 0xf0) == 0x80
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&& (insn & 0x0c) >> 2 != (insn & 0x03))
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|| ((insn & 0xf0) == 0x90
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&& (insn & 0x0c) >> 2 != (insn & 0x03))
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|| ((insn & 0xf0) == 0xa0
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&& (insn & 0x0c) >> 2 != (insn & 0x03))
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|| ((insn & 0xf0) == 0xb0
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&& (insn & 0x0c) >> 2 != (insn & 0x03))
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|| (insn & 0xff) == 0xcb
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|| (insn & 0xfc) == 0xd0
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|| (insn & 0xfc) == 0xd4
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|| (insn & 0xfc) == 0xd8
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|| (insn & 0xf0) == 0xe0)
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||||
{
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consume = 1;
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||||
}
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/* These are two byte insns. */
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else if ((insn & 0xf0) == 0x80
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||||
|| (insn & 0xf0) == 0x90
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||||
|| (insn & 0xf0) == 0xa0
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||||
|| (insn & 0xf0) == 0xb0
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|| (insn & 0xfc) == 0x20
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||||
|| (insn & 0xfc) == 0x28
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|| (insn & 0xf3) == 0x43
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|| (insn & 0xf3) == 0x42
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|| (insn & 0xfc) == 0x58
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|| (insn & 0xfc) == 0x5c
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|| ((insn & 0xf0) == 0xc0
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&& (insn & 0xff) != 0xcb
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&& (insn & 0xff) != 0xcc
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&& (insn & 0xff) != 0xcd)
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|| (insn & 0xff) == 0xf0
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|| (insn & 0xff) == 0xf1
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|| (insn & 0xff) == 0xf2
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|| (insn & 0xff) == 0xf3
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||||
|| (insn & 0xff) == 0xf4
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||||
|| (insn & 0xff) == 0xf5
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||||
|| (insn & 0xff) == 0xf6)
|
||||
{
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status = (*info->read_memory_func) (memaddr, buffer, 2, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
insn = bfd_getb16 (buffer);
|
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consume = 2;
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||||
}
|
||||
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/* These are three byte insns. */
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else if ((insn & 0xff) == 0xf8
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|| (insn & 0xff) == 0xcc
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|| (insn & 0xff) == 0xf9
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|| (insn & 0xf3) == 0x01
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||||
|| (insn & 0xf3) == 0x02
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|| (insn & 0xf3) == 0x03
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|| (insn & 0xfc) == 0x24
|
||||
|| (insn & 0xfc) == 0x2c
|
||||
|| (insn & 0xfc) == 0x30
|
||||
|| (insn & 0xfc) == 0x34
|
||||
|| (insn & 0xfc) == 0x38
|
||||
|| (insn & 0xff) == 0xde
|
||||
|| (insn & 0xff) == 0xdf
|
||||
|| (insn & 0xff) == 0xcc)
|
||||
{
|
||||
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
insn = bfd_getb16 (buffer);
|
||||
insn <<= 8;
|
||||
status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
insn |= *(unsigned char *)buffer;
|
||||
consume = 3;
|
||||
}
|
||||
|
||||
/* These are four byte insns. */
|
||||
else if ((insn & 0xff) == 0xfa
|
||||
|| (insn & 0xff) == 0xfb)
|
||||
{
|
||||
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
insn = bfd_getb32 (buffer);
|
||||
consume = 4;
|
||||
}
|
||||
|
||||
/* These are five byte insns. */
|
||||
else if ((insn & 0xff) == 0xcd
|
||||
|| (insn & 0xff) == 0xdc)
|
||||
{
|
||||
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
insn = bfd_getb32 (buffer);
|
||||
consume = 5;
|
||||
}
|
||||
|
||||
/* These are six byte insns. */
|
||||
else if ((insn & 0xff) == 0xfd
|
||||
|| (insn & 0xff) == 0xfc)
|
||||
{
|
||||
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
insn = bfd_getb32 (buffer);
|
||||
consume = 6;
|
||||
}
|
||||
|
||||
/* Else its a seven byte insns (in theory). */
|
||||
else
|
||||
{
|
||||
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
insn = bfd_getb32 (buffer);
|
||||
consume = 7;
|
||||
}
|
||||
|
||||
disassemble (memaddr, info, insn, consume);
|
||||
|
||||
return consume;
|
||||
}
|
||||
|
||||
static void
|
||||
disassemble (memaddr, info, insn, size)
|
||||
bfd_vma memaddr;
|
||||
struct disassemble_info *info;
|
||||
unsigned long insn;
|
||||
unsigned int size;
|
||||
{
|
||||
struct mn10300_opcode *op = (struct mn10300_opcode *)mn10300_opcodes;
|
||||
const struct mn10300_operand *operand;
|
||||
bfd_byte buffer[4];
|
||||
unsigned long extension = 0;
|
||||
int status, match = 0;
|
||||
|
||||
/* Find the opcode. */
|
||||
while (op->name)
|
||||
{
|
||||
int mysize, extra_shift;
|
||||
|
||||
if (op->format == FMT_S0)
|
||||
mysize = 1;
|
||||
else if (op->format == FMT_S1
|
||||
|| op->format == FMT_D0)
|
||||
mysize = 2;
|
||||
else if (op->format == FMT_S2
|
||||
|| op->format == FMT_D1)
|
||||
mysize = 3;
|
||||
else if (op->format == FMT_S4)
|
||||
mysize = 5;
|
||||
else if (op->format == FMT_D2)
|
||||
mysize = 4;
|
||||
else if (op->format == FMT_D4)
|
||||
mysize = 6;
|
||||
else
|
||||
mysize = 7;
|
||||
|
||||
if ((op->mask & insn) == op->opcode
|
||||
&& size == mysize)
|
||||
{
|
||||
const unsigned char *opindex_ptr;
|
||||
unsigned int nocomma;
|
||||
int paren = 0;
|
||||
|
||||
if (op->format == FMT_D1 || op->format == FMT_S1)
|
||||
extra_shift = 8;
|
||||
else if (op->format == FMT_D2 || op->format == FMT_D4
|
||||
|| op->format == FMT_S2 || op->format == FMT_S4
|
||||
|| op->format == FMT_S6 || op->format == FMT_D5)
|
||||
extra_shift = 16;
|
||||
else
|
||||
extra_shift = 0;
|
||||
|
||||
if (size == 1 || size == 2)
|
||||
{
|
||||
extension = 0;
|
||||
}
|
||||
else if (size == 3
|
||||
&& (op->format == FMT_D1
|
||||
|| op->opcode == 0xdf0000
|
||||
|| op->opcode == 0xde0000))
|
||||
{
|
||||
extension = 0;
|
||||
}
|
||||
else if (size == 3)
|
||||
{
|
||||
insn &= 0xff0000;
|
||||
status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return;
|
||||
}
|
||||
|
||||
insn |= bfd_getl16 (buffer);
|
||||
extension = 0;
|
||||
}
|
||||
else if (size == 4
|
||||
&& (op->opcode == 0xfaf80000
|
||||
|| op->opcode == 0xfaf00000
|
||||
|| op->opcode == 0xfaf40000))
|
||||
{
|
||||
extension = 0;
|
||||
}
|
||||
else if (size == 4)
|
||||
{
|
||||
insn &= 0xffff0000;
|
||||
status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return;
|
||||
}
|
||||
|
||||
insn |= bfd_getl16 (buffer);
|
||||
extension = 0;
|
||||
}
|
||||
else if (size == 5 && op->opcode == 0xdc000000)
|
||||
{
|
||||
unsigned long temp = 0;
|
||||
status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return;
|
||||
}
|
||||
temp |= bfd_getl32 (buffer);
|
||||
|
||||
insn &= 0xff000000;
|
||||
insn |= (temp & 0xffffff00) >> 8;
|
||||
extension = temp & 0xff;
|
||||
}
|
||||
else if (size == 5)
|
||||
{
|
||||
unsigned long temp = 0;
|
||||
status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return;
|
||||
}
|
||||
temp |= bfd_getl16 (buffer);
|
||||
|
||||
insn &= 0xff0000ff;
|
||||
insn |= temp << 8;
|
||||
|
||||
status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return;
|
||||
}
|
||||
extension = *(unsigned char *)buffer;
|
||||
}
|
||||
else if (size == 6)
|
||||
{
|
||||
unsigned long temp = 0;
|
||||
status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return;
|
||||
}
|
||||
temp |= bfd_getl32 (buffer);
|
||||
|
||||
insn &= 0xffff0000;
|
||||
insn |= (temp >> 16) & 0xffff;
|
||||
extension = temp & 0xffff;
|
||||
}
|
||||
else if (size == 7 && op->opcode == 0xdd000000)
|
||||
{
|
||||
unsigned long temp = 0;
|
||||
status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return;
|
||||
}
|
||||
temp |= bfd_getl32 (buffer);
|
||||
|
||||
insn &= 0xff000000;
|
||||
insn |= (temp >> 8) & 0xffffff;
|
||||
extension = (temp & 0xff) << 16;
|
||||
|
||||
status = (*info->read_memory_func) (memaddr + 5, buffer, 2, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return;
|
||||
}
|
||||
extension |= bfd_getb16 (buffer);
|
||||
}
|
||||
else if (size == 7)
|
||||
{
|
||||
unsigned long temp = 0;
|
||||
status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return;
|
||||
}
|
||||
temp |= bfd_getl32 (buffer);
|
||||
|
||||
insn &= 0xffff0000;
|
||||
insn |= (temp >> 16) & 0xffff;
|
||||
extension = (temp & 0xffff) << 8;
|
||||
|
||||
status = (*info->read_memory_func) (memaddr + 6, buffer, 1, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return;
|
||||
}
|
||||
extension |= *(unsigned char *)buffer;
|
||||
}
|
||||
|
||||
match = 1;
|
||||
(*info->fprintf_func) (info->stream, "%s\t", op->name);
|
||||
|
||||
/* Now print the operands. */
|
||||
for (opindex_ptr = op->operands, nocomma = 1;
|
||||
*opindex_ptr != 0;
|
||||
opindex_ptr++)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
operand = &mn10300_operands[*opindex_ptr];
|
||||
|
||||
if ((operand->flags & MN10300_OPERAND_SPLIT) != 0)
|
||||
{
|
||||
unsigned long temp;
|
||||
value = insn & ((1 << operand->bits) - 1);
|
||||
value <<= (32 - operand->bits);
|
||||
temp = extension >> operand->shift;
|
||||
temp &= ((1 << (32 - operand->bits)) - 1);
|
||||
value |= temp;
|
||||
}
|
||||
else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0)
|
||||
{
|
||||
value = ((extension >> (operand->shift))
|
||||
& ((1 << operand->bits) - 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
value = ((insn >> (operand->shift))
|
||||
& ((1 << operand->bits) - 1));
|
||||
}
|
||||
|
||||
if ((operand->flags & MN10300_OPERAND_SIGNED) != 0)
|
||||
value = ((long)(value << (32 - operand->bits))
|
||||
>> (32 - operand->bits));
|
||||
|
||||
if (!nocomma
|
||||
&& (!paren
|
||||
|| ((operand->flags & MN10300_OPERAND_PAREN) == 0)))
|
||||
(*info->fprintf_func) (info->stream, ",");
|
||||
|
||||
nocomma = 0;
|
||||
|
||||
if ((operand->flags & MN10300_OPERAND_DREG) != 0)
|
||||
{
|
||||
value = ((insn >> (operand->shift + extra_shift))
|
||||
& ((1 << operand->bits) - 1));
|
||||
(*info->fprintf_func) (info->stream, "d%d", value);
|
||||
}
|
||||
|
||||
else if ((operand->flags & MN10300_OPERAND_AREG) != 0)
|
||||
{
|
||||
value = ((insn >> (operand->shift + extra_shift))
|
||||
& ((1 << operand->bits) - 1));
|
||||
(*info->fprintf_func) (info->stream, "a%d", value);
|
||||
}
|
||||
|
||||
else if ((operand->flags & MN10300_OPERAND_SP) != 0)
|
||||
(*info->fprintf_func) (info->stream, "sp");
|
||||
|
||||
else if ((operand->flags & MN10300_OPERAND_PSW) != 0)
|
||||
(*info->fprintf_func) (info->stream, "psw");
|
||||
|
||||
else if ((operand->flags & MN10300_OPERAND_MDR) != 0)
|
||||
(*info->fprintf_func) (info->stream, "mdr");
|
||||
|
||||
else if ((operand->flags & MN10300_OPERAND_PAREN) != 0)
|
||||
{
|
||||
if (paren)
|
||||
(*info->fprintf_func) (info->stream, ")");
|
||||
else
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "(");
|
||||
nocomma = 1;
|
||||
}
|
||||
paren = !paren;
|
||||
}
|
||||
|
||||
else if ((operand->flags & MN10300_OPERAND_PCREL) != 0)
|
||||
(*info->print_address_func) (value + memaddr, info);
|
||||
|
||||
else if ((operand->flags & MN10300_OPERAND_MEMADDR) != 0)
|
||||
(*info->print_address_func) (value, info);
|
||||
|
||||
else if ((operand->flags & MN10300_OPERAND_REG_LIST) != 0)
|
||||
{
|
||||
int comma = 0;
|
||||
|
||||
(*info->fprintf_func) (info->stream, "[");
|
||||
if (value & 0x80)
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "d2");
|
||||
comma = 1;
|
||||
}
|
||||
|
||||
if (value & 0x40)
|
||||
{
|
||||
if (comma)
|
||||
(*info->fprintf_func) (info->stream, ",");
|
||||
(*info->fprintf_func) (info->stream, "d3");
|
||||
comma = 1;
|
||||
}
|
||||
|
||||
if (value & 0x20)
|
||||
{
|
||||
if (comma)
|
||||
(*info->fprintf_func) (info->stream, ",");
|
||||
(*info->fprintf_func) (info->stream, "a2");
|
||||
comma = 1;
|
||||
}
|
||||
|
||||
if (value & 0x10)
|
||||
{
|
||||
if (comma)
|
||||
(*info->fprintf_func) (info->stream, ",");
|
||||
(*info->fprintf_func) (info->stream, "a3");
|
||||
comma = 1;
|
||||
}
|
||||
|
||||
if (value & 0x08)
|
||||
{
|
||||
if (comma)
|
||||
(*info->fprintf_func) (info->stream, ",");
|
||||
(*info->fprintf_func) (info->stream, "other");
|
||||
comma = 1;
|
||||
}
|
||||
(*info->fprintf_func) (info->stream, "]");
|
||||
}
|
||||
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%d", value);
|
||||
}
|
||||
/* All done. */
|
||||
break;
|
||||
}
|
||||
op++;
|
||||
}
|
||||
|
||||
if (!match)
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "unknown\t0x%04x", insn);
|
||||
}
|
||||
}
|
||||
|
|
@ -1,514 +0,0 @@
|
|||
/* Assemble Matsushita MN10300 instructions.
|
||||
Copyright (C) 1996, 1997 Free Software Foundation, Inc.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#include "ansidecl.h"
|
||||
#include "opcode/mn10300.h"
|
||||
|
||||
|
||||
const struct mn10300_operand mn10300_operands[] = {
|
||||
#define UNUSED 0
|
||||
{0, 0, 0},
|
||||
|
||||
/* dn register in the first register operand position. */
|
||||
#define DN0 (UNUSED+1)
|
||||
{2, 0, MN10300_OPERAND_DREG},
|
||||
|
||||
/* dn register in the second register operand position. */
|
||||
#define DN1 (DN0+1)
|
||||
{2, 2, MN10300_OPERAND_DREG},
|
||||
|
||||
/* dn register in the third register operand position. */
|
||||
#define DN2 (DN1+1)
|
||||
{2, 4, MN10300_OPERAND_DREG},
|
||||
|
||||
/* dm register in the first register operand position. */
|
||||
#define DM0 (DN2+1)
|
||||
{2, 0, MN10300_OPERAND_DREG},
|
||||
|
||||
/* dm register in the second register operand position. */
|
||||
#define DM1 (DM0+1)
|
||||
{2, 2, MN10300_OPERAND_DREG},
|
||||
|
||||
/* dm register in the third register operand position. */
|
||||
#define DM2 (DM1+1)
|
||||
{2, 4, MN10300_OPERAND_DREG},
|
||||
|
||||
/* an register in the first register operand position. */
|
||||
#define AN0 (DM2+1)
|
||||
{2, 0, MN10300_OPERAND_AREG},
|
||||
|
||||
/* an register in the second register operand position. */
|
||||
#define AN1 (AN0+1)
|
||||
{2, 2, MN10300_OPERAND_AREG},
|
||||
|
||||
/* an register in the third register operand position. */
|
||||
#define AN2 (AN1+1)
|
||||
{2, 4, MN10300_OPERAND_AREG},
|
||||
|
||||
/* am register in the first register operand position. */
|
||||
#define AM0 (AN2+1)
|
||||
{2, 0, MN10300_OPERAND_AREG},
|
||||
|
||||
/* am register in the second register operand position. */
|
||||
#define AM1 (AM0+1)
|
||||
{2, 2, MN10300_OPERAND_AREG},
|
||||
|
||||
/* am register in the third register operand position. */
|
||||
#define AM2 (AM1+1)
|
||||
{2, 4, MN10300_OPERAND_AREG},
|
||||
|
||||
/* 8 bit unsigned immediate which may promote to a 16bit
|
||||
unsigned immediate. */
|
||||
#define IMM8 (AM2+1)
|
||||
{8, 0, MN10300_OPERAND_PROMOTE},
|
||||
|
||||
/* 16 bit unsigned immediate which may promote to a 32bit
|
||||
unsigned immediate. */
|
||||
#define IMM16 (IMM8+1)
|
||||
{16, 0, MN10300_OPERAND_PROMOTE},
|
||||
|
||||
/* 16 bit pc-relative immediate which may promote to a 16bit
|
||||
pc-relative immediate. */
|
||||
#define IMM16_PCREL (IMM16+1)
|
||||
{16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
|
||||
|
||||
/* 16bit unsigned dispacement in a memory operation which
|
||||
may promote to a 32bit displacement. */
|
||||
#define IMM16_MEM (IMM16_PCREL+1)
|
||||
{16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
|
||||
|
||||
/* 32bit immediate, high 16 bits in the main instruction
|
||||
word, 16bits in the extension word.
|
||||
|
||||
The "bits" field indicates how many bits are in the
|
||||
main instruction word for MN10300_OPERAND_SPLIT! */
|
||||
#define IMM32 (IMM16_MEM+1)
|
||||
{16, 0, MN10300_OPERAND_SPLIT},
|
||||
|
||||
/* 32bit pc-relative offset. */
|
||||
#define IMM32_PCREL (IMM32+1)
|
||||
{16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
|
||||
|
||||
/* 32bit memory offset. */
|
||||
#define IMM32_MEM (IMM32_PCREL+1)
|
||||
{16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
|
||||
|
||||
/* 32bit immediate, high 16 bits in the main instruction
|
||||
word, 16bits in the extension word, low 16bits are left
|
||||
shifted 8 places.
|
||||
|
||||
The "bits" field indicates how many bits are in the
|
||||
main instruction word for MN10300_OPERAND_SPLIT! */
|
||||
#define IMM32_LOWSHIFT8 (IMM32_MEM+1)
|
||||
{16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
|
||||
|
||||
/* 32bit immediate, high 24 bits in the main instruction
|
||||
word, 8 in the extension word.
|
||||
|
||||
The "bits" field indicates how many bits are in the
|
||||
main instruction word for MN10300_OPERAND_SPLIT! */
|
||||
#define IMM32_HIGH24 (IMM32_LOWSHIFT8+1)
|
||||
{24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
|
||||
|
||||
/* 32bit immediate, high 24 bits in the main instruction
|
||||
word, 8 in the extension word, low 8 bits are left
|
||||
shifted 16 places.
|
||||
|
||||
The "bits" field indicates how many bits are in the
|
||||
main instruction word for MN10300_OPERAND_SPLIT! */
|
||||
#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
|
||||
{24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
|
||||
|
||||
/* Stack pointer. */
|
||||
#define SP (IMM32_HIGH24_LOWSHIFT16+1)
|
||||
{8, 0, MN10300_OPERAND_SP},
|
||||
|
||||
/* Processor status word. */
|
||||
#define PSW (SP+1)
|
||||
{0, 0, MN10300_OPERAND_PSW},
|
||||
|
||||
/* MDR register. */
|
||||
#define MDR (PSW+1)
|
||||
{0, 0, MN10300_OPERAND_MDR},
|
||||
|
||||
/* Index register. */
|
||||
#define DI (MDR+1)
|
||||
{2, 2, MN10300_OPERAND_DREG},
|
||||
|
||||
/* 8 bit signed displacement, may promote to 16bit signed dispacement. */
|
||||
#define SD8 (DI+1)
|
||||
{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
|
||||
|
||||
/* 16 bit signed displacement, may promote to 32bit dispacement. */
|
||||
#define SD16 (SD8+1)
|
||||
{16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
|
||||
|
||||
/* 8 bit signed displacement that can not promote. */
|
||||
#define SD8N (SD16+1)
|
||||
{8, 0, MN10300_OPERAND_SIGNED},
|
||||
|
||||
/* 8 bit pc-relative displacement. */
|
||||
#define SD8N_PCREL (SD8N+1)
|
||||
{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
|
||||
|
||||
/* 8 bit signed displacement shifted left 8 bits in the instruction. */
|
||||
#define SD8N_SHIFT8 (SD8N_PCREL+1)
|
||||
{8, 8, MN10300_OPERAND_SIGNED},
|
||||
|
||||
/* 8 bit signed immediate which may promote to 16bit signed immediate. */
|
||||
#define SIMM8 (SD8N_SHIFT8+1)
|
||||
{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
|
||||
|
||||
/* 16 bit signed immediate which may promote to 32bit immediate. */
|
||||
#define SIMM16 (SIMM8+1)
|
||||
{16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
|
||||
|
||||
/* Either an open paren or close paren. */
|
||||
#define PAREN (SIMM16+1)
|
||||
{0, 0, MN10300_OPERAND_PAREN},
|
||||
|
||||
/* dn register that appears in the first and second register positions. */
|
||||
#define DN01 (PAREN+1)
|
||||
{2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
|
||||
|
||||
/* an register that appears in the first and second register positions. */
|
||||
#define AN01 (DN01+1)
|
||||
{2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
|
||||
|
||||
/* 16bit pc-relative displacement which may promote to 32bit pc-relative
|
||||
displacement. */
|
||||
#define D16_SHIFT (AN01+1)
|
||||
{16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
|
||||
|
||||
/* 8 bit immediate found in the extension word. */
|
||||
#define IMM8E (D16_SHIFT+1)
|
||||
{8, 0, MN10300_OPERAND_EXTENDED},
|
||||
|
||||
/* Register list found in the extension word shifted 8 bits left. */
|
||||
#define REGSE_SHIFT8 (IMM8E+1)
|
||||
{8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
|
||||
|
||||
/* Register list shifted 8 bits left. */
|
||||
#define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
|
||||
{8, 8, MN10300_OPERAND_REG_LIST},
|
||||
|
||||
/* Reigster list. */
|
||||
#define REGS (REGS_SHIFT8+1)
|
||||
{8, 0, MN10300_OPERAND_REG_LIST},
|
||||
} ;
|
||||
|
||||
#define MEM(ADDR) PAREN, ADDR, PAREN
|
||||
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
|
||||
|
||||
/* The opcode table.
|
||||
|
||||
The format of the opcode table is:
|
||||
|
||||
NAME OPCODE MASK { OPERANDS }
|
||||
|
||||
NAME is the name of the instruction.
|
||||
OPCODE is the instruction opcode.
|
||||
MASK is the opcode mask; this is used to tell the disassembler
|
||||
which bits in the actual opcode must match OPCODE.
|
||||
OPERANDS is the list of operands.
|
||||
|
||||
The disassembler reads the table in order and prints the first
|
||||
instruction which matches, so this table is sorted to put more
|
||||
specific instructions before more general instructions. It is also
|
||||
sorted by major opcode. */
|
||||
|
||||
const struct mn10300_opcode mn10300_opcodes[] = {
|
||||
{ "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN01}},
|
||||
{ "mov", 0x80, 0xf0, FMT_S0, {DM1, DN0}},
|
||||
{ "mov", 0xf1e0, 0xfff0, FMT_D0, {DM1, AN0}},
|
||||
{ "mov", 0xf1d0, 0xfff0, FMT_D0, {AM1, DN0}},
|
||||
{ "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN01}},
|
||||
{ "mov", 0x90, 0xf0, FMT_S0, {AM1, AN0}},
|
||||
{ "mov", 0x3c, 0xfc, FMT_S0, {SP, AN0}},
|
||||
{ "mov", 0xf2f0, 0xfff3, FMT_D0, {AM1, SP}},
|
||||
{ "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN0}},
|
||||
{ "mov", 0xf2f3, 0xfff3, FMT_D0, {DM1, PSW}},
|
||||
{ "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN0}},
|
||||
{ "mov", 0xf2f2, 0xfff3, FMT_D0, {DM1, MDR}},
|
||||
{ "mov", 0x70, 0xf0, FMT_S0, {MEM(AM0), DN1}},
|
||||
{ "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
|
||||
{ "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
|
||||
{ "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
|
||||
{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(IMM8, SP), DN0}},
|
||||
{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
|
||||
{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
|
||||
{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
|
||||
{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
|
||||
{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
|
||||
{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM0), AN1}},
|
||||
{ "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(SD8,AM0), AN1}},
|
||||
{ "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), AN1}},
|
||||
{ "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), AN1}},
|
||||
{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(IMM8, SP), AN0}},
|
||||
{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), AN0}},
|
||||
{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), AN0}},
|
||||
{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN2}},
|
||||
{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(IMM16_MEM), AN0}},
|
||||
{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), AN0}},
|
||||
{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM0), SP}},
|
||||
{ "mov", 0x60, 0xf0, FMT_S0, {DM1, MEM(AN0)}},
|
||||
{ "mov", 0xf81000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
|
||||
{ "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
|
||||
{ "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
|
||||
{ "mov", 0x4200, 0xf300, FMT_S1, {DM1, MEM2(IMM8, SP)}},
|
||||
{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
|
||||
{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
|
||||
{ "mov", 0xf340, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
|
||||
{ "mov", 0x010000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
|
||||
{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
|
||||
{ "mov", 0xf010, 0xfff0, FMT_D0, {AM1, MEM(AN0)}},
|
||||
{ "mov", 0xf83000, 0xfff000, FMT_D1, {AM1, MEM2(SD8, AN0)}},
|
||||
{ "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM1, MEM2(SD16, AN0)}},
|
||||
{ "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM1, MEM2(IMM32,AN0)}},
|
||||
{ "mov", 0x4300, 0xf300, FMT_S1, {AM1, MEM2(IMM8, SP)}},
|
||||
{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM1, MEM2(IMM16, SP)}},
|
||||
{ "mov", 0xfc900000, 0xfff30000, FMT_D4, {AM1, MEM2(IMM32, SP)}},
|
||||
{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM2, MEM2(DI, AN0)}},
|
||||
{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM1, MEM(IMM16_MEM)}},
|
||||
{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM1, MEM(IMM32_MEM)}},
|
||||
{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN0)}},
|
||||
{ "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN0}},
|
||||
{ "mov", 0xfccc0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
|
||||
{ "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN0}},
|
||||
{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
|
||||
|
||||
{ "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
|
||||
{ "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
|
||||
{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
|
||||
{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
|
||||
{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
|
||||
{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
|
||||
{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
|
||||
{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
|
||||
{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
|
||||
{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
|
||||
{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
|
||||
{ "movbu", 0xf85000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
|
||||
{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
|
||||
{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
|
||||
{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
|
||||
{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
|
||||
{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
|
||||
{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
|
||||
{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
|
||||
{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
|
||||
|
||||
{ "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
|
||||
{ "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
|
||||
{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
|
||||
{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
|
||||
{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
|
||||
{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
|
||||
{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
|
||||
{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
|
||||
{ "movhu", 0x380000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
|
||||
{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
|
||||
{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
|
||||
{ "movhu", 0xf87000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
|
||||
{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
|
||||
{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
|
||||
{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
|
||||
{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
|
||||
{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
|
||||
{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
|
||||
{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
|
||||
{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
|
||||
|
||||
{ "ext", 0xf2d0, 0xfffc, FMT_D0, {DN0}},
|
||||
{ "extb", 0x10, 0xfc, FMT_S0, {DN0}},
|
||||
{ "extbu", 0x14, 0xfc, FMT_S0, {DN0}},
|
||||
{ "exth", 0x18, 0xfc, FMT_S0, {DN0}},
|
||||
{ "exthu", 0x1c, 0xfc, FMT_S0, {DN0}},
|
||||
|
||||
{ "movm", 0xce00, 0xff00, FMT_S1, {MEM(SP), REGS}},
|
||||
{ "movm", 0xcf00, 0xff00, FMT_S1, {REGS, MEM(SP)}},
|
||||
|
||||
{ "clr", 0x00, 0xf3, FMT_S0, {DN1}},
|
||||
|
||||
{ "add", 0xe0, 0xf0, FMT_S0, {DM1, DN0}},
|
||||
{ "add", 0xf160, 0xfff0, FMT_D0, {DM1, AN0}},
|
||||
{ "add", 0xf150, 0xfff0, FMT_D0, {AM1, DN0}},
|
||||
{ "add", 0xf170, 0xfff0, FMT_D0, {AM1, AN0}},
|
||||
{ "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN0}},
|
||||
{ "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
|
||||
{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
|
||||
{ "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN0}},
|
||||
{ "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN0}},
|
||||
{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
|
||||
{ "add", 0xf8fe00, 0xffff00, FMT_D1, {SIMM8, SP}},
|
||||
{ "add", 0xfafe0000, 0xffff0000, FMT_D2, {SIMM16, SP}},
|
||||
{ "add", 0xfcfe0000, 0xffff0000, FMT_D4, {IMM32, SP}},
|
||||
{ "addc", 0xf140, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
|
||||
{ "sub", 0xf100, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "sub", 0xf120, 0xfff0, FMT_D0, {DM1, AN0}},
|
||||
{ "sub", 0xf110, 0xfff0, FMT_D0, {AM1, DN0}},
|
||||
{ "sub", 0xf130, 0xfff0, FMT_D0, {AM1, AN0}},
|
||||
{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
|
||||
{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
|
||||
{ "subc", 0xf180, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
|
||||
{ "mul", 0xf240, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "mulu", 0xf250, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
|
||||
{ "div", 0xf260, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "divu", 0xf270, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
|
||||
{ "inc", 0x40, 0xf3, FMT_S0, {DN1}},
|
||||
{ "inc", 0x41, 0xf3, FMT_S0, {AN1}},
|
||||
{ "inc4", 0x50, 0xfc, FMT_S0, {AN0}},
|
||||
|
||||
{ "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN01}},
|
||||
{ "cmp", 0xa0, 0xf0, FMT_S0, {DM1, DN0}},
|
||||
{ "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM1, AN0}},
|
||||
{ "cmp", 0xf190, 0xfff0, FMT_D0, {AM1, DN0}},
|
||||
{ "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN01}},
|
||||
{ "cmp", 0xb0, 0xf0, FMT_S0, {AM1, AN0}},
|
||||
{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
|
||||
{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
|
||||
{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN0}},
|
||||
{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
|
||||
|
||||
{ "and", 0xf200, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN0}},
|
||||
{ "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
|
||||
{ "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
|
||||
{ "and", 0xfafc0000, 0xffff0000, FMT_D2, {IMM16, PSW}},
|
||||
{ "or", 0xf210, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN0}},
|
||||
{ "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
|
||||
{ "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
|
||||
{ "or", 0xfafd0000, 0xffff0000, FMT_D2, {IMM16, PSW}},
|
||||
{ "xor", 0xf220, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
|
||||
{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
|
||||
{ "not", 0xf230, 0xfffc, FMT_D0, {DN0}},
|
||||
|
||||
{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}},
|
||||
{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
|
||||
{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
|
||||
{ "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8E,
|
||||
MEM(IMM32_LOWSHIFT8)}},
|
||||
{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2,
|
||||
{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
|
||||
{ "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
|
||||
{ "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8E,
|
||||
MEM(IMM32_LOWSHIFT8)}},
|
||||
{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2,
|
||||
{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
|
||||
{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
|
||||
{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8E,
|
||||
MEM(IMM32_LOWSHIFT8)}},
|
||||
{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8,
|
||||
MEM2(SD8N_SHIFT8,AN0)}},
|
||||
|
||||
{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}},
|
||||
{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}},
|
||||
{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}},
|
||||
{ "asl2", 0x54, 0xfc, FMT_S0, {DN0}},
|
||||
{ "ror", 0xf284, 0xfffc, FMT_D0, {DN0}},
|
||||
{ "rol", 0xf280, 0xfffc, FMT_D0, {DN0}},
|
||||
|
||||
{ "beq", 0xc800, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
{ "bne", 0xc900, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
{ "bgt", 0xc100, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
{ "bge", 0xc200, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
{ "ble", 0xc300, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
{ "blt", 0xc000, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
{ "bhi", 0xc500, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
{ "bcc", 0xc600, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
{ "bls", 0xc700, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
{ "bcs", 0xc400, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
{ "bvc", 0xf8e800, 0xffff00, FMT_D1, {SD8N_PCREL}},
|
||||
{ "bvs", 0xf8e900, 0xffff00, FMT_D1, {SD8N_PCREL}},
|
||||
{ "bnc", 0xf8ea00, 0xffff00, FMT_D1, {SD8N_PCREL}},
|
||||
{ "bns", 0xf8eb00, 0xffff00, FMT_D1, {SD8N_PCREL}},
|
||||
{ "bra", 0xca00, 0xff00, FMT_S1, {SD8N_PCREL}},
|
||||
|
||||
{ "leq", 0xd8, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "lne", 0xd9, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "lgt", 0xd1, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "lge", 0xd2, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "lle", 0xd3, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "llt", 0xd0, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "lhi", 0xd5, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "lls", 0xd7, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "lcs", 0xd4, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "lra", 0xda, 0xff, FMT_S0, {UNUSED}},
|
||||
{ "setlb", 0xdb, 0xff, FMT_S0, {UNUSED}},
|
||||
|
||||
{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}},
|
||||
{ "jmp", 0xcc0000, 0xff0000, FMT_S2, {IMM16_PCREL}},
|
||||
{ "jmp", 0xdc000000, 0xff000000, FMT_S4, {IMM32_HIGH24}},
|
||||
{ "call", 0xcd000000, 0xff000000, FMT_S4, {D16_SHIFT,REGS,IMM8E}},
|
||||
{ "call", 0xdd000000, 0xff000000, FMT_S6,
|
||||
{IMM32_HIGH24_LOWSHIFT16,REGSE_SHIFT8,IMM8E}},
|
||||
{ "calls", 0xf0f0, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}},
|
||||
{ "calls", 0xfaff0000, 0xffff0000, FMT_D2, {IMM16_PCREL}},
|
||||
{ "calls", 0xfcff0000, 0xffff0000, FMT_D4, {IMM32_PCREL}},
|
||||
|
||||
{ "ret", 0xdf0000, 0xff0000, FMT_S2, {REGS_SHIFT8, IMM8}},
|
||||
{ "retf", 0xde0000, 0xff0000, FMT_S2, {REGS_SHIFT8, IMM8}},
|
||||
{ "rets", 0xf0fc, 0xffff, FMT_D0, {UNUSED}},
|
||||
{ "rti", 0xf0fd, 0xffff, FMT_D0, {UNUSED}},
|
||||
{ "trap", 0xf0fe, 0xffff, FMT_D0, {UNUSED}},
|
||||
{ "rtm", 0xf0ff, 0xffff, FMT_D0, {UNUSED}},
|
||||
{ "nop", 0xcb, 0xff, FMT_S0, {UNUSED}},
|
||||
/* { "udf", 0, 0, {0}}, */
|
||||
|
||||
{ "putx", 0xf500, 0xfff0, FMT_D0, {DN01}},
|
||||
{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN01}},
|
||||
{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN0}},
|
||||
{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
|
||||
{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
|
||||
{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "mulqu", 0xf91400, 0xfffc00, FMT_D1, {SIMM8, DN0}},
|
||||
{ "mulqu", 0xfb140000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
|
||||
{ "mulqu", 0xfd140000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
|
||||
{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM1, DN0}},
|
||||
|
||||
/* Extension. We need some instruction to trigger "emulated syscalls"
|
||||
for our simulator. */
|
||||
{ "syscall", 0xf020, 0xffff, FMT_D0, {UNUSED}},
|
||||
|
||||
/* Extension. When talking to the simulator, gdb requires some instruction
|
||||
that will trigger a "breakpoint" (really just an instruction that isn't
|
||||
otherwise used by the tools. This instruction must be the same size
|
||||
as the smallest instruction on the target machine. In the case of the
|
||||
mn10x00 the "break" instruction must be one byte. 0xff is available on
|
||||
both mn10x00 architectures. */
|
||||
{ "break", 0xff, 0xff, FMT_S0, {UNUSED}},
|
||||
{ 0, 0, 0, 0, {0}},
|
||||
|
||||
} ;
|
||||
|
||||
const int mn10300_num_opcodes =
|
||||
sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
|
||||
|
||||
|
||||
Loading…
Reference in a new issue