* ppc-opc.c (powerpc_operands): Make comment match the
actual fields (no shift field). * sparc-opc.c (sparc_opcodes): Document why this cannot be "const". * tic80-dis.c (print_insn_tic80): Replace abort stub with a partial implementation, work in progress. * tic80-opc.c (tic80_operands): Begin construction operands table. (tic80_opcodes): Continue populating opcodes table and start filling in the operand indices. (tic80_num_opcodes): Add this.
This commit is contained in:
Fred Fish
parent
28eb95aa33
commit
872dc6f0bc
3 changed files with 422 additions and 1 deletions
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@ -1,3 +1,17 @@
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Fri Jan 3 18:32:11 1997 Fred Fish <fnf@cygnus.com>
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* ppc-opc.c (powerpc_operands): Make comment match the
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actual fields (no shift field).
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* sparc-opc.c (sparc_opcodes): Document why this cannot be "const".
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start-sanitize-tic80
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* tic80-dis.c (print_insn_tic80): Replace abort stub with a
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partial implementation, work in progress.
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* tic80-opc.c (tic80_operands): Begin construction operands table.
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(tic80_opcodes): Continue populating opcodes table and start
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filling in the operand indices.
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(tic80_num_opcodes): Add this.
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end-sanitize-tic80
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Fri Jan 3 12:13:52 1997 Ian Lance Taylor <ian@cygnus.com>
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* m68k-opc.c: Add #B case for moveq.
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@ -26,5 +26,180 @@ print_insn_tic80 (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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abort ();
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bfd_byte buffer[4];
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int status;
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unsigned long insn[2];
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const struct tic80_opcode *opcode;
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const struct tic80_opcode *opcode_end;
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const unsigned char *opindex;
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const struct tic80_operand *operand;
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int need_comma;
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int need_paren;
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int length = 4;
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status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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if (info -> endian == BFD_ENDIAN_LITTLE)
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{
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insn[0] = bfd_getl32 (buffer);
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}
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else if (info -> endian == BFD_ENDIAN_BIG)
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{
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insn[0] = bfd_getb32 (buffer);
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}
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else
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{
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/* FIXME: Should probably just default to one or the other */
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abort ();
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}
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/* Find the first opcode match in the opcodes table. FIXME: there should
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be faster ways to find one (hash table or binary search), but don't
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worry too much about it until other TIc80 support is finished. */
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opcode_end = tic80_opcodes + tic80_num_opcodes;
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for (opcode = tic80_opcodes; opcode < opcode_end; opcode++)
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{
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if ((insn[0] & opcode -> mask) == opcode -> opcode)
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{
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break;
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}
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}
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if (opcode == opcode_end)
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{
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/* No match found, just print the bits as a .word directive */
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(*info -> fprintf_func) (info -> stream, ".word %#08lx", insn[0]);
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}
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else
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{
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/* Match found, decode the instruction. */
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(*info -> fprintf_func) (info -> stream, "%s", opcode -> name);
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/* Now extract and print the operands. */
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need_comma = 0;
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need_paren = 0;
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if (opcode -> operands[0] != 0)
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{
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(*info -> fprintf_func) (info -> stream, "\t");
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}
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for (opindex = opcode -> operands; *opindex != 0; opindex++)
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{
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long value;
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operand = tic80_operands + *opindex;
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/* Extract the value from the instruction. */
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if (operand -> extract)
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{
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value = (*operand -> extract) (insn[0], (int *) NULL);
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}
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else if (operand -> bits == 32)
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{
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status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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if (info -> endian == BFD_ENDIAN_LITTLE)
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{
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insn[1] = bfd_getl32 (buffer);
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}
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else if (info -> endian == BFD_ENDIAN_BIG)
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{
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insn[1] = bfd_getb32 (buffer);
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}
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value = (long) insn[1];
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length += 4;
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}
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else
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{
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value = (insn[0] >> operand -> shift) & ((1 << operand -> bits) - 1);
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if ((operand -> flags & TIC80_OPERAND_SIGNED) != 0
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&& (value & (1 << (operand -> bits - 1))) != 0)
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value -= 1 << operand -> bits;
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}
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if (need_comma)
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{
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(*info -> fprintf_func) (info -> stream, ",");
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need_comma = 0;
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}
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/* Print the operand as directed by the flags. */
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if ((operand -> flags & TIC80_OPERAND_GPR) != 0)
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{
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(*info -> fprintf_func) (info -> stream, "r%ld", value);
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}
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else if ((operand -> flags & TIC80_OPERAND_FPA) != 0)
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{
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(*info -> fprintf_func) (info -> stream, "a%ld", value);
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}
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else if ((operand -> flags & TIC80_OPERAND_RELATIVE) != 0)
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{
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(*info -> print_address_func) (memaddr + value, info);
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}
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else if ((operand -> flags & TIC80_OPERAND_CC_SZ) != 0)
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{
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#if 0 /* FIXME */
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if (operand -> bits == 3)
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(*info -> fprintf_func) (info -> stream, "cr%d", value);
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else
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{
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static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
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int cr;
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int cc;
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cr = value >> 2;
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if (cr != 0)
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(*info -> fprintf_func) (info -> stream, "4*cr%d", cr);
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cc = value & 3;
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if (cc != 0)
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{
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if (cr != 0)
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(*info -> fprintf_func) (info -> stream, "+");
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(*info -> fprintf_func) (info -> stream, "%s", cbnames[cc]);
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}
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}
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#endif
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}
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else
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{
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if ((value > 999 || value < -999)
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|| operand -> flags & TIC80_OPERAND_BITFIELD)
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{
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(*info -> fprintf_func) (info -> stream, "%#lx", value);
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}
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else
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{
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(*info -> fprintf_func) (info -> stream, "%ld", value);
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}
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}
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if (need_paren)
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{
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(*info -> fprintf_func) (info -> stream, ")");
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need_paren = 0;
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}
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if ((operand -> flags & TIC80_OPERAND_PARENS) == 0)
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{
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need_comma = 1;
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}
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else
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{
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(*info -> fprintf_func) (info -> stream, "(");
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need_paren = 1;
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}
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}
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}
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return (length);
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}
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@ -17,5 +17,237 @@ You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "ansidecl.h"
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#include "opcode/tic80.h"
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/* This file holds the TMS320C80 (MVP) opcode table. The table is
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strictly constant data, so the compiler should be able to put it in
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the .text section.
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This file also holds the operand table. All knowledge about
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inserting operands into instructions and vice-versa is kept in this
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file. */
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/* The operands table. The fields are:
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bits, shift, insertion function, extraction function, flags
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*/
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const struct tic80_operand tic80_operands[] =
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{
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/* The zero index is used to indicate the end of the list of operands. */
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#define UNUSED (0)
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{ 0, 0, 0, 0, 0 },
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/* Short signed immediate value in bits 14-0. */
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#define SSI (UNUSED + 1)
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{ 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
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/* Short unsigned immediate value in bits 14-0 */
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#define SUI (SSI + 1)
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{ 15, 0, NULL, NULL, 0 },
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/* Short unsigned bitfield in bits 14-0. We distinguish this
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from a regular unsigned immediate value only for the convenience
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of the disassembler and the user. */
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#define SUBF (SUI + 1)
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{ 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
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/* Long signed immediate in following 32 bit word */
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#define LSI (SUBF + 1)
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{ 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
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/* Long unsigned immediate in following 32 bit word */
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#define LUI (LSI + 1)
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{ 32, 0, NULL, NULL, 0 },
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/* Long unsigned bitfield in following 32 bit word. We distinguish
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this from a regular unsigned immediate value only for the
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convenience of the disassembler and the user. */
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#define LUBF (LUI + 1)
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{ 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
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/* Register in bits 4-0 */
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#define REG0 (LUBF + 1)
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{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
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/* Register in bits 26-22 */
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#define REG22 (REG0 + 1)
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{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
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/* Register in bits 31-27 */
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#define REG27 (REG22 + 1)
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{ 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
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};
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const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
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/* Macros used to generate entries for the opcodes table. */
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#define FIXME 0
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/* Short-Immediate Format Instructions */
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#define OP_SI(x) (((x) & 0x7F) << 15)
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#define MASK_SI OP_SI(0x7F)
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#define MASK_SI_M OP_SI(0x7B) /* Short-Immediate with embedded M bit */
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/* Long-Immediate Format Instructions */
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#define OP_LI(x) (((x) & 0x3FF) << 12)
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#define MASK_LI OP_LI(0x3FF)
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#define MASK_LI_M OP_LI(0x3F7) /* Long-Immediate with embedded M bit */
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/* Register Format Instructions */
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#define OP_REG(x) OP_LI(x) /* For readability */
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#define MASK_REG MASK_LI /* For readability */
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#define MASK_REG_M MASK_LI_M /* For readability */
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const struct tic80_opcode tic80_opcodes[] = {
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/* Signed integer ADD */
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{"add", OP_SI(0x58), MASK_SI, FMT_SI, {SSI, REG22, REG27} },
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{"add", OP_LI(0x3B1), MASK_LI, FMT_LI, {LSI, REG22, REG27} },
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{"add", OP_REG(0x3B0), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
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/* Unsigned integer ADD */
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{"addu", OP_SI(0x59), MASK_SI, FMT_SI, {SSI, REG22, REG27} },
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{"addu", OP_LI(0x3B3), MASK_LI, FMT_LI, {LSI, REG22, REG27} },
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{"addu", OP_REG(0x3B2), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
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/* Bitwise AND */
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{"and", OP_SI(0x11), MASK_SI, FMT_SI, {SUBF, REG22, REG27} },
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{"and", OP_LI(0x323), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
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{"and", OP_REG(0x322), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
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{"and.tt", OP_SI(0x11), MASK_SI, FMT_SI, {SUBF, REG22, REG27} },
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{"and.tt", OP_LI(0x323), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
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{"and.tt", OP_REG(0x322), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
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/* Bitwise AND with ones complement of both sources */
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{"and.ff", OP_SI(0x18), MASK_SI, FMT_SI, {SUBF, REG22, REG27} },
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{"and.ff", OP_LI(0x331), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
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{"and.ff", OP_REG(0x330), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
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/* Bitwise AND with ones complement of source 1 */
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{"and.ft", OP_SI(0x14), MASK_SI, FMT_SI, {SUBF, REG22, REG27} },
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{"and.ft", OP_LI(0x329), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
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{"and.ft", OP_REG(0x328), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
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/* Bitwise AND with ones complement of source 2 */
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{"and.tf", OP_SI(0x12), MASK_SI, FMT_SI, {SUBF, REG22, REG27} },
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{"and.tf", OP_LI(0x325), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
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{"and.tf", OP_REG(0x324), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
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/* WORK IN PROGRESS BELOW THIS POINT */
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{"brcr", OP_LI(0x30D), MASK_LI, FMT_LI, FIXME},
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{"brcr", OP_REG(0x30C), MASK_REG, FMT_REG, FIXME},
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{"brcr", OP_SI(0x6), MASK_SI, FMT_SI, FIXME},
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{"cmnd", OP_LI(0x305), MASK_LI, FMT_LI, FIXME},
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{"cmnd", OP_REG(0x304), MASK_REG, FMT_REG, FIXME},
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{"cmnd", OP_SI(0x2), MASK_SI, FMT_SI, FIXME},
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{"illop0", OP_SI(0), MASK_SI, FMT_SI, FIXME},
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{"ld", OP_LI(0x345), MASK_LI_M, FMT_LI, FIXME},
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{"ld", OP_REG(0x344), MASK_REG_M, FMT_REG, FIXME},
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{"ld", OP_SI(0x22), MASK_SI_M, FMT_SI, FIXME},
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{"ld.b", OP_LI(0x341), MASK_LI_M, FMT_LI, FIXME},
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{"ld.b", OP_REG(0x340), MASK_REG_M, FMT_REG, FIXME},
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{"ld.b", OP_SI(0x20), MASK_SI_M, FMT_SI, FIXME},
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{"ld.d", OP_LI(0x347), MASK_LI_M, FMT_LI, FIXME},
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{"ld.d", OP_REG(0x346), MASK_REG_M, FMT_REG, FIXME},
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{"ld.d", OP_SI(0x23), MASK_SI_M, FMT_SI, FIXME},
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{"ld.h", OP_LI(0x343), MASK_LI_M, FMT_LI, FIXME},
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{"ld.h", OP_REG(0x342), MASK_REG_M, FMT_REG, FIXME},
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{"ld.h", OP_SI(0x21), MASK_SI_M, FMT_SI, FIXME},
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{"ld.u", OP_LI(0x355), MASK_LI_M, FMT_LI, FIXME},
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{"ld.u", OP_REG(0x354), MASK_REG_M, FMT_REG, FIXME},
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{"ld.u", OP_SI(0x2A), MASK_SI_M, FMT_SI, FIXME},
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{"ld.ub", OP_LI(0x351), MASK_LI_M, FMT_LI, FIXME},
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{"ld.ub", OP_REG(0x350), MASK_REG_M, FMT_REG, FIXME},
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{"ld.ub", OP_SI(0x28), MASK_SI_M, FMT_SI, FIXME},
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{"ld.ud", OP_LI(0x357), MASK_LI_M, FMT_LI, FIXME},
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{"ld.ud", OP_REG(0x356), MASK_REG_M, FMT_REG, FIXME},
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{"ld.ud", OP_SI(0x2B), MASK_SI_M, FMT_SI, FIXME},
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{"ld.uh", OP_LI(0x353), MASK_LI_M, FMT_LI, FIXME},
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{"ld.uh", OP_REG(0x352), MASK_REG_M, FMT_REG, FIXME},
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{"ld.uh", OP_SI(0x29), MASK_SI_M, FMT_SI, FIXME},
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{"or.ff", OP_LI(0x33D), MASK_LI, FMT_LI, FIXME},
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{"or.ff", OP_REG(0x33C), MASK_REG, FMT_REG, FIXME},
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{"or.ff", OP_SI(0x1E), MASK_SI, FMT_SI, FIXME},
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{"or.ft", OP_LI(0x33B), MASK_LI, FMT_LI, FIXME},
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{"or.ft", OP_REG(0x33A), MASK_REG, FMT_REG, FIXME},
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{"or.ft", OP_SI(0x1D), MASK_SI, FMT_SI, FIXME},
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{"or.tf", OP_LI(0x337), MASK_LI, FMT_LI, FIXME},
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{"or.tf", OP_REG(0x336), MASK_REG, FMT_REG, FIXME},
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{"or.tf", OP_SI(0x1B), MASK_SI, FMT_SI, FIXME},
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{"or.tt", OP_LI(0x32F), MASK_LI, FMT_LI, FIXME},
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{"or.tt", OP_REG(0x32E), MASK_REG, FMT_REG, FIXME},
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{"or.tt", OP_SI(0x17), MASK_SI, FMT_SI, FIXME},
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{"rdcr", OP_LI(0x309), MASK_LI, FMT_LI, FIXME},
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{"rdcr", OP_REG(0x308), MASK_REG, FMT_REG, FIXME},
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{"rdcr", OP_SI(0x4), MASK_SI, FMT_SI, FIXME},
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{"shift.dm", OP_REG(0x312), MASK_REG, FMT_REG, FIXME},
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{"shift.dm", OP_SI(0x9), MASK_SI, FMT_SI, FIXME},
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{"shift.ds", OP_REG(0x314), MASK_REG, FMT_REG, FIXME},
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{"shift.ds", OP_SI(0xA), MASK_SI, FMT_SI, FIXME},
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||||
{"shift.dz", OP_REG(0x310), MASK_REG, FMT_REG, FIXME},
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{"shift.dz", OP_SI(0x8), MASK_SI, FMT_SI, FIXME},
|
||||
{"shift.em", OP_REG(0x318), MASK_REG, FMT_REG, FIXME},
|
||||
{"shift.em", OP_SI(0xC), MASK_SI, FMT_SI, FIXME},
|
||||
{"shift.es", OP_REG(0x31A), MASK_REG, FMT_REG, FIXME},
|
||||
{"shift.es", OP_SI(0xD), MASK_SI, FMT_SI, FIXME},
|
||||
{"shift.ez", OP_REG(0x316), MASK_REG, FMT_REG, FIXME},
|
||||
{"shift.ez", OP_SI(0xB), MASK_SI, FMT_SI, FIXME},
|
||||
{"shift.im", OP_REG(0x31E), MASK_REG, FMT_REG, FIXME},
|
||||
{"shift.im", OP_SI(0xF), MASK_SI, FMT_SI, FIXME},
|
||||
{"shift.iz", OP_REG(0x31C), MASK_REG, FMT_REG, FIXME},
|
||||
{"shift.iz", OP_SI(0xE), MASK_SI, FMT_SI, FIXME},
|
||||
{"st", OP_LI(0x365), MASK_LI_M, FMT_LI, FIXME},
|
||||
{"st", OP_REG(0x364), MASK_REG_M, FMT_REG, FIXME},
|
||||
{"st", OP_SI(0x32), MASK_SI_M, FMT_SI, FIXME},
|
||||
{"st.b", OP_LI(0x361), MASK_LI_M, FMT_LI, FIXME},
|
||||
{"st.b", OP_REG(0x360), MASK_REG_M, FMT_REG, FIXME},
|
||||
{"st.b", OP_SI(0x30), MASK_SI_M, FMT_SI, FIXME},
|
||||
{"st.d", OP_LI(0x367), MASK_LI_M, FMT_LI, FIXME},
|
||||
{"st.d", OP_REG(0x366), MASK_REG_M, FMT_REG, FIXME},
|
||||
{"st.d", OP_SI(0x33), MASK_SI_M, FMT_SI, FIXME},
|
||||
{"st.h", OP_LI(0x363), MASK_LI_M, FMT_LI, FIXME},
|
||||
{"st.h", OP_REG(0x362), MASK_REG_M, FMT_REG, FIXME},
|
||||
{"st.h", OP_SI(0x31), MASK_SI_M, FMT_SI, FIXME},
|
||||
{"swcr", OP_LI(0x30B), MASK_LI, FMT_LI, FIXME},
|
||||
{"swcr", OP_REG(0x30A), MASK_REG, FMT_REG, FIXME},
|
||||
{"swcr", OP_SI(0x5), MASK_SI, FMT_SI, FIXME},
|
||||
{"trap", OP_LI(0x303), MASK_LI, FMT_LI, FIXME},
|
||||
{"trap", OP_REG(0x302), MASK_REG, FMT_REG, FIXME},
|
||||
{"trap", OP_SI(0x1), MASK_SI, FMT_SI, FIXME},
|
||||
{"xnor", OP_LI(0x333), MASK_LI, FMT_LI, FIXME},
|
||||
{"xnor", OP_REG(0x332), MASK_REG, FMT_REG, FIXME},
|
||||
{"xnor", OP_SI(0x19), MASK_SI, FMT_SI, FIXME},
|
||||
{"xor", OP_LI(0x32D), MASK_LI, FMT_LI, FIXME},
|
||||
{"xor", OP_REG(0x32C), MASK_REG, FMT_REG, FIXME},
|
||||
{"xor", OP_SI(0x16), MASK_SI, FMT_SI, FIXME},
|
||||
|
||||
};
|
||||
|
||||
const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue