* mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". Matsushita.
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@ -1,3 +1,8 @@
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Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com)
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* mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
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"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
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Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com)
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* mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
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@ -366,6 +366,20 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "rtm", 0xf0ff, 0xffff, FMT_D0, {UNUSED}},
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{ "nop", 0xcb, 0xff, FMT_S0, {UNUSED}},
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/* { "udf", 0, 0, {0}}, */
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{ "putx", 0xf500, 0xfff0, FMT_D0, {DM}},
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{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN}},
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{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM, DN}},
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{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN}},
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{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN}},
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{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN}},
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{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM, DN}},
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{ "mulqu", 0xf90400, 0xfffc00, FMT_D1, {SIMM8, DN}},
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{ "mulqu", 0xfb040000, 0xfffc0000, FMT_D2, {SIMM16, DN}},
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{ "mulqu", 0xfd040000, 0xfffc0000, FMT_D4, {IMM32, DN}},
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{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM, DN}},
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{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM, DN}},
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{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM, DN}},
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{ 0, 0, 0, 0, {0}},
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} ;
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