* mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2
operands (for indexed load/stores). Fix bitpos for DI
operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
few instructions that insert immediates/displacements in the
middle of the instruction. Add IMM8E for 8 bit immediate in
the extended part of an instruction.
(mn10300_operands): Use new opcodes as appropriate.
Opcode table changes so we can correctly insert everything except
32bit operands.
This commit is contained in:
Jeff Law
parent
d13f39914f
commit
bb5e141ab4
2 changed files with 57 additions and 20 deletions
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@ -1,3 +1,13 @@
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Tue Nov 5 13:26:58 1996 Jeffrey A Law (law@cygnus.com)
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* mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2
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operands (for indexed load/stores). Fix bitpos for DI
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operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
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few instructions that insert immediates/displacements in the
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middle of the instruction. Add IMM8E for 8 bit immediate in
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the extended part of an instruction.
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(mn10300_operands): Use new opcodes as appropriate.
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start-sanitize-d10v
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Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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@ -29,25 +29,37 @@ const struct mn10300_operand mn10300_operands[] = {
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#define DN1 (DN0+1)
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{2, 2, MN10300_OPERAND_DREG},
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#define DM0 (DN1+1)
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#define DN2 (DN1+1)
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{2, 4, MN10300_OPERAND_DREG},
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#define DM0 (DN2+1)
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{2, 0, MN10300_OPERAND_DREG},
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#define DM1 (DM0+1)
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{2, 2, MN10300_OPERAND_DREG},
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#define AN0 (DM1+1)
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#define DM2 (DM1+1)
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{2, 4, MN10300_OPERAND_DREG},
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#define AN0 (DM2+1)
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{2, 0, MN10300_OPERAND_AREG},
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#define AN1 (AN0+1)
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{2, 2, MN10300_OPERAND_AREG},
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#define AM0 (AN1+1)
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#define AN2 (AN1+1)
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{2, 4, MN10300_OPERAND_AREG},
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#define AM0 (AN2+1)
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{2, 0, MN10300_OPERAND_AREG},
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#define AM1 (AM0+1)
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{2, 2, MN10300_OPERAND_AREG},
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#define IMM8 (AM1+1)
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#define AM2 (AM1+1)
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{2, 4, MN10300_OPERAND_AREG},
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#define IMM8 (AM2+1)
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{8, 0, MN10300_OPERAND_PROMOTE},
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#define IMM16 (IMM8+1)
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@ -81,7 +93,7 @@ const struct mn10300_operand mn10300_operands[] = {
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{32, 0, 0},
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#define DI (ABS32+1)
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{2, 0, MN10300_OPERAND_DREG},
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{2, 2, MN10300_OPERAND_DREG},
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#define SD8 (DI+1)
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{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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@ -92,7 +104,10 @@ const struct mn10300_operand mn10300_operands[] = {
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#define SD8N (SD16+1)
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{8, 0, MN10300_OPERAND_SIGNED},
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#define SIMM8 (SD8N+1)
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#define SD8N_SHIFT8 (SD8N+1)
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{8, 8, MN10300_OPERAND_SIGNED},
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#define SIMM8 (SD8N_SHIFT8+1)
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{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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#define SIMM16 (SIMM8+1)
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@ -107,6 +122,15 @@ const struct mn10300_operand mn10300_operands[] = {
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#define AN01 (DN01+1)
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{2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
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#define D16_SHIFT (AN01+1)
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{16, 8, MN10300_OPERAND_PROMOTE},
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#define IMM8E (D16_SHIFT+1)
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{8, 0, MN10300_OPERAND_EXTENDED},
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#define IMM8_SHIFT8 (IMM8E + 1)
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{8, 8, 0},
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} ;
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#define MEM(ADDR) PAREN, ADDR, PAREN
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@ -149,7 +173,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(D8, SP), DN0}},
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{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN0}},
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{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN0}},
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{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN0}},
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{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
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{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}},
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{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN0}},
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{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM0), AN1}},
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@ -159,7 +183,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(D8, SP), AN0}},
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{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), AN0}},
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{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), AN0}},
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{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN0}},
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{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN2}},
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{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(ABS16), AN0}},
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{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(ABS32), AN0}},
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{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM0), SP}},
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@ -170,7 +194,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "mov", 0x4200, 0xf300, FMT_S1, {DM1, MEM2(D8, SP)}},
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{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM1, MEM2(D16, SP)}},
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{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM1, MEM2(D32, SP)}},
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{ "mov", 0xf340, 0xffc0, FMT_D0, {DM0, MEM2(DI, AN0)}},
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{ "mov", 0xf340, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
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{ "mov", 0x010000, 0xf30000, FMT_S2, {DM1, MEM(ABS16)}},
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{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM1, MEM(ABS32)}},
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{ "mov", 0xf010, 0xfff0, FMT_D0, {AM1, MEM(AN0)}},
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@ -180,7 +204,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "mov", 0x4300, 0xf300, FMT_S1, {AM1, MEM2(D8, SP)}},
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{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM1, MEM2(D16, SP)}},
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{ "mov", 0xfc900000, 0xfc930000, FMT_D4, {AM1, MEM2(D32, SP)}},
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{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM0, MEM2(DI, AN0)}},
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{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM2, MEM2(DI, AN0)}},
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{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM1, MEM(ABS16)}},
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{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM1, MEM(ABS32)}},
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{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN0)}},
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@ -196,7 +220,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(D8, SP), DN0}},
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{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN0}},
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{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN0}},
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{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN0}},
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{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
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{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}},
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{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN0}},
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{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
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@ -206,7 +230,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM1, MEM2(D8, SP)}},
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{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM1, MEM2(D16, SP)}},
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{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM1, MEM2(D32, SP)}},
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{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM0, MEM2(DI, AN0)}},
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{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
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{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM1, MEM(ABS16)}},
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{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM1, MEM(ABS32)}},
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@ -217,7 +241,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(D8, SP), DN0}},
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{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN0}},
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{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN0}},
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{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN0}},
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{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
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{ "movhu", 0x380000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}},
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{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN0}},
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{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
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@ -227,7 +251,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM1, MEM2(D8, SP)}},
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{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM1, MEM2(D16, SP)}},
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{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM1, MEM2(D32, SP)}},
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{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM0, MEM2(DI, AN0)}},
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{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
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{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM1, MEM(ABS16)}},
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{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM1, MEM(ABS32)}},
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@ -305,13 +329,16 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
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{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
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{ "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
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{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}},
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{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2,
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{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
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{ "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
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{ "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
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{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}},
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{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2,
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{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
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{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
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{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
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{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}},
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{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8,
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MEM2(SD8N_SHIFT8,AN0)}},
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{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}},
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{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}},
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@ -356,14 +383,14 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {AN0}},
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{ "jmp", 0xcc0000, 0xff0000, FMT_S2, {D16}},
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{ "jmp", 0xdc0000, 0xff0000, FMT_S4, {D32}},
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{ "call", 0xcd000000, 0xff000000, FMT_S4, {D16,IMM8,IMM8}},
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{ "call", 0xcd000000, 0xff000000, FMT_S4, {D16_SHIFT,IMM8,IMM8E}},
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{ "call", 0xdd000000, 0xff000000, FMT_S6, {D32,IMM8,IMM8}},
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{ "calls", 0xf0f0, 0xfffc, FMT_D0, {AN0}},
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{ "calls", 0xfaff0000, 0xffff0000, FMT_D2, {D16}},
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{ "calls", 0xfcff0000, 0xffff0000, FMT_D4, {D32}},
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{ "ret", 0xdf0000, 0xff00000, FMT_S2, {IMM8, IMM8}},
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{ "retf", 0xde0000, 0xff00000, FMT_S2, {IMM8, IMM8}},
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{ "ret", 0xdf0000, 0xff00000, FMT_S2, {IMM8_SHIFT8, IMM8}},
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{ "retf", 0xde0000, 0xff00000, FMT_S2, {IMM8_SHIFT8, IMM8}},
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{ "rets", 0xf0fc, 0xffff, FMT_D0, {UNUSED}},
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{ "rti", 0xf0fd, 0xffff, FMT_D0, {UNUSED}},
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{ "trap", 0xf0fe, 0xffff, FMT_D0, {UNUSED}},
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