* gas/i386/opcode-intel.d: Undo the last change.
* gas/i386/opcode-suffix.d: Likewise.
* gas/i386/opcode.d: Likewise.
* gas/i386/opcode.s: Likewise.
* gas/i386/prefix.s: Add test for fwait with prefix.
* gas/i386/prefix.d: Updated.
0x9b (fwait) is both an instruction and an opcode prefix. When 0x9b is
treated as an instruction, we need to handle any prefixes before it.
This patch handles it properly.
gas/testsuite/
PR binutils/16891
* gas/i386/opcode.s: Add test for fwait with prefix.
* gas/i386/opcode-intel.d: Updated.
* gas/i386/opcode-suffix.d: Likewise.
* gas/i386/opcode.d: Likewise.
opcodes/
PR binutils/16891
* i386-dis.c (print_insn): Handle prefixes before fwait.
Fix various places where endianness needed to be taken into account
in the gas testsuite for ARM.
gas/testsuite/ChangeLog:
2014-04-23 Will Newton <will.newton@linaro.org>
* gas/arm/backslash-at.d: Fix dump output regexps for
armeb-linux-eabi configuration.
* gas/arm/got_prel.d: Likewise.
* gas/arm/inst-po.d: Likewise.
* gas/arm/unwind.d: Likewise.
If there is a a trailing align statement in a code section we may
output data padding with a data mapping followed by a code alignment
with a code mapping. The literal pool may then be output with a code
mapping symbol which will cause it to be endian swapped in a big-endian
configuration. When outputting a literal pool make sure that a data
mapping symbol is output in all cases.
gas/ChangeLog:
2014-04-23 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (s_ltorg): Call make_mapping_symbol
directly instead of mapping_state.
gas/testsuite/ChangeLog:
2014-04-23 Will Newton <will.newton@linaro.org>
* gas/arm/mapmisc.d: Check literal pool mapping with
a trailing .align statement.
* gas/arm/mapmisc.s: Likewise.
ChangeLog:
binutils/
* doc/binutils.texi: Document the disassemble MIPS XPA instructions
command line option.
gas/
* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
(md_longopts): Add xpa and no-xpa command line options.
(mips_ases): Add MIPS XPA ASE.
(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
* doc/as.texinfo: Document the MIPS XPA command line options.
* doc/c-mips.texi: Document the MIPS XPA command line options,
and assembler directives.
gas/testsuite/
* gas/mips/mips.exp: Add xpa tests.
* gas/mips/xpa.s: New test.
* gas/mips/xpa.d: Likewise.
include/
* opcode/mips.h (ASE_XPA): New define.
opcodes/
* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
to allow the MIPS XPA ASE.
(parse_mips_dis_option): Process the -Mxpa option.
* mips-opc.c (XPA): New define.
(mips_builtin_opcodes): Add MIPS XPA instructions and move the
locations of the ctc0 and cfc0 instructions.
Linking object files produced by partial linking with link-time
relaxation enabled sometimes fails with the following error message:
dangerous relocation: call8: misaligned call target: (.text.unlikely+0x63)
This happens because no basic block with an XTENSA_PROP_ALIGN flag in the
property table is generated for the first basic block, even if the
.align directive is present.
It was believed that the first frag alignment could be derived from the
section alignment, but this was not implemented for the partial linking
case: after partial linking first frag of a section may become not
first, but no additional alignment frag is inserted before it.
Basic block for such frag may be merged with previous basic block into
extended basic block during relaxation pass losing its alignment
restrictions.
Fix this by always recording alignment for the first section frag.
2014-04-22 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (xtensa_handle_align): record alignment for the
first section frag.
gas/testsuite/
* gas/xtensa/all.exp: Add test for the first section frag alignment.
* gas/xtensa/first_frag_align.d: First section frag alignment expected
dump.
* gas/xtensa/first_frag_align.s: First section frag alignment test
source.
(enum options): add OPTION_RMW_ISA for -mrmw option.
(struct option md_longopts): Add mrmw option.
(md_show_usage): add -mrmw option description.
(md_parse_option): Update isa details if -mrmw option specified.
* doc/c-avr.texi: Add doc for new option -mrmw.
* gas/avr/avr.exp: Run new tests.
* gas/avr/rmw.d: Add test for additional ISA support.
* gas/avr/rmw.s: Ditto.
For gathers with indices larger than elements (e. g.)
vpgatherqd ymm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123]
We currently treat memory size as a size of index register, while it is
actually should be size of destination register:
vpgatherqd ymm6{k1}, YMMWORD PTR [ebp+zmm7*8-123]
This patch fixes it.
opcodes/
* i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
vscatterqps.
* i386-tbl.h: Regenerate.
gas/testsuite/
* gas/i386/avx512pf-intel.d: Change memory size for vgatherpf0qps,
vgatherpf1qps, vscatterpf0qps, vscatterpf1qps.
* gas/i386/avx512pf.s: Ditto.
* gas/i386/x86-64-avx512pf-intel.d: Ditto.
* gas/i386/x86-64-avx512pf.s: Ditto.
* gas/i386/avx512f-intel.d: Change memory size for vgatherqps,
vpgatherqd, vpscatterqd, vscatterqps.
* gas/i386/avx512f.s: Ditto.
* gas/i386/x86-64-avx512f-intel.d: Ditto.
* gas/i386/x86-64-avx512f.s: Ditto.
and %hstick_enable to the Sparc assembler.
* config/tc-sparc.c (hpriv_reg_table): Added entries for
%hstick_offset and %hstick_enable.
* doc/c-sparc.texi (Sparc-Regs): Document the %hstick_offset and
%hstick_enable hyperprivileged registers.
* sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
%hstick_enable added.
* gas/sparc/rdhpr.s: Test rd %hstick_offset and %hstick_enable.
* gas/sparc/rdhpr.d: Likewise.
* gas/sparc/wrhpr.s: Test wr %hstick_offset and %hstick_enable.
* gas/sparc/wrhpr.d: Likewise.
* config/tc-arm.c (codecomposer_syntax): New flag that states whether the
CCS syntax compatibility mode is on or off.
(asmfunc_states): New enum to represent the asmfunc directive state.
(asmfunc_state): New variable holding the asmfunc directive state.
(comment_chars): Rename to arm_comment_chars.
(line_separator_chars): Rename to arm_line_separator_chars.
(s_ccs_ref): New function that handles the .ref directive.
(asmfunc_debug): New function.
(s_ccs_asmfunc): New function that handles the .asmfunc directive.
(s_ccs_endasmfunc): New function that handles the .endasmfunc directive.
(s_ccs_def): New function that handles the .def directive.
(tc_start_label_without_colon): New function.
(md_pseudo_table): Added new CCS directives.
(arm_ccs_mode): New function that handles the -mccs command line option.
(arm_long_opts): Added new -mccs command line option.
* config/tc-arm.h (LABELS_WITHOUT_COLONS): New macro.
(TC_START_LABEL_WITHOUT_COLON): New macro.
(tc_start_label_without_colon): Added extern function declaration.
(tc_comment_chars): Define.
(tc_line_separator_chars): Define.
* app.c (do_scrub_begin): Use tc_line_separator_chars, if defined.
* read.c (read_begin): Likewise.
* doc/as.texinfo: Add documentation for the -mccs command line
option.
* doc/c-arm.texi: Likewise.
* doc/internals.texi: Document tc_line_separator_chars.
* NEWS: Mention the new feature.
* gas/arm/ccs.s: New test case.
* gas/arm/ccs.d: New expected disassembly.
* rx-decode.opc (bwl): Allow for bogus instructions with a size
field of 3.
(sbwl, ubwl, SCALE): Likewise.
* rx-decode.c: Regenerate.
* gas/rx/mov.d: Update expected disassembly.
bfd/
* peicode.h (pe_ILF_object_p): Adjust, as the version number
has been read.
(pe_bfd_object_p): Also read version number to detect ILF.
* pe-x86_64.c (COFF_WITH_PE_BIGOBJ): Define.
(x86_64pe_bigobj_vec): Define
* coffcode.h (bfd_coff_backend_data): Add _bfd_coff_max_nscns field.
(bfd_coff_max_nscns): New macro.
(coff_compute_section_file_positions): Use unsigned int for
target_index. Compare with bfd_coff_max_nscns.
(bfd_coff_std_swap_table, ticoff0_swap_table, ticoff1_swap_table):
Set a value for _bfd_coff_max_nscns.
(header_bigobj_classid): New constant.
(coff_bigobj_swap_filehdr_in, coff_bigobj_swap_filehdr_out)
(coff_bigobj_swap_sym_in, coff_bigobj_swap_sym_out)
(coff_bigobj_swap_aux_in, coff_bigobj_swap_aux_out): New
functions.
(bigobj_swap_table): New table.
* libcoff.h: Regenerate.
* coff-sh.c (bfd_coff_small_swap_table): Likewise.
* coff-alpha.c (alpha_ecoff_backend_data): Add value for
_bfd_coff_max_nscns.
* coff-mips.c (mips_ecoff_backend_data): Likewise.
* coff-rs6000.c (bfd_xcoff_backend_data)
(bfd_pmac_xcoff_backend_data): Likewise.
* coff64-rs6000.c (bfd_xcoff_backend_data)
(bfd_xcoff_aix5_backend_data): Likewise.
* targets.c (x86_64pe_bigobj_vec): Declare.
* configure.in (x86_64pe_bigobj_vec): New vector.
* configure: Regenerate.
* config.bfd: Add bigobj object format for Windows targets.
gas/
* config/tc-i386.c (use_big_obj): Declare.
(OPTION_MBIG_OBJ): Define.
(md_longopts): Add -mbig-obj option.
(md_parse_option): Handle it.
(md_show_usage): Display help for this option.
(i386_target_format): Use bigobj for x86-64 if -mbig-obj.
* doc/c-i386.texi: Document the option.
gas/testsuite/
* gas/pe/big-obj.d, gas/pe/big-obj.s: Add test.
* gas/pe/pe.exp: Add test.
include/coff/
* pe.h (struct external_ANON_OBJECT_HEADER_BIGOBJ): Declare.
(FILHSZ_BIGOBJ): Define.
(struct external_SYMBOL_EX): Declare.
(SYMENT_BIGOBJ, SYMESZ_BIGOBJ): Define.
(union external_AUX_SYMBOL_EX): Declare.
(AUXENT_BIGOBJ, AUXESZ_BIGOBJ): Define.
* internal.h (struct internal_filehdr): Change type
of f_nscns.
that if multiple bignum values are encountered only the most recent is valid.
If such expressions are cached, eg to be emitted into a literal pool later on
in the assembly, then only one expression - the last - will be correct. This
patch fixes the problem for the AArch64 target by caching each bignum value
locally.
PR gas/16688
* config/tc-aarch64.c (literal_expression): New structure.
(literal_pool): Replace exp array with literal_expression array.
(add_to_lit_pool): When adding a bignum cache the big value.
(s_ltorg): When emitting a bignum initialise the global bignum
array from the cached value.
* gas/aarch64/litpool.s: New test case.
* gas/aarch64/litpool.d: Expected disassembly.
generate warning messages about an instruction that changes the interrupt
state not being followed by a NOP instruction.
* config/msp430/msp430.c: Replace known mcu array with known
msp430 ISA mcu name array.
Accept any name for -mmcu option.
Add -mz option to warn about missing NOP following an interrupt
status change.
(check_for_nop): New.
(msp430_operands): Emit a warning, if requested, when an interrupt
changing instruction is not followed by a NOP.
* doc/c-msp430.c: Document -mz option.
* gas/msp430/bad.d: Add -mz option.
* gas/msp430/bad.s: Add more cases where warnings should be
generated.
* gas/msp430/bad.l: Add expected warning messages.
SHF_INFO_LINK bit set, which shows up in readelf section dumps. This
has broken a couple of IA64 testcases in the gas testsuite, which are
fixed by this patch.
PR binutils/16317
* gas/ia64/group-2.d: Expect I attribute with RELA sections.
* gas/ia64/xdata.d: Likewise.
The direct rounding floating-point VCVT instructions introduced in
ARMv8 encode the s32.f64 variant incorrectly. The op bit should be
set to 1 for all signed conversions.
gas/ChangeLog:
2014-01-17 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_vfp_nsyn_cvt_fpv8): Set OP to 1
for the s32.f64 flavours of VCVT.
gas/testsuite/ChangeLog:
2014-01-17 Will Newton <will.newton@linaro.org>
* gas/arm/armv8-a+fp.d: Correct encoding of vcvta.s32.f64.
Add two more as test files for user special and system register.
Fix typo.
2013-12-17 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* gas/nds32/nds32.exp: Add system and user special register tests.
* gas/nds32/sys-reg.s: New test.
* gas/nds32/sys-reg.d: Likewise.
* gas/nds32/usr-spe-reg.s: Likewise.
* gas/nds32/usr-spe-reg.d: Likewise.
* gas/nds32/alu-2.d: Delete the new blank line at EOF.
* gas/nds32/br-1.d: Likewise.
* gas/nds32/br-2.d: Likewise.
* gas/nds32/ji-jr.d: Likewise.
* gas/nds32/lsi.d: Likewise.
* nds32-dis.c (sr_map): Add system register table for disassembling.
(usr_map): Fix typo.
* nds32-asm.c (keyword_sr): Add embedded debug registers.
2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
gas/testsuite/gas/mips/
* mips.exp: Add CP1 register name tests.
* cp1-names-mips32.d: New test.
* cp1-names-mips32r2.d: New test.
* cp1-names-mips64.d: New test.
* cp1-names-mips64r2.d: New test.
* cp1-names-numeric.d: New test.
* cp1-names-r3000.d: New test.
* cp1-names-r4000.d: New test.
* cp1-names-sb1.d: New test.
* cp1-names.s: New test.
* micromips-insn32.d: Add the correct symbolic names for the CP1
registers.
* micromips-noinsn32.d: Likewise.
* micromips-trap.d: Likewise.
* micromips.d: Likewise.
opcodes/
* mips-dis.c: Add mips_cp1_names pointer.
(mips_cp1_names_numeric): New array.
(mips_cp1_names_mips3264): New array.
(mips_arch_choice): Add cp1_names.
(mips_arch_choices): Add relevant cp1 register name array to each of
the elements.
(set_default_mips_dis_options): Add support for setting up the
mips_cp1_names pointer.
(parse_mips_dis_option): Add support for the cp1-names command line
variable. Also setup the mips_cp1_names pointer.
(print_reg): Print out name of the cp1 register.
The element index range for the following MIPS MSA instructions: sldi, splati,
copy_s, copy_u, insert and insve is 1 bit too large. This patch fixes this issue.
ChangeLog:
gas/testsuite/gas/mips/
* msa.s: Reduced maximum element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* msa64.s: Likewise.
* micromips@msa.d: Likewise.
* micromips@msa64.d: Likewise.
* msa.d: Likewise.
* msa64.d: Likewise.
include/opcode/
* mips.h: Updated description of +o, +u, +v and +w for MIPS and
microMIPS.
opcodes/
* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
+v and +w.
(micromips_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
+v and +w.
(mips_builtin_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
These files are source files and have no business being +x. We couldn't
easily fix it in CVS (you need login+write access to the raw rcs files),
but we can fix this w/git.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-11-27 Matthew Fortune <matthew.fortune@imgtec.com>
* binutils-all/objcopy.exp: Consider mips-mti-elf the same as
mips-sde-elf
* binutils-all/readelf.exp: Likewise
gas/testsuite/
2013-11-27 Matthew Fortune <matthew.fortune@imgtec.com>
* gas/mips/mips.exp: Consider mips-mti-elf the same as mips-sde-elf
ld/testsuite/
2013-11-27 Matthew Fortune <matthew.fortune@imgtec.com>
* ld-mips-elf/mips-elf.exp: Consider mips-mti-elf the same as
mips-sde-elf
gas/
* config/tc-arm.c (arm_archs): New armv7ve architecture option.
(arm_cpus): Replace ARM_ARCH_V7A_IDIV_MP_SEC_VIRT with
ARM_ARCH_V7VE for cortex-a7, cortex-a12 and cortex-a15.
(cpu_arch_ver): Likewise.
* doc/c-arm.texi: Document armv7ve.
gas/testsuite/
* gas/arm/attr-march-armv7ve.d: New test case for armv7ve.
include/opcode/
* arm.h (ARM_AEXT_V7VE): New define.
(ARM_ARCH_V7VE): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
* config/tc-aarch64.c (set_other_error): New function.
(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
the variable to which it points with 'o'.
(parse_operands): Update; check for write to read-only system
registers or read from write-only ones.
gas/testsuite/
* gas/aarch64/diagnostic.s: Add tests.
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/tracereg-illegal.d: New file.
* gas/aarch64/tracereg-illegal.l: Ditto.
* gas/aarch64/tracereg-illegal.s: Ditto.
* gas/aarch64/tracereg.d: Ditto.
* gas/aarch64/tracereg.s: Ditto.
include/opcode
* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
(aarch64_sys_reg_writeonly_p): Ditto.
opcodes/
* aarch64-opc.c (CPENT): New define.
(F_READONLY, F_WRITEONLY): Likewise.
(aarch64_sys_regs): Add trace unit registers.
(aarch64_sys_reg_readonly_p): New function.
(aarch64_sys_reg_writeonly_p): Ditto.
* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg;
call aarch64_sys_reg_deprecated_p and warn about the deprecated
system registers.
gas/testsuite/
* gas/aarch64/deprecated.d: New file.
* gas/aarch64/deprecated.l: New file.
* gas/aarch64/deprecated.s: New file.
* gas/aarch64/sysreg-1.s: Add tests.
* gas/aarch64/sysreg-1.d: Add tests.
include/opcode/
* aarch64.h (aarch64_sys_reg): New typedef.
(aarch64_sys_regs): Change to define with the new type.
(aarch64_sys_reg_deprecated_p): Declare.
opcodes/
* aarch64-opc.c (F_DEPRECATED): New macro.
(aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
F_DEPRECATED.
(aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
AARCH64_OPND_SYSREG.
Parsing a vector mov instruction currently leads to a phantom undefined
symbol being added to the symbol table. e.g.:
.text
mov x0, v0.D[0]
Produces an undefined symbol called "v0.D".
gas/ChangeLog:
2013-11-05 Will Newton <will.newton@linaro.org>
PR gas/16103
* config/tc-aarch64.c (parse_operands): Avoid trying to
parse a vector register as an immediate.
gas/testsuite/ChangeLog:
2013-11-05 Will Newton <will.newton@linaro.org>
* gas/aarch64/advsimd-mov-bad.d: New file.
* gas/aarch64/advsimd-mov-bad.s: Likewise.
Without this, constructs like "orw %rax, (%rax)" aren't being rejected
(other than any other wrong suffix/register combination).
gas/
2013-11-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_long_reg): Correct comment indentation.
(check_qword_reg): Correct comment and its indentation.
(check_word_reg): Extend comment and correct its indentation. Also
check for 64-bit register.
gas/testsuite/
2013-11-04 Jan Beulich <jbeulich@suse.com>
* gas/i386/x86-64-suffix-bad.[sl]: New.
* gas/i386/i386.exp: Run new test.
I think HJ has already fixed the binutils and ld tests with his
2013-09-27 readelf change, but this allows them to pass with wider
address output as per Nick's 2013-09-12 readelf change.
binutils/testsuite/
* binutils-all/x86-64/compressed-1a.d: Allow wide display of addresses.
gas/testsuite/
* gas/cfi/cfi-x86_64.d: Match when lacking end of section padding.
ld/testsuite/
* ld-pe/cfi.d: Allow wide display of addresses.
There's no real need to emit these always: They're needed only if we
indeed want to emit a localized symbol. Hence defer emission until we
at least did the basic early checks that would lead to no such symbol
getting emitted. This in particular avoids emitting such a symbol in
the majority of (if not all) "ld -r" cases.
I hope my set of cross build tests caught all the test cases needing
adjustment - please forgive if I missed a few.
bfd/
2013-10-29 Jan Beulich <jbeulich@suse.com>
* elflink.c (struct elf_outext_info): Add field file_sym_done.
(bfd_elf_final_link): Initialize new field. Move fake STT_FILE
symbol emission from here ...
(elf_link_output_extsym): ... to here.
gas/testsuite/
2013-10-29 Jan Beulich <jbeulich@suse.com>
* gas/microblaze/relax_size.elf: Drop expectation of no longer
present STT_FILE symbol.
* gas/microblaze/relax_size2.elf: Likewise.
ld/testsuite/
2013-10-29 Jan Beulich <jbeulich@suse.com>
* ld-cris/tls-e-tpoffcomm1.d: Drop expectation of no longer
present STT_FILE symbol.
* ld-mmix/bpo-18.d: Likewise.
* ld-mmix/bpo-22.d: Likewise.
* ld-mmix/greg-6.d: Likewise.
* ld-mmix/greg-7.d: Likewise.
* ld-mmix/loc4.d: Likewise.
* ld-mmix/local1.d: Likewise.
* ld-mmix/local3.d: Likewise.
* ld-mmix/local5.d: Likewise.
* ld-mmix/local7.d: Likewise.
* ld-mmix/loct-1.d: Likewise.
* ld-sh/sh64/abi32.xd: Likewise.
* ld-sh/sh64/abi64.xd: Likewise.
* ld-sh/sh64/cmpct1.xd: Likewise.
* ld-sh/sh64/crange1.rd: Likewise.
* ld-sh/sh64/crange2.rd: Likewise.
* ld-sh/sh64/crange3-cmpct.rd: Likewise.
* ld-sh/sh64/crange3-media.rd: Likewise.
* ld-sh/sh64/crange3.rd: Likewise.
* ld-sh/sh64/crangerel1.rd: Likewise.
* ld-sh/sh64/crangerel2.rd: Likewise.
* ld-sh/sh64/mix1.xd: Likewise.
* ld-sh/sh64/mix2.xd: Likewise.
* ld-sh/sh64/shdl32.xd: Likewise.
* ld-sh/sh64/shdl64.xd: Likewise.
opcodes/
* nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
as the primary name of r30.
gas/
* config/tc-nios2.c (nios2_consume_arg): Make the "ba" warning
also test/refer to "sstatus". Reformat the warning message.
gas/testsuite/
* gas/nios2/warn_nobreak.l: Update text of warning messages.
* gas/nios2/registers.s: Use "sstatus" rather than "ba"
as the primary name of r30.
* gas/nios2/registers.d: Likewise.
for "<foo>a". Issue error messages for unrecognised or corrrupt
size extensions.
* gas/msp430/bad.s: New test: Checks erroneous size extensions.
* gas/msp430/bad.d: New test command file.
* gas/msp430/bad.l: New file: Expected error messages.
* gas/msp430/msp430.exp: Run the new test.
* gas/msp430/msp430x.s: Add "<foo>.a" aliases of "<foo>a"
instructions.
* gas/msp430/msp430x.d: Update expected disassembly.
The existing code would accept VLD2.64 and similar undefined
instructions.
gas/ChangeLog:
2013-09-16 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_neon_ld_st_interleave): Add constraint
disallowing element size 64 with interleave other than 1.
gas/testsuite/ChangeLog:
2013-09-16 Will Newton <will.newton@linaro.org>
* gas/arm/neon-ldst-es.d: Add VLD1.64 instructions.
* gas/arm/neon-ldst-es.s: Likewise.
* testsuite/gas/arm/neon-ldst-es-bad.d: New file.
* testsuite/gas/arm/neon-ldst-es-bad.l: Likewise.
* testsuite/gas/arm/neon-ldst-es-bad.s: Likewise.
* config/tc-ppc.c (md_apply_fix): Handle defined after use toc
symbols.
gas/testsuite/
* gas/ppc/aix.exp: Run xcoff-toc-1 test.
* gas/ppc/xcoff-toc-1.s, gas/ppc/xcoff-toc-1.d: New test.
* config/tc-arm.c (T16_32_TAB): Add _udf.
(do_t_udf): New function.
(insns): Add "udf".
* gas/arm/udf-bad.s: New file.
* gas/arm/udf-bad.d: New file.
* gas/arm/udf-bad.l: New file.
* gas/arm/udf.s: New file.
* gas/arm/udf.d: New file.
* gas/arm/udf.l: New file.
* arm-dis.c (arm_opcodes): Add udf.
(thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
(thumb32_opcodes): Add udf.w.
(print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
immediate is not suitable for the 32-bit ABI.
* gas/aarch64/illegal.s: Add illegal constant for logical
operation.
* gas/aarch64/illegal.l: Add expected error message.
NEON vector load and store instructions do not accept immediates
or pre-indexed base plus offset addressing modes, so make sure that
the assembler enforces this.
gas/ChangeLog:
2013-08-23 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_neon_ldx_stx): Add extra constraints
for pre-indexed addressing modes.
* testsuite/gas/arm/neon-addressing-bad.l: Add test for
VLDn and VSTn instructions.
* testsuite/gas/arm/neon-addressing-bad.s: Likewise.
gas/testsuite/ChangeLog:
2013-08-23 Will Newton <will.newton@linaro.org>
* testsuite/gas/arm/neon-addressing-bad.l: Add test for
VLDn and VSTn instructions.
* testsuite/gas/arm/neon-addressing-bad.s: Likewise.
* mips.h (M_DEXT, M_DINS): Delete.
opcodes/
* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
Use +H rather than +C for the real "dext".
* mips-opc.c (mips_builtin_opcodes): Likewise.
gas/
* config/tc-mips.c (report_bad_range, report_bad_field): Delete.
(macro): Remove M_DEXT and M_DINS handling.
gas/testsuite/
* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
error messages to have the same form as the EXT and INS ones.
* gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d,
gas/mips/micromips-trap.d, gas/mips/micromips.d,
gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect
"dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
* config/tc-mips.c (mips_arg_info): Remove soft_match.
(match_out_of_range, match_not_constant): New functions.
(match_const_int): Remove fallback parameter and check for soft_match.
Use match_not_constant.
(match_mapped_int_operand, match_addiusp_operand)
(match_perf_reg_operand, match_save_restore_list_operand)
(match_mdmx_imm_reg_operand): Update accordingly. Use
match_out_of_range and set_insn_error* instead of as_bad.
(match_int_operand): Likewise. Use match_not_constant in the
!allows_nonconst case.
(match_float_constant): Report invalid float constants.
(match_insn, match_mips16_insn): Remove soft_match code. Rely on
match_float_constant to check for invalid constants. Fail the
match if match_const_int or match_float_constant return false.
(mips_ip): Update accordingly.
(mips16_ip): Likewise. Undo null termination of instruction name
once lookup is complete.
gas/testsuite/
* gas/mips/ext-ill.l, gas/mips/lui-1.l, gas/mips/mips16e-64.l,
gas/mips/mips32r2-ill-fp64.l, gas/mips/mips32r2-ill-nofp.l,
gas/mips/mips32r2-ill.l, gas/mips/mips64r2-ill.l,
gas/mips/octeon-ill.l, gas/mips/r5900-error-vu0.l,
gas/mips/vr5400-ill.l: Adjust expected errors.
* gas/mips/micromips-size-0.l,
gas/mips/micromips-size-0.s: Likewise. Add new tests.
* gas/mips/mips16e-save-err.s, gas/mips/mips16e-save-err.l: New test.
* gas/mips/mips.exp: Run it.
* config/tc-mips.c (mips_insn_error_format): New enum.
(mips_insn_error): New struct.
(insn_error): Change to a mips_insn_error.
(clear_insn_error, set_insn_error_format, set_insn_error)
(set_insn_error_i, set_insn_error_ss, report_insn_error): New
functions.
(mips_parse_argument_token, md_assemble, match_insn)
(match_mips16_insn): Use them instead of manipulating insn_error
directly.
(mips_ip, mips16_ip): Likewise. Simplify control flow.
gas/testsuite/
* gas/mips/micromips-ill.l: Expect "floating-point expression required"
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
VCLIPW.
gas/
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel
suffixes to be elided too.
(mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here.
(mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N
to be omitted too.
gas/testsuite/
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l,
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d: Allow
single-channel suffixes to be elided.
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Document new VU0 operand characters.
(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
(OP_REG_R5900_ACC): New mips_reg_operand_types.
(INSN2_VU0_CHANNEL_SUFFIX): New macro.
(mips_vu0_channel_mask): Declare.
opcodes/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(print_vu0_channel): New function.
(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(print_insn_args): Handle '#'.
(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
* mips-opc.c (mips_vu0_channel_mask): New constant.
(decode_mips_operand): Handle new VU0 operand types.
(VU0, VU0CH): New macros.
(mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
Use "+6" rather than "G" for QMFC2 and QMTC2.
gas/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
(RWARN): Bump to 0x8000000.
(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
(RTYPE_R5900_ACC): New register types.
(RTYPE_MASK): Include them.
(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
macros.
(reg_names): Include them.
(mips_parse_register_1): New function, split out from...
(mips_parse_register): ...here. Add a channels_ptr parameter.
Look for VU0 channel suffixes when nonnull.
(reg_lookup): Update the call to mips_parse_register.
(mips_parse_vu0_channels): New function.
(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
(mips_operand_token): Add a "channels" field to the union.
Extend the comment above "ch" to OT_DOUBLE_CHAR.
(mips_parse_base_start): Match -- and ++. Handle channel suffixes.
(mips_parse_argument_token): Handle channel suffixes here too.
(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
Handle '#' formats.
(md_begin): Register $vfN and $vfI registers.
(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(match_vu0_suffix_operand): New function.
(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
(mips_lookup_insn): New function.
(mips_ip): Use it. Allow "+K" operands to be elided at the end
of an instruction. Handle '#' sequences.
gas/testsuite/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
coprocessor registers.
* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
* gas/mips/mips.exp: Run them.
* config/tc-mips.c (mips16_macro): Don't use move_register.
(mips16_ip): Allow macros to use 'p'.
gas/testsuite/
* gas/mips/mips16-macro.s, gas/mips/mips16-macro.d: New test.
* gas/mips/mips.exp: Run it.
gas/
* config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag.
(AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
(aarch64_abi): New variable.
(ilp32_p): Change to be a macro.
(aarch64_opts): Remove the support for option -milp32 and -mlp64.
(struct aarch64_option_abi_value_table): New struct.
(aarch64_abis): New table.
(aarch64_parse_abi): New function.
(aarch64_long_opts): Add entry for -mabi=.
* doc/as.texinfo (Target AArch64 options): Document -mabi.
* doc/c-aarch64.texi: Likewise.
gas/testsuite/
* gas/aarch64/ilp32-basic.d (#as): Update to use -mabi=ilp32
* config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register):
New functions, split out from...
(reg_lookup): ...here. Remove itbl support.
(reglist_lookup): Delete.
(mips_operand_token_type): New enum.
(mips_operand_token): New structure.
(mips_operand_tokens): New variable.
(mips_add_token, mips_parse_base_start, mips_parse_argument_token)
(mips_parse_arguments): New functions.
(md_begin): Initialize mips_operand_tokens.
(mips_arg_info): Add a token field. Remove optional_reg field.
(match_char, match_expression): New functions.
(match_const_int): Use match_expression. Remove "s" argument
and return a boolean result. Remove O_register handling.
(match_regno, match_reg, match_reg_range): New functions.
(match_int_operand, match_mapped_int_operand, match_msb_operand)
(match_reg_operand, match_reg_pair_operand, match_perf_reg_operand)
(match_addiusp_operand, match_clo_clz_dest_operand)
(match_lwm_swm_list_operand, match_entry_exit_operand)
(match_save_restore_list_operand, match_mdmx_imm_reg_operand)
(match_tied_reg_operand): Remove "s" argument and return a boolean
result. Match tokens rather than text. Update calls to
match_const_int. Rely on match_regno to call check_regno.
(match_pcrel_operand, match_pc_operand): Replace "s" argument with
"arg" argument. Return a boolean result.
(parse_float_constant): Replace with...
(match_float_constant): ...this new function.
(match_operand): Remove "s" argument and return a boolean result.
Update calls to subfunctions.
(mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines
rather than string-parsing routines. Update handling of optional
registers for token scheme.
gas/testsuite/
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: Add some more cases.
* gas/mips/micromips-ill.s, gas/mips/micromips-ill.l: New test.
* gas/mips/mips.exp: Run it.
* config/tc-mips.c: Enable functions commented out in previous patch.
(SKIP_SPACE_TABS): Move further up file.
(mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map)
(mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map)
(ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map)
(mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map)
(mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map)
(micromips_imm_b_map, micromips_imm_c_map): Delete.
(mips_lookup_reg_pair): Delete.
(macro): Use report_bad_range and report_bad_field.
(mips_immed, expr_const_in_range): Delete.
(mips_ip): Rewrite main parsing loop to use new functions.
gas/testsuite/
* gas/mips/at-2.l: Remove duplicated $at warnings.
* gas/mips/ext-ill.l, gas/mips/lui-1.l, gas/mips/mips32r2-ill.l,
gas/mips/mips32r2-ill-nofp.l, gas/mips/mips32r2-ill-fp64.l,
gas/mips/mips64r2-ill.l, gas/mips/octeon-ill.l: Update error
messages. Expect negative numbers to be printed as such,
rather than as large unsigned positive numbers.
* mips.h (EF_MIPS_NAN2008): New macro.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Handle
EF_MIPS_NAN2008.
(_bfd_mips_elf_print_private_bfd_data): Likewise.
binutils/
* readelf.c (get_machine_flags): Handle EF_MIPS_NAN2008.
gas/
* config/tc-mips.c (mips_flag_nan2008): New variable.
(options): Add OPTION_NAN enum value.
(md_longopts): Handle it.
(md_parse_option): Likewise.
(s_nan): New function.
(mips_elf_final_processing): Handle EF_MIPS_NAN2008.
(md_show_usage): Add -mnan.
* doc/as.texinfo (Overview): Add -mnan.
* doc/c-mips.texi (MIPS Opts): Document -mnan.
(MIPS NaN Encodings): New node. Document .nan directive.
(MIPS-Dependent): List the new node.
gas/testsuite/
* gas/mips/nan-2008-1.d: New test.
* gas/mips/nan-2008-2.d: New test.
* gas/mips/nan-2008-3.d: New test.
* gas/mips/nan-2008-4.d: New test.
* gas/mips/nan-legacy-1.d: New test.
* gas/mips/nan-legacy-2.d: New test.
* gas/mips/nan-legacy-3.d: New test.
* gas/mips/nan-legacy-4.d: New test.
* gas/mips/nan-legacy-5.d: New test.
* gas/mips/nan-error-1.l: New list test.
* gas/mips/nan-error-2.l: New list test.
* gas/mips/nan-2008-override.s: New test source.
* gas/mips/nan-2008.s: New test source.
* gas/mips/nan-legacy-override.s: New test source.
* gas/mips/nan-legacy.s: New test source.
* gas/mips/nan-error-1.s: New test source.
* gas/mips/nan-error-2.s: New test source.
* gas/mips/mips.exp: Run the new tests.
ld/testsuite/
* ld-mips-elf/nan-2008.d: New test.
* ld-mips-elf/nan-legacy.d: New test.
* ld-mips-elf/nan-mixed-1.d: New test.
* ld-mips-elf/nan-mixed-2.d: New test.
* ld-mips-elf/nan-2008.s: New test source.
* ld-mips-elf/nan-legacy.s: New test source.
* config/tc-mips.c (mips_ip): Unconditionally parse an expression
for 'A' and assume that the constant has been elided if the result
is an O_register.
gas/testsuite/
* gas/mips/la.s, gas/mips/la.d, gas/mips/la-svr4pic.d,
gas/mips/la-xgot.d: Add tests for bracketed addresses.
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
Rename to...
(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
(M_USD_AB): ...these.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
and SD A(B) macros up.
* micromips-opc.c (micromips_opcodes): Likewise.
gas/
* config/tc-mips.c (gprel16_reloc_p): New function.
(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
BFD_RELOC_UNUSED.
(offset_high_part, small_offset_p): New functions.
(nacro): Use them. Remove *_OB and *_DOB cases. For single-
register load and store macros, handle the 16-bit offset case first.
If a 16-bit offset is not suitable for the instruction we're
generating, load it into the temporary register using
ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
M_L_DAB code once the address has been constructed. For double load
and store macros, again handle the 16-bit offset case first.
If the second register cannot be accessed from the same high
part as the first, load it into AT using ADDRESS_ADDI_INSN.
Fix the handling of LD in cases where the first register is the
same as the base. Also handle the case where the offset is
not 16 bits and the second register cannot be accessed from the
same high part as the first. For unaligned loads and stores,
fuse the offbits == 12 and old "ab" handling. Apply this handling
whenever the second offset needs a different high part from the first.
Construct the offset using ADDRESS_ADDI_INSN where possible,
for offbits == 16 as well as offbits == 12. Use offset_reloc
when constructing the individual loads and stores.
(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
and offset_reloc before matching against a particular opcode.
Handle elided 'A' constants. Allow 'A' constants to use
relocation operators.
gas/testsuite/
* gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for
truncated constants.
* gas/mips/ldstla-32-shared.d: Likewise.
* gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding
16-bit constants to the base.
* gas/mips/micromips@mcu.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips.d, gas/mips/micromips-insn32.d,
gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise.
Allow the full 16-bit offset range to be used for SB, LB and LBU in
USH and ULH sequences. Fix the expected output for LD and SD when
the two LW and SW offsets need different high parts.
* gas/mips/eva.s: Test PREFE with relocation operators.
* gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit
constants. Update after eva.s change.
* gas/mips/micromips@eva.d: Likewise.
* gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s,
gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d,
gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s,
gas/mips/ulh-reloc.d: New tests.
* gas/mips/mips.exp: Run them.
* mips.h: Remove documentation of "[" and "]". Update documentation
of "k" and the MDMX formats.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
MDMX-like instructions.
* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
printing "Q" operands for INSN_5400 instructions.
gas/
* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
(mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
gas/testsuite/
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test.
* gas/mips/mips.exp: Run it.
* mips.h: Remove documentation of "+D" and "+T".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
and "+T" handling. Check for a "0" suffix when deciding whether to
use coprocessor 0 names. In that case, also check for ",H" selectors.
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
(mips_ip): Remove "+D" and "+T" handling.
gas/testsuite/
* gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names
for LWC0 and SWC0.
opcodes/
* s390-opc.c (J12_12, J24_24): New macros.
(INSTR_MII_UPI): Rename to INSTR_MII_UPP.
(MASK_MII_UPI): Rename to MASK_MII_UPP.
* s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
include/elf/
* s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL,
R_390_PC24DBL, and R_390_PLT24DBL.
gas/testsuite/
* gas/s390/zarch-zEC12.s: Change bprp second operand and add
variants requiring relocations.
* gas/s390/zarch-zEC12.d: Likewise.
gas/
* config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
relocs.
bfd/
* elf32-s390.c: Add new relocation definitions R_390_PC12DBL,
R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL.
(elf_s390_reloc_type_lookup, elf_s390_check_relocs)
(elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new
relocations.
* elf64-s390.c: See elf32-s390.c
* bfd-in2.h: Add new relocs to enum bfd_reloc_code_real.
* libbfd.h: Add new reloc strings.
* config/tc-arm.c (parse_reg_list): Use skip_past_char for '}',
so it skips whitespace before it.
(s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise.
gas/testsuite/
* gas/arm/macro-vld1.s: Add a case with whitespace before '}'.
* gas/arm/macro-vld1.d: Update.
* gas/mips/mips.exp: Remove "LOSE" comments.
(run_dump_test_arch): Remove format selector support.
(run_dump_test_arches): Remove associated upvars.
(elf, ecoff, aout, no_mips16, no_micromips): Remove variables.
Remove all conditions based on them, on the assumption that $elf
is true and the others are false. Rename "elf-jal" to "jal".
(tmips): Set to "t" for *bsd targets.
* gas/mips/elf-jal.d: Rename to...
* gas/mips/jal.d: ...this, replacing the old file.
* gas/mips/micromips@elf-jal.d: Rename to...
* gas/mips/micromips@jal.d: ...this.
* gas/mips/at-1.d, gas/mips/ld.d, gas/mips/l_d.d, gas/mips/lui.d,
gas/mips/mips1@l_d.d, gas/mips/mips1@ld-forward.d, gas/mips/mips1@ld.d,
gas/mips/mips1@s_d.d, gas/mips/s_d.d, gas/mips/sd.d: Remove ECOFF
relocation names. Do not allow any offset on the symbol.
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
(ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
(ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
(ISA_SUPPORTS_VIRT64_ASE): Delete.
(mips_ase): New structure.
(mips_ases): New table.
(FP64_ASES): New macro.
(mips_ase_groups): New array.
(mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
(mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
functions.
(is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
(md_parse_option): Use mips_ases and mips_set_ase instead of
separate case statements for each ASE option.
(mips_after_parse_args): Use FP64_ASES. Use
mips_check_isa_supports_ases to check the ASEs against
other options.
(s_mipsset): Use mips_ases and mips_set_ase instead of
separate if statements for each ASE option. Use
mips_check_isa_supports_ases, even when a non-ASE option
is specified.
gas/testsuite/
* gas/mips/ase-errors-1.s, gas/mips/ase-errors-1.l,
gas/mips/ase-errors-2.s, gas/mips/ase-errors-2.l,
gas/mips/ase-errors-3.s, gas/mips/ase-errors-3.l,
gas/mips/ase-errors-4.s, gas/mips/ase-errors-4.l: New tests.
* gas/mips/mips.exp: Run them.
gas/
* config/tc-nios2.c (md_apply_fix): Mask constant
BFD_RELOC_NIOS2_HIADJ16 value to 16 bits.
gas/testsuite/
* gas/nios2/movia.s: Add additional test case with negative
constant value.
* gas/nios2/movia.d: Likewise.
* config/tc-mips.c (append_insn): Don't do branch relaxation for
MIPS-3D instructions either.
(md_convert_frag): Update the COPx branch mask accordingly.
* config/tc-mips.c (md_show_usage): Document --[no-]relax-branch
option.
* doc/as.texinfo (Overview): Add --relax-branch and
--no-relax-branch.
* doc/c-mips.texi (MIPS Opts): Document --relax-branch and
--no-relax-branch.
gas/testsuite/
* gas/mips/relax-bc1any.l: New test.
* gas/mips/relax-bc1any.s: New test source.
* gas/mips/mips.exp: Run the new test.
* write.c (resolve_reloc_expr_symbols): On REL targets don't
convert relocs who have no relocatable field either. Rephrase
the conditional so that the PC-relative check is only applied
for REL targets.
gas/testsuite/
* gas/mips/jalr3.d: New test.
* gas/mips/jalr3-n32.d: New test.
* gas/mips/jalr3-n64.d: New test.
* gas/mips/jalr3.s: New test source.
* gas/mips/mips.exp: Run the new tests.
ld/testsuite/
* ld-mips-elf/jalr3.dd: New test.
* ld-mips-elf/jalr3.ld: New test linker script.
* ld-mips-elf/mips-elf.exp: Run the new test.
* config/tc-mips.c (macro) <ld>: Don't use $zero for address
calculation.
gas/testsuite/
* gas/mips/ld-zero.d: New test.
* gas/mips/ld-zero-2.d: New test.
* gas/mips/ld-zero-3.d: New test.
* gas/mips/ld-zero-q.d: New test.
* gas/mips/ld-zero-u.d: New test.
* gas/mips/ecoff@ld-zero-3.d: New test.
* gas/mips/micromips@ld-zero-2.d: New test.
* gas/mips/micromips@ld-zero-3.d: New test.
* gas/mips/ld-zero.s: New test source.
* gas/mips/ld-zero-2.s: New test source.
* gas/mips/ld-zero-3.s: New test source.
* gas/mips/ld-zero-q.s: New test source.
* gas/mips/ld-zero-u.s: New test source.
* gas/mips/mips.exp: Run the new tests.
2013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/tc-aarch64.c (md_apply_fix): Move value range checking
inside fx_done condition.
2013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
* gas/aarch64/adr_1.d: New file.
* gas/aarch64/adr_1.s: New file.
* gas/aarch64/b_1.d: New file.
* gas/aarch64/b_1.s: New file.
* gas/aarch64/beq_1.d: New file.
* gas/aarch64/beq_1.s: New file.
* gas/aarch64/ldr_1.d: New file.
* gas/aarch64/ldr_1.s: New file.
* gas/aarch64/tbz_1.d: New file.
* gas/aarch64/tbz_1.s: New file.
* s390-opc.txt (flogr): Require a register pair destination.
gas/testsuite/
* gas/s390/zarch-z9-109-err.s, gas/s390/zarch-z9-109-err.l: New test.
* gas/s390/s390.exp: Run it.
Add -mcpu command to specify core type.
* doc/c-msp430.c: Update documentation.
* gas/msp430/opcodes.s: Use correct value for .arch pseudo.
* gas/msp430/msp430x.d: Use correct value for -mcpu option.
* doc/binutils.texi: Document -Mvirt disassembler option.
gas/ChangeLog:
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
(mips_opts): Update for the new field.
(file_ase_virt): New variable.
(ISA_SUPPORTS_VIRT_ASE): New macro.
(ISA_SUPPORTS_VIRT64_ASE): New macro.
(MIPS_CPU_ASE_VIRT): New define.
(is_opcode_valid): Handle ase_virt.
(macro_build): Handle "+J".
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
(md_longopts): Add mvirt and mnovirt
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
(mips_after_parse_args): Handle ase_virt field.
(s_mipsset): Handle "virt" and "novirt".
(mips_elf_final_processing): Add a comment about virt ASE might need a new flag.
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
* doc/c-mips.texi: Document -mvirt and -mno-virt.
Document ".set virt" and ".set novirt".
gas/testsuite/ChangeLog:
* gas/mips/mips.exp: Run virt and virt64 testcases.
* gas/mips/virt.d: New file.
* gas/mips/virt.s: New file.
* gas/mips/virt64.d: New file.
* gas/mips/virt64.s: New file.
include/opcode/ChangeLog:
* mips.h (OP_MASK_CODE10): Correct definition.
(OP_SH_CODE10): Likewise.
Add a comment that "+J" is used now for OP_*CODE10.
(INSN_ASE_MASK): Update.
(INSN_VIRT): New macro.
(INSN_VIRT64): New macro
opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 .
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
* config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries.
(s_mips_stab): Do not restrict to stabn only.
gas/testsuite/
* gas/mips/mips16-stabs.s, gas/mips/mips16-stabs.d: New test.
* gas/mips/mips.exp: Run it.
* config.bfd (msp430): Define targ_selvecs.
* configure.in: Add bfd_elf32_msp430_ti_vec.
* cpu-msp430.c: Add some more MSP430 machine numbers.
* elf32-msp430.c Add support for MSP430X relocations.
Add support for TI compiler generated relocations.
Add support for sym_diff relocations.
Add support for relaxing out of range short branches into long
branches.
Add support for MSP430 attribute section.
* reloc.c: Add MSP430X relocations.
* targets.c: Add bfd_elf32_msp430_ti_vec.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* readelf.c: Add support for MSP430X architecture.
* readelf.exp: Expect -wi test to fail for the MSP430.
* config/tc-msp430.c: Add support for the MSP430X architecture.
Add code to insert a NOP instruction after any instruction that
might change the interrupt state.
Add support for the LARGE memory model.
Add code to initialise the .MSP430.attributes section.
* config/tc-msp430.h: Add support for the MSP430X architecture.
* doc/c-msp430.texi: Document the new -mL and -mN command line
options.
* NEWS: Mention support for the MSP430X architecture.
* gas/all/gas.exp: Skip the DIFF1 test for the MSP430.
Expect the FORWARD test to pass for the MSP430.
Skip the REDEF tests for the MSP430.
Expect the 930509A test to fail for the MSP430.
* gas/all/sleb128-4.d: Skip for the MSP430.
* gas/elf/elf.exp: Set target_machine to msp430 for the MSP430.
Skip the EHOPT0 test for the MSP430.
Skip the REDEF and EQU-RELOC tests for the MSP430.
* gas/elf/section2.e-msp430: New file.
* gas/lns/lns-big-delta.d: Remove expectation of 20-bit
addresses.
* gas/lns/lns.exp: Use alternate LNS COMMON test for the MSP430.
* gas/msp430/msp430x.s: New test.
* gas/msp430/msp430x.d: Expected disassembly.
* gas/msp430/msp430.exp: Run new test.
* gas/msp430/opcode.d: Update expected disassembly.
* msp430.h: Add MSP430X relocs.
Add some more MSP430 machine numbers.
Add values used by .MSP430.attributes section.
* msp430.h: Add patterns for MSP430X instructions.
* Makefile.am: Add emsp430X.c
* Makefine.in: Regenerate.
* configure.tgt (msp430): Add msp430X emulation.
* ldmain.c (multiple_definition): Only disable relaxation if it
was enabled by the user.
* ldmain.h (RELAXATION_ENABLED_BY_USER): New macro.
* emulparams/msp430all.sh: Add support for MSP430X.
* emultempl/generic.em: (before_parse): Enable relaxation for the
MSP430.
* scripttempl/msp430.sc: Reorganize sections. Add .rodata
section.
* scripttempl/msp430_3.sc: Likewise.
* NEWS: Mention support for MSP430X.
* ld-elf/flags1.d: Expect this test to pass on the MSP430.
* ld-elf/init-fini-arrays.d: Expect this test to fail on the
MSP430.
* ld-elf/merge.d: Expect this test to pass on the MSP430.
* ld-elf/sec64k.exp: Skip these tests for the MSP430.
* ld-gc/pr13683.d: Expect this test to fail on the MSP430.
* ld-srec/srec.exp: Expect these tests to fail on the MSP430.
* ld-undefined/undefined.exp: Expect the UNDEFINED LINE test to
fail on the MSP430.
* msp430-dis.c: Add support for MSP430X instructions.
This patch enables x32 for x86_64-*-elf* for embedded target and disables
rex tests since it uses '/' as prefix separator which is `\' for
x86_64-*-elf*.
bfd/
* config.bfd (targ_selvecs): Add bfd_elf32_x86_64_vec for
x86_64-*-elf*.
gas/testsuite/
* gas/i386/rex.d: Skip x86_64-*-elf*.
* gas/i386/ilp32/rex.d: Likewise.
ld/
* configure.tgt (targ_extra_emuls): Adds elf32_x86_64 for
x86_64-*-elf*.
(targ_extra_libpath): Likewise.
(tdir_elf_i386): Replace x86_64 with i386 for x86_64-*-elf*.
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base
register being PC when is_t or writeback, and use distinct
diagnostic for the latter case.
gas/testsuite/
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/testsuite/gas/arm/ldst-pc.s: Add index, non-writeback
forms of various loads and stores with PC as base.
* gas/testsuite/gas/arm/ldst-pc.d: Update accordingly.
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (parse_operands): Re-write
po_barrier_or_imm().
(do_barrier): Remove bogus constraint().
(do_t_barrier): Remove.
gas/testsuite/
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/arm/barrier-bad.d: Change title.
* gas/arm/barrier-bad.s: Add immediate form of ISB and DSB as
well as one symbolic form of DSB.
* gas/arm/barrier-bad.l: Update accordingly.
* gas/arm/barrier-bad-thumb.d: Adjust title. Use barrier-bad.s as
source. Pass -mthumb to gas.
* gas/arm/barrier-bad-thumb.l: Remove.
* gas/arm/barrier-bad-thumb.s: Remove.
* gas/arm/barrier-thumb.d: Adjust title. Use barrier.s as source.
Pass -mthumb to gas.
* gas/arm/barrier-thumb.s: Remove.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_vmrs): Accept all control registers.
Use local variable Rt in more places.
(do_vmsr): Accept all control registers.
gas/testsuite/
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/vfp1xD.s: Add VMRS/VMSR tests with FPINST, FPINST2,
and C15.
* gas/arm/vfp1xD.d: Update accordingly.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
if there was none specified for moves between scalar and core
register.
gas/testsuite/
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-omit.s: Add tests for suffix less VMOV.
* gas/arm/neon-omit.d: Update accordingly.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the
NEON_ALL_LANES case.
gas/testsuite/
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-addressing-bad.s: Add test for further invalid VST
operands.
* gas/arm/neon-addressing-bad.l: Update accordingly.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
* gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add
and xor.
* gas/tic6x/insns16-lsd-unit.d: Update expected output.
2013-03-26 Douglas B Rupp <rupp@gnat.com>
* config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment
after fixup.
gas/testsuite/
2013-03-26 Douglas B Rupp <rupp@adacore.com
* gas/ia64/ia64.exp: Add new test reloc-mlx
* gas/ia64/reloc-mlx.[sd]: New test for X-unit reloc.
* gas/ia64/pcrel.d: Fix output for X-unit reloc.
2013-03-21 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all
pc-relative str instructions in Thumb mode.
gas/testsuite/ChangeLog:
2013-03-21 Will Newton <will.newton@linaro.org>
* gas/arm/thumb2_relax.d: Strip out invalid pc-relative strs.
* gas/arm/thumb2_relax.s: Likewise.
* gas/arm/thumb32.d: Likewise.
* gas/arm/thumb32.l: Likewise.
* gas/arm/thumb32.s: Likewise.
* gas/arm/thumb2_str-bad.d: New file.
* gas/arm/thumb2_str-bad.l: Likewise.
* gas/arm/thumb2_str-bad.s: Likewise.
* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
tic6x_operand_xregpair operand coding type.
Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
opcode field, usu ORXREGD1324 for the src2 operand and remove the
TIC6X_FLAG_NO_CROSS.
* gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with
cross-path.
* gas/tic6x/insns-bad-1.l: Update expected output.
* gas/tic6x/insns-c674x.s: Add a test-case for mpydp with
cross-path.
* gas/tic6x/insns-c674x.d: Update expected output.
order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.
* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types
and use it to encode register pair numbers when required.
* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.
* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.
* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.
2013-03-12 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_neon_ldr_str): Fix error check for PC register
in vstr in Thumb mode for pre-ARMv7 cores.
gas/testsuite/ChangeLog:
2013-03-12 Will Newton <will.newton@linaro.org>
* gas/arm/vstr-thumb-bad.d: Assemble with -mcpu=arm1156t2f-s.
opcodes/
* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
gas/testsuite/
* gas/nios2/nios2.exp: Run registers.
* gas/nios2/registers.d: New file.
* gas/nios2/registers.s: Likewise.
* config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
for system registers.
gas/testsuite/
* gas/aarch64/illegal.l: Delete the error message for
msr S3_1_C13_C15_1,x7.
* gas/aarch64/sysreg.s: Add new tests.
* gas/aarch64/sysreg.d: Update.
which also makes the disassembler output be in little
endian like it should be.
* metag/labelarithmetic.d: Fix the expected disassembler
output to be in little endian format
* metag/metacore12.d: likewise
* metag/metacore21.d: likewise
* metag/metacore21ext.d: likewise
* metag/metadsp21.d: likewise
* metag/metadsp21ext.d: likewise
* metag/metafpu.d: likewise
* metag/metafpuext.d: likewise
* metag/tls.d: likewise
* ld-metag/pcrel.d: Fix the expected disassembler
output to be in little endian format
* ld-metag/shared.d: likewise
* ld-metag/stub.d: likewise
* ld-metag/stub_pic_app.d: likewise
* ld-metag/stub_pic_shared.d: likewise
* ld-metag/stub_shared.d: likewise
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
(macro): Use it. Assert that trunc.w.s is not used for r5900.
opcodes/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
single-float. Disable ll, lld, sc and scd for EE. Disable the
trunc.w.s macro for EE.
gas/testsuite/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/24k-triple-stores-2.d, gas/mips/24k-triple-stores-2.s,
gas/mips/micromips@24k-triple-stores-2.d: Move "sc" tests to...
* gas/mips/24k-triple-stores-2-llsc.d,
gas/mips/24k-triple-stores-2-llsc.s,
gas/mips/micromips@24k-triple-stores-2-llsc.d: ...these new tests.
* gas/mips/r5900-full.d, gas/mips/r5900-full.s: Verify that the
MIPS ISA level can be upgraded to support ll, sc, lld and scd.
* gas/mips/l_d-single.d, gas/mips/s_d-single.d,
gas/mips/r5900-nollsc.l, gas/mips/r5900-nollsc.s: New tests.
* gas/mips/mips.exp: Update accordingly. Add "nollsc" to r5900
properties.
* tic6x-opcode-table.h: Fix encoding of BNOP instruction.
* gas/tic6x/insns-c674x-pcrel.s: Add test of BNOP instruction
within header based fetch packet.
* gas/tic6x/insns-c674x-pcrel.d: Update expected disassembly.
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
opcodes/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): For
AARCH64_MOD_LSL, move the range check on the shift amount before the
alignment check; change to call set_sft_amount_out_of_range_error
instead of set_imm_out_of_range_error.
* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
SIMD_IMM_SFT.
gas/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (output_operand_error_record): Change to output
the out-of-range error message as value-expected message if there is
only one single value in the expected range.
(programmer_friendly_fixup): Remove the handling of 8-bit MOVI with
LSL #0 as a programmer-friendly feature.
gas/testsuite/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/movi.s: Add tests.
* gas/aarch64/movi.d: Update.
* gas/aarch64/programmer-friendly.s: Add comment.
