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gas/config/tc-arm.c: Improve validation of NEON addressing modes.

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NEON vector load and store instructions do not accept immediates
or pre-indexed base plus offset addressing modes, so make sure that
the assembler enforces this.

gas/ChangeLog:

2013-08-23  Will Newton  <will.newton@linaro.org>

	* config/tc-arm.c (do_neon_ldx_stx): Add extra constraints
	for pre-indexed addressing modes.
	* testsuite/gas/arm/neon-addressing-bad.l: Add test for
	VLDn and VSTn instructions.
	* testsuite/gas/arm/neon-addressing-bad.s: Likewise.

gas/testsuite/ChangeLog:

2013-08-23  Will Newton  <will.newton@linaro.org>

	* testsuite/gas/arm/neon-addressing-bad.l: Add test for
	VLDn and VSTn instructions.
	* testsuite/gas/arm/neon-addressing-bad.s: Likewise.
This commit is contained in:
Will Newton 2013-08-23 07:16:56 +00:00
parent 1ed3ee940d
commit 4f2374c7fa
5 changed files with 41 additions and 14 deletions
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5
gas/ChangeLog
View file

@ -1,3 +1,8 @@
2013-08-23 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_neon_ldx_stx): Add extra constraints
for pre-indexed addressing modes.
2013-08-21 Alan Modra <amodra@gmail.com>
* symbols.c (fb_label_instance_inc, fb_label_instance): Properly

18
gas/config/tc-arm.c
View file

@ -16008,12 +16008,20 @@ do_neon_ldx_stx (void)
_("bad register for post-index"));
inst.instruction |= postreg;
}
else if (inst.operands[1].writeback)
{
inst.instruction |= 0xd;
}
else
inst.instruction |= 0xf;
{
constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
constraint (inst.reloc.exp.X_op != O_constant
|| inst.reloc.exp.X_add_number != 0,
BAD_ADDR_MODE);
if (inst.operands[1].writeback)
{
inst.instruction |= 0xd;
}
else
inst.instruction |= 0xf;
}
if (thumb_mode)
inst.instruction |= 0xf9000000;

6
gas/testsuite/ChangeLog
View file

@ -1,3 +1,9 @@
2013-08-23 Will Newton <will.newton@linaro.org>
* testsuite/gas/arm/neon-addressing-bad.l: Add test for
VLDn and VSTn instructions.
* testsuite/gas/arm/neon-addressing-bad.s: Likewise.
2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/ase-errors-1.l, gas/mips/ase-errors-2.l,

22
gas/testsuite/gas/arm/neon-addressing-bad.l
View file

@ -12,12 +12,16 @@
[^:]*:14: Error: only loads support such operands -- `vst2.8 {D0\[\].*
[^:]*:15: Error: only loads support such operands -- `vst3.16 {D0\[\].*
[^:]*:16: Error: only loads support such operands -- `vst4.32 {D0\[\].*
[^:]*:18: Error: r15 not allowed here -- `vld1.8 {d0},2f'
[^:]*:20: Error: r15 not allowed here -- `vld1.8 {D0},R0'
[^:]*:21: Error: r15 not allowed here -- `vld1.8 {Q1},R0'
[^:]*:22: Error: r15 not allowed here -- `vld1.8 {D0},\[PC\]'
[^:]*:23: Error: r15 not allowed here -- `vld1.8 {D0},\[PC,#0\]'
[^:]*:24: Error: r15 not allowed here -- `vst1.8 {D0},R0'
[^:]*:25: Error: r15 not allowed here -- `vst1.8 {Q1},R0'
[^:]*:26: Error: r15 not allowed here -- `vst1.8 {D0},\[PC\]'
[^:]*:27: Error: r15 not allowed here -- `vst1.8 {D0},\[PC,#0\]'
[^:]*:17: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,#8\]'
[^:]*:18: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,#8\]!'
[^:]*:19: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,R1\]'
[^:]*:20: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,R1\]!'
[^:]*:22: Error: r15 not allowed here -- `vld1.8 {d0},2f'
[^:]*:24: Error: r15 not allowed here -- `vld1.8 {D0},R0'
[^:]*:25: Error: r15 not allowed here -- `vld1.8 {Q1},R0'
[^:]*:26: Error: r15 not allowed here -- `vld1.8 {D0},\[PC\]'
[^:]*:27: Error: r15 not allowed here -- `vld1.8 {D0},\[PC,#0\]'
[^:]*:28: Error: r15 not allowed here -- `vst1.8 {D0},R0'
[^:]*:29: Error: r15 not allowed here -- `vst1.8 {Q1},R0'
[^:]*:30: Error: r15 not allowed here -- `vst1.8 {D0},\[PC\]'
[^:]*:31: Error: r15 not allowed here -- `vst1.8 {D0},\[PC,#0\]'

4
gas/testsuite/gas/arm/neon-addressing-bad.s
View file

@ -14,6 +14,10 @@ VST1.8 {D0[]}, [R0]
VST2.8 {D0[], D2[]}, [R0]
VST3.16 {D0[], D1[], D2[]}, [R0]
VST4.32 {D0[], D1[], D2[], D3[]}, [R0]
VLD1.8 {Q0}, [R0, #8]
VLD1.8 {Q0}, [R0, #8]!
VLD1.8 {Q0}, [R0, R1]
VLD1.8 {Q0}, [R0, R1]!
.thumb
VLD1.8 {d0}, 2f
2: