gas/
* config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn for system registers. gas/testsuite/ * gas/aarch64/illegal.l: Delete the error message for msr S3_1_C13_C15_1,x7. * gas/aarch64/sysreg.s: Add new tests. * gas/aarch64/sysreg.d: Update.
This commit is contained in:
parent
589bc9275a
commit
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6 changed files with 26 additions and 4 deletions
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@ -1,3 +1,8 @@
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2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
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* config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
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for system registers.
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2013-02-27 DJ Delorie <dj@redhat.com>
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* config/tc-rl78.c (reloc_function): Add %code -> BFD_RELOC_RL78_CODE.
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@ -3197,10 +3197,14 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
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unsigned int op0, op1, cn, cm, op2;
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if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
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return PARSE_FAIL;
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/* Register access is encoded as follows:
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/* The architecture specifies the encoding space for implementation
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defined registers as:
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op0 op1 CRn CRm op2
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11 xxx 1x11 xxxx xxx. */
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if (op0 != 3 || op1 > 7 || (cn | 0x4) != 0xf || cm > 15 || op2 > 7)
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11 xxx 1x11 xxxx xxx
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For convenience GAS accepts a wider encoding space, as follows:
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op0 op1 CRn CRm op2
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11 xxx xxxx xxxx xxx */
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if (op0 != 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
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return PARSE_FAIL;
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value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
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}
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@ -1,3 +1,10 @@
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2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
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* gas/aarch64/illegal.l: Delete the error message for
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msr S3_1_C13_C15_1,x7.
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* gas/aarch64/sysreg.s: Add new tests.
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* gas/aarch64/sysreg.d: Update.
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2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/15159
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@ -520,7 +520,6 @@
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[^:]*:496: Error: .*`str x1,page_table_count'
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[^:]*:498: Error: .*`prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
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[^:]*:500: Error: .*`mrs x5,S1_0_C13_C8_0'
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[^:]*:501: Error: .*`msr S3_1_C13_C15_1,x7'
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[^:]*:502: Error: .*`msr S3_1_C11_C15_-1,x7'
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[^:]*:503: Error: .*`msr S3_1_11_15_1,x7'
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[^:]*:506: Error: .*`movi w1,#15'
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@ -23,3 +23,6 @@ Disassembly of section \.text:
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3c: d5380260 mrs x0, id_isar3_el1
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40: d5380280 mrs x0, id_isar4_el1
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44: d53802a0 mrs x0, id_isar5_el1
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48: d538cc00 mrs x0, s3_0_c12_c12_0
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4c: d5384600 mrs x0, s3_0_c4_c6_0
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50: d5184600 msr s3_0_c4_c6_0, x0
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@ -22,3 +22,7 @@
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mrs x0, id_isar3_el1
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mrs x0, id_isar4_el1
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mrs x0, id_isar5_el1
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mrs x0, s3_0_c12_c12_0
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mrs x0, s3_0_c4_c6_0
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msr s3_0_c4_c6_0, x0
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