gas/
2013-04-09 Jan Beulich <jbeulich@suse.com> * gas/config/tc-arm.c (do_vmrs): Accept all control registers. Use local variable Rt in more places. (do_vmsr): Accept all control registers. gas/testsuite/ 2013-04-09 Jan Beulich <jbeulich@suse.com> * gas/arm/vfp1xD.s: Add VMRS/VMSR tests with FPINST, FPINST2, and C15. * gas/arm/vfp1xD.d: Update accordingly.
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05ac0ffbb5
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16d02dc907
5 changed files with 40 additions and 34 deletions
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@ -1,3 +1,9 @@
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2013-04-09 Jan Beulich <jbeulich@suse.com>
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* gas/config/tc-arm.c (do_vmrs): Accept all control registers.
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Use local variable Rt in more places.
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(do_vmsr): Accept all control registers.
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2013-04-09 Jan Beulich <jbeulich@suse.com>
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* gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
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@ -8256,32 +8256,22 @@ do_vmrs (void)
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{
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unsigned Rt = inst.operands[0].reg;
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if (thumb_mode && inst.operands[0].reg == REG_SP)
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if (thumb_mode && Rt == REG_SP)
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{
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inst.error = BAD_SP;
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return;
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}
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/* APSR_ sets isvec. All other refs to PC are illegal. */
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if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
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if (!inst.operands[0].isvec && Rt == REG_PC)
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{
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inst.error = BAD_PC;
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return;
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}
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switch (inst.operands[1].reg)
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{
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case 0: /* FPSID */
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case 1: /* FPSCR */
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case 6: /* MVFR1 */
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case 7: /* MVFR0 */
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case 8: /* FPEXC */
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inst.instruction |= (inst.operands[1].reg << 16);
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break;
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default:
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first_error (_("operand 1 must be a VFP extension System Register"));
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}
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/* If we get through parsing the register name, we just insert the number
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generated into the instruction without further validation. */
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inst.instruction |= (inst.operands[1].reg << 16);
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inst.instruction |= (Rt << 12);
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}
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@ -8298,17 +8288,9 @@ do_vmsr (void)
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return;
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}
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switch (inst.operands[0].reg)
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{
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case 0: /* FPSID */
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case 1: /* FPSCR */
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case 8: /* FPEXC */
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inst.instruction |= (inst.operands[0].reg << 16);
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break;
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default:
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first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
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}
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/* If we get through parsing the register name, we just insert the number
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generated into the instruction without further validation. */
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inst.instruction |= (inst.operands[0].reg << 16);
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inst.instruction |= (Rt << 12);
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}
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@ -1,3 +1,9 @@
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2013-04-09 Jan Beulich <jbeulich@suse.com>
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* gas/arm/vfp1xD.s: Add VMRS/VMSR tests with FPINST, FPINST2,
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and C15.
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* gas/arm/vfp1xD.d: Update accordingly.
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2013-04-09 Jan Beulich <jbeulich@suse.com>
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* gas/arm/neon-omit.s: Add tests for suffix less VMOV.
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@ -280,10 +280,16 @@ Disassembly of section .text:
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0+438 <[^>]*> eee1ea10 vmsr fpscr, lr
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0+43c <[^>]*> eee01a10 vmsr fpsid, r1
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0+440 <[^>]*> eee82a10 vmsr fpexc, r2
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0+444 <[^>]*> eef03a10 vmrs r3, fpsid
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0+448 <[^>]*> eef64a10 vmrs r4, mvfr1
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0+44c <[^>]*> eef75a10 vmrs r5, mvfr0
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0+450 <[^>]*> eef86a10 vmrs r6, fpexc
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0+454 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+458 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+45c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+444 <[^>]*> eee93a10 vmsr fpinst, r3 @ Impl def
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0+448 <[^>]*> eeea4a10 vmsr fpinst2, r4 @ Impl def
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0+44c <[^>]*> eeef5a10 vmsr (c15|<impl def 0xf>), r5
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0+450 <[^>]*> eef03a10 vmrs r3, fpsid
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0+454 <[^>]*> eef64a10 vmrs r4, mvfr1
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0+458 <[^>]*> eef75a10 vmrs r5, mvfr0
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0+45c <[^>]*> eef86a10 vmrs r6, fpexc
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0+460 <[^>]*> eef97a10 vmrs r7, fpinst @ Impl def
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0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 @ Impl def
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0+468 <[^>]*> eeff9a10 vmrs r9, (c15|<impl def 0xf>)
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0+46c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+470 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+474 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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@ -381,13 +381,19 @@ F:
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vmsr FPSCR, r12
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vmsr FPSCR, r14
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@ Priviledged externsions to VMSR/VMRS instructions
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@ Priviledged extensions to VMSR/VMRS instructions
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vmsr FPSID, r1
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vmsr FPEXC, r2
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vmsr FPINST, r3
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vmsr FPINST2, r4
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vmsr C15, r5
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vmrs r3, FPSID
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vmrs r4, MVFR1
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vmrs r5, MVFR0
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vmrs r6, FPEXC
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vmrs r7, FPINST
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vmrs r8, FPINST2
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vmrs r9, C15
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nop
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nop
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