into single PKE-style vu.[ch].
[ChangeLog]
Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
start-sanitize-sky
* Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
* interp.c (sim_{load,store}_register): Use new vu[01]_device
static to access VU registers.
(decode_coproc): Added skeleton of sky COP2 (VU) instruction
decoding. Work in progress.
* mips.igen (LDCzz, SDCzz): Removed *5900 case for this
overlapping/redundant bit pattern.
(LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
progress.
* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
status register.
end-sanitize-sky
* interp.c (cop_lq, cop_sq): New functions for future 128-bit
access to coprocessor registers.
* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
[ChangeLog.sky]
* sky-engine.c (engine_run): Adapted from vu[01] -> vu merge.
* sky-hardware.c (register_devices): Ditto
* sky-pke.c (pke_fifo_*): Made these functions private again, now
that the GPUIF code does not use them.
* sky-pke.h (pke_fifo_*): Removed newly private declarations.
* sky-vu.c (*): Major rework: merge of old sky-vu0.c and
sky-vu1.c. Management of two VU devices parallels two PKEs.
Work in progress.
* sky-vu.h (*): Other half of merge.
(vu_device): New struct, parallel to pke_device.
for sim/testsuite/sky:
* t-pke4.run: Removed test, since it succeeds yet returns a
non-zero exit code.
* Makefile.in (RUNOPTS): Removed --memory-size flag, made
unnecessary by sim/mips/interp.c changes.
(TESTS): Removed t-pke4.ok target.
* t-pke3.trc: Classified tests with [---] indicators, to match
items up with entries documented in testplan.sgml. Added numerous
additional tests. They assert behavior that assumes certain
favorable answers to PKE question set #6 to SCEI.
* t-pke1.trc: Added some [---] indicators.
for sim/mips:
* sky-pke.c (pke_issue): Revamped interrupt & stall code. Assume
that ER1/ER0/PIS bits are only set if not masked by ERR bits.
Signal PIS only if unmasked.
(pke_code_error): Signal ER1 only if unmasked.
(pke_pc_fifo): Signal ER0 only if unmasked.
(pke_code_unpack): Round up num_operands for last operand's
partial-word. Factor out "R" bit handling for better coverage
analysis. Fill upper words of a quadword with zeroes for Vn_m
UNPACK with n < 4.
* sky-device.c (device_error): Made function accept varargs.
* sky-device.h (device_error): Changed declaration to match.
* interp.c (sim_open): Made 0x0000 area memory be an alias of
the K0/K1 segments. Sanitized code.
little struct.
interp.c: Update. Also add floating point Max/Min functions.
mips.igen: Remove r5900 tag from any floating point instructions.
r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st).
r5400.igen: Tag mdmx functions as being mdmx specific.
update v850, tic80 and mips simulators.
IGEN - Prepend prefix to more generated symbols and macros
(idecode_issue, instruction_word).
IGEN - Add -Wnowith option to supress warnings about word size
inflicts in input files.
MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so
that a mips16 simulator built using IGEN can be compiled.
Use the bfd-processor name in the sim-engine switch.
Add nr_cpus argument to sim_engine_run.
tic80, v850, d30v, mips, common:
Update
mips: Fill in bfd-processor field of model records so that
they match ../bfd/archures.
MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
calls) and sim_open so that they uses the virtual memory data transfer
functions sim_read & sim_write. This eliminates all code (other than
in load_memory & store_memory) that makes assumptions about the
implementation of the underlying memory model.
When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
Add file sim-hload.c - generic load for hardware only simulators.
Review each simulators sim_open, sim_load, sim_create_inferior so that
they more closely match required behavour.
that image properties such as endianness can be checked.
More strongly document the expected behavour of each of the sim_*
interfaces.
Add default endian argument to simulator config macro
SIM_AC_OPTION_ENDIAN. Use in sim_config.
* interp.c: #include bfd.h.
(target_byte_order): Delete.
(sim_kind, myname, big_endian_p): New static locals.
(sim_open): Set sim_kind, myname. Move call to set_endianness to
after argument parsing. Recognize -E arg, set endianness accordingly.
(sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
load file into simulator. Set PC from bfd.
(sim_create_inferior): Return SIM_RC. Delete arg start_address.
(set_endianness): Use big_endian_p instead of target_byte_order.
(SignalException): Pass floating point cases to mips16_entry.
(ValueFPR): Don't restrict fmt_single and fmt_word to even
registers.
(StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
or fmt_word.
(COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
and then set the state to fmt_uninterpreted.
(COP_SW): Temporarily set the state to fmt_word while calling
ValueFPR.
(mips16_entry): New static function.
(SignalException): Look for mips16 entry and exit instructions.
(simulate): Use the correct index when setting fpr_state after
doing a pending move.
relative operands.
(build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
jal instruction.
* interp.c (simJALDELAYSLOT): Define.
(JALDELAYSLOT): Define.
(INDELAYSLOT, INJALDELAYSLOT): Define.
(simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
* gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
* interp.c (CHECKHILO): Define away.
(simSIGINT): New macro.
(membank_size): Increase from 1MB to 2MB.
(control_c): New function.
(sim_resume): Rename parameter signal to signal_number. Add local
variable prev. Call signal before and after simulate.
(sim_stop_reason): Add simSIGINT support.
(sim_warning, sim_error, dotrace, SignalException): Define as stdarg
functions always.
(sim_warning): Delete call to SignalException. Do call printf_filtered
if logfh is NULL.
(AddressTranslation): Add #ifdef DEBUG around debugging message and
a call to sim_warning.
* interp.c (sim_monitor): Improved monitor printf
simulation. Tidied up simulator warnings, and added "--log" option
for directing warning message output.
* gencode.c: Use sim_warning() rather than WARNING macro.
AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
stamp-h.
* configure: Rebuild.
* config.in: New file, generated by autoheader.
* interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
and <strings.h> if they exist. Replace #ifdef sun with #ifdef
HAVE_ANINT and HAVE_AINT, as appropriate.
* Makefile.in (run): Use @LIBS@ rather than -lm.
(interp.o): Depend upon config.h.
(Makefile): Just rebuild Makefile.
(clean): Remove stamp-h.
(mostlyclean): Make the same as clean, not as distclean.
(config.h, stamp-h): New targets.
* interp.c (xfer_direct_word, xfer_direct_long,
swap_direct_word, swap_direct_long, xfer_big_word,
xfer_big_long, xfer_little_word, xfer_little_long,
swap_word,swap_long): Added.
* interp.c (ColdReset): Provide function indirection to
host<->simulated_target transfer routines.
* interp.c (sim_store_register, sim_fetch_register): Updated to
make use of indirected transfer routines.
* interp.c (Convert): Provide round-to-nearest and round-to-zero
support for Sun hosts.
* Makefile.in (gencode): Ensure the host compiler and libraries
used for cross-hosted build.
Allow a DOS hosted version of the simulator to be built. NOTE: The FP
is still not complete, since round-to-nearest and round-to-zero have
not been implemented generically.
support.
* interp.c: Added dineroIII, and BSD profiling support. Also
run-time FP handling.
At the moment the options are still mostly build-time controlled,
rather than run-time. Also work still needs to be done to remove (long
long) usage (However this is trivial, just time-consuming).
The out-standing instruction work to be done is in supporting round
and trunc for FP operations, and providing better exception support.
