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* interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.

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It's OK to have a mult follow a mult.  What's not OK is to have a
	mult follow an mfhi.
This commit is contained in:
Ian Lance Taylor 1996-09-19 22:52:26 +00:00
parent 47c6ce6c2d
commit c05d17211e
2 changed files with 4 additions and 4 deletions
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4
sim/mips/ChangeLog
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@ -1,5 +1,9 @@
Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
* interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
It's OK to have a mult follow a mult. What's not OK is to have a
mult follow an mfhi.
* gencode.c (process_instructions): Correct handling of nor
instruction. Correct shift count for 32 bit shift instructions.
Correct sign extension for arithmetic shifts to not shift the

4
sim/mips/interp.c
View file

@ -361,10 +361,6 @@ static ut_reg HLPC = 0;
#define CHECKHILO(s) {\
if ((HIACCESS != 0) || (LOACCESS != 0))\
sim_warning("%s over-writing HI and LO registers values (PC = 0x%08X%08X HLPC = 0x%08X%08X)\n",(s),(unsigned int)(PC>>32),(unsigned int)(PC&0xFFFFFFFF),(unsigned int)(HLPC>>32),(unsigned int)(HLPC&0xFFFFFFFF));\
/* Set the access counts, since we are about\
to update the HI and LO registers: */\
HIACCESS = LOACCESS = 3; /* 3rd instruction will be safe */\
HLPC = PC;\
}
/* NOTE: We keep the following status flags as bit values (1 for true,