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Author SHA1 Message Date
Alan Modra
92007e403c * a29k.h: Replace CONST with const. 
(CONST): Don't define.
	* convex.h: Replace CONST with const.
	(CONST): Don't define.
	* dlx.h: Replace CONST with const.
	* or32.h (CONST): Don't define.
 2002-06-08 07:32:12 +00:00
Chris Demetriou
deec17343c [ gas/ChangeLog ] 
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

	* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
	(mips_opts): Initialize "ase_mdmx" member.
	(file_ase_mdmx): New variable.
	(CPU_HAS_MDMX): New macro.
	(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
	based on command line options and configuration defaults.
	(macro_build): Note in comment that use of MDMX in macros is
	not currently allowed.
	(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
	"Z" MDMX operand types.
	(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
	and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
	types.
	(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
	Add support for "-mdmx" and "-no-mdmx" options.
	(OPTION_ELF_BASE): Move to accomodate new options.
	(s_mipsset): Support ".set mdmx" and ".set nomdmx".
	(mips_elf_final_processing): Set MDMX ASE ELF header flag if
	file_ase_mdmx was set.
	* doc/as.texinfo: Document -mdmx and -no-mdmx options.
	* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
	nomdmx" directives.

[ gas/testsuite/ChangeLog ]
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>

	* gas/mips/mips64-mdmx.s: New file.
	* gas/mips/mips64-mdmx.d: Likewise.
	* gas/mips/mips.exp: Run new "mips64-mdmx" test.

[ include/opcode/ChangeLog ]
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>

	* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
	(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
	(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
	(INSN_MDMX): New constants, for MDMX support.
	(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.

[ opcodes/ChangeLog ]
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

	* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
	and 'Z' formats, for MDMX.
        (mips_isa_type): Add MDMX instructions to the ISA
	bit mask for bfd_mach_mipsisa64.
	* mips-opc.c: Add support for MDMX instructions.
	(MX): New definition.

	* mips-dis.c: Update copyright years to include 2002.
 2002-05-31 01:17:18 +00:00
Nick Clifton
d172d4ba03 Add DLX target 2002-05-28 14:08:47 +00:00
Alan Modra
b3f7d5fdb0 * ia64.h: Use #include "" instead of <> for local header files. 
* sparc.h: Likewise.
 2002-05-25 12:53:48 +00:00
Thiemo Seufer
771c7ce4bc ? gas/testsuite/gas/mips/rol64.d 
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog	21 May 2002 20:01:51 -0000	1.1334
+++ gas/ChangeLog	21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+	Optimize the rotate by zero case.
+
 2002-05-21  Nick Clifton  <nickc@cambridge.redhat.com>

 	* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c	14 May 2002 23:35:59 -0000	1.123
+++ gas/config/tc-mips.c	21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
       --mips_opts.noreorder;
       break;

+    case M_DROL:
+      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+		   "d,v,t", AT, 0, treg);
+      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+		   "d,t,s", AT, sreg, AT);
+      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+		   "d,t,s", dreg, sreg, treg);
+      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+		   "d,v,t", dreg, dreg, AT);
+      break;
+
     case M_ROL:
       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
 		   "d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
 		   "d,v,t", dreg, dreg, AT);
       break;

+    case M_DROL_I:
+      {
+	unsigned int rot;
+	char *l, *r;
+
+	if (imm_expr.X_op != O_constant)
+	  as_bad (_("rotate count too large"));
+	rot = imm_expr.X_add_number & 0x3f;
+	if (! rot)
+	  break;
+	l = (rot < 0x20) ? "dsll" : "dsll32";
+	r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+	rot &= 0x1f;
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+		     "d,w,<", AT, sreg, rot);
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+		     "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+		     "d,v,t", dreg, dreg, AT);
+      }
+      break;
+
     case M_ROL_I:
-      if (imm_expr.X_op != O_constant)
-	as_bad (_("rotate count too large"));
-      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
-		   AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
-      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
-		   dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
-      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
-		   dreg, dreg, AT);
+      {
+	unsigned int rot;
+
+	if (imm_expr.X_op != O_constant)
+	  as_bad (_("rotate count too large"));
+	rot = imm_expr.X_add_number & 0x1f;
+	if (! rot)
+	  break;
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+		     "d,w,<", AT, sreg, rot);
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+		     "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+		     "d,v,t", dreg, dreg, AT);
+      }
+      break;
+
+    case M_DROR:
+      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+		   "d,v,t", AT, 0, treg);
+      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+		   "d,t,s", AT, sreg, AT);
+      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+		   "d,t,s", dreg, sreg, treg);
+      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+		   "d,v,t", dreg, dreg, AT);
       break;

     case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
 		   "d,v,t", dreg, dreg, AT);
       break;

+    case M_DROR_I:
+      {
+	unsigned int rot;
+	char *l, *r;
+
+	if (imm_expr.X_op != O_constant)
+	  as_bad (_("rotate count too large"));
+	rot = imm_expr.X_add_number & 0x3f;
+	if (! rot)
+	  break;
+	r = (rot < 0x20) ? "dsrl" : "dsrl32";
+	l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+	rot &= 0x1f;
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+		     "d,w,<", AT, sreg, rot);
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+		     "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+		     "d,v,t", dreg, dreg, AT);
+      }
+      break;
+
     case M_ROR_I:
-      if (imm_expr.X_op != O_constant)
-	as_bad (_("rotate count too large"));
-      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
-		   AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
-      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
-		   dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
-      macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
-		   dreg, dreg, AT);
+      {
+	unsigned int rot;
+
+	if (imm_expr.X_op != O_constant)
+	  as_bad (_("rotate count too large"));
+	rot = imm_expr.X_add_number & 0x1f;
+	if (! rot)
+	  break;
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+		     "d,w,<", AT, sreg, rot);
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+		     "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+	macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+		     "d,v,t", dreg, dreg, AT);
+      }
       break;

     case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog	20 May 2002 17:05:34 -0000	1.315
+++ gas/testsuite/ChangeLog	21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* gas/mips/rol64.s: New file, test of drol, dror macros.
+	* gas/mips/rol64.d: Likewise.
+	* gas/mips/mips.exp: Add new test.
+
 2002-05-20  Nick Clifton  <nickc@cambridge.redhat.com>

 	* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp	4 Apr 2002 08:23:30 -0000	1.32
+++ gas/testsuite/gas/mips/mips.exp	21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
 	run_dump_test "mul"
     }
     run_dump_test "rol"
+    run_dump_test "rol64"
     if !$aout { run_dump_test "sb" }
     run_dump_test "trunc"
     if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog	17 May 2002 19:01:03 -0000	1.167
+++ include/opcode/ChangeLog	21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
 2002-05-17  Andrey Volkov  <avolkov@sources.redhat.com>

         * h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h	16 Mar 2002 03:09:18 -0000	1.24
+++ include/opcode/mips.h	21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
   M_REM_3I,
   M_REMU_3,
   M_REMU_3I,
+  M_DROL,
   M_ROL,
+  M_DROL_I,
   M_ROL_I,
+  M_DROR,
   M_ROR,
+  M_DROR_I,
   M_ROR_I,
   M_S_DA,
   M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog	17 May 2002 14:36:45 -0000	1.447
+++ opcodes/ChangeLog	21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
 Fri May 17 14:26:44 2002  J"orn Rennecke <joern.rennecke@superh.com>

 	* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c	17 Mar 2002 02:42:25 -0000	1.32
+++ opcodes/mips-opc.c	21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
 {"dremu",   "d,v,t",	3,    (int) M_DREMU_3,	INSN_MACRO,		I3	},
 {"dremu",   "d,v,I",	3,    (int) M_DREMU_3I,	INSN_MACRO,		I3	},
+{"drol",    "d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		I3	},
+{"drol",    "d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		I3	},
+{"dror",    "d,v,t",	0,    (int) M_DROR,	INSN_MACRO,		I3	},
+{"dror",    "d,v,I",	0,    (int) M_DROR_I,	INSN_MACRO,		I3	},
 {"dsllv",   "d,t,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,		I3	},
 {"dsll32",  "d,w,<",	0x0000003c, 0xffe0003f, WR_d|RD_t,		I3	},
 {"dsll",    "d,w,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,		I3	}, /* dsllv */
 2002-05-21 23:54:48 +00:00
Andrey Volkov
b9c9142c40 * h8300.h: Corrected defs of all control regs and eepmov instr. 2002-05-17 19:01:03 +00:00
Alan Modra
b9612d142d reorder cmpsd, movsd 2002-04-11 11:58:30 +00:00
Alan Modra
cd47f4f16f * i386.h: Add intel mode cmpsd and movsd. 2002-04-11 10:21:58 +00:00
Chris Demetriou
1f25f5d300 [ gas/ChangeLog ] 
2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>

	* config/tc-mips.c (mips_set_options): New "ase_mips3d" member.
	(mips_opts): Initialize "ase_mips3d" member.
	(file_ase_mips3d): New variable.
	(CPU_HAS_MIPS3D): New macro.
	(md_begin): Initialize mips_opts.ase_mips3d and file_ase_mips3d
	based on command line options and configuration defaults.
	(macro_build, mips_ip): Accept MIPS-3D instructions if
	mips_opts.ase_mips3d is set.
	(OPTION_MIPS3D, OPTION_NO_MIPS3D, md_longopts, md_parse_option):
	Add support for "-mips3d" and "-no-mips3d" options.
	(OPTION_ELF_BASE): Move to accomodate new options.
	(s_mipsset): Support ".set mips3d" and ".set nomips3d".
	(mips_elf_final_processing): Add a comment indicating that a
	MIPS-3D ASE ELF header flag should be set, when one exists.
	* doc/as.texinfo: Document -mips3d and -no-mips3d options.
	* doc/c-mips.texi: Likewise, and document ".set mips3d" and ".set
	nomips3d" directives.

[ gas/testsuite/ChangeLog ]
2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>

	* gas/mips/mips64-mips3d.s: New file.
	* gas/mips/mips64-mips3d.d: Likewise.
	* gas/mips/mips.exp: Run new "mips64-mips3d" test.

[ include/opcode/ChangeLog ]
2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>

	* mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
	instructions.
	(OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
	may be passed along with the ISA bitmask.

[ opcodes/ChangeLog ]
2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>

	* mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA
	bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64.  Add
	comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that
	indicate that they should dissassemble all applicable
	MIPS-specified ASEs.
	* mips-opc.c: Add support for MIPS-3D instructions.
	(M3D): New definition.

	* mips-opc.c: Update copyright years.
 2002-03-16 03:09:19 +00:00
Alan Modra
e4b29ec6bd * pdp11.h: Add format codes for float instruction formats. 2002-03-05 03:09:01 +00:00
Alan Modra
eea5c83f2f missdit 2002-02-25 04:13:42 +00:00
Jan Hubicka
5a8b245cb6 * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands. 2002-02-18 16:32:25 +00:00
Jan Hubicka
85a33fe281 * i386.h (push,pop): Allow 16bit operands in 64bit mode. 
(xchg): Fix.
	(in, out): Disable 64bit operands.
	(call, jmp): Avoid REX prefixes.
	(jcxz): Prohibit in 64bit mode
	(jrcxz, loop): Add 64bit variants.
	(movq): Fix patterns.
	(movmskps, pextrw, pinstrw): Add 64bit variants.
 2002-02-11 11:56:20 +00:00
Nick Clifton
3b16e843f2 Add support for OpenRISC 32-bit embedded processor 2002-01-31 17:33:08 +00:00
Graydon Hoare
9a2e995d8a [ include/opcode/ChangeLog ] 
2002-01-22  Graydon Hoare  <graydon@redhat.com>

	* cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure.
	(CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field.

[ opcodes/ChangeLog ]

2002-01-22  Graydon Hoare  <graydon@redhat.com>

	* fr30-asm.c: Regenerate.
	* fr30-desc.c: Likewise.
	* fr30-desc.h: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-ibld.c: Likewise.
	* fr30-opc.c: Likewise.
	* fr30-opc.h: Likewise.
	* m32r-asm.c: Likewise.
	* m32r-desc.c: Likewise.
	* m32r-desc.h: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-ibld.c: Likewise.
	* m32r-opc.c: Likewise.
	* m32r-opc.h: Likewise.
	* m32r-opinst.c: Likewise.
	* openrisc-asm.c: Likewise.
	* openrisc-desc.c: Likewise.
	* openrisc-desc.h: Likewise.
	* openrisc-dis.c: Likewise.
	* openrisc-ibld.c: Likewise.
	* openrisc-opc.c: Likewise.
	* openrisc-opc.h: Likewise.
	* xstormy16-desc.c: Likewise.

[ cgen/ChangeLog ]

2002-01-22  Graydon Hoare  <graydon@redhat.com>

	* desc-cpu.scm (ifld-number-cache): Add.
	(ifld-number): Add.
	(gen-maybe-multi-ifld-of-op): Add.
	(gen-maybe-multi-ifld): Add.
	(gen-multi-ifield-nodes): Add.
	(cgen-desc.c): Add call to gen-multi-ifield-nodes.
 2002-01-22 21:45:36 +00:00
Alan Modra
7b45c6e1da comment typo fixes 2002-01-21 14:03:27 +00:00
Matthew Green
a09cf9bd77 [gas/ChangeLog] 
* config/tc-ppc.c (md_parse_option): BookE is not Motorola specific.

[include/opcode/ChangeLog]
* ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific.
(PPC_OPCODE_BOOKE64): Likewise.
 2002-01-03 02:07:19 +00:00
Jeff Law
1befefea7e * hppa.h (call, ret): Move to end of table. 
(addb, addib): PA2.0 variants should have been PA2.0W.
        (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler
        happy.
        (fldw, fldd, fstw, fstd, bb): Likewise.
        (short loads/stores): Tweak format specifier slightly to keep
        disassembler happy.
        (indexed loads/stores): Likewise.
        (absolute loads/stores): Likewise.
 2001-12-31 23:43:03 +00:00
Alexandre Oliva
124ddbb22f * d10v.h (OPERAND_NOSP): New macro. 2001-12-04 10:06:40 +00:00
Alexandre Oliva
9b21d49b4a * d10v.h (OPERAND_SP): New macro. 2001-11-29 18:03:50 +00:00
Alan Modra
802a735ed9 binutils/ChangeLog 
* doc/binutils.texi (objdump): Document ppc -M options.
gas/ChangeLog
	* config/tc-ppc.c (ppc_insert_operand): Pass (ppc_cpu | ppc_size)
	to operand->insert.
	(md_assemble): Likewise.
gas/testsuite/ChangeLog
	* gas/ppc/booke.d: Modify reloc and target matches for powerpc64.
include/opcode/ChangeLog
	* ppc.h (struct powerpc_operand <insert, extract>): Add dialect param.
opcodes/ChangeLog
	* ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC.
	(insert_bat, extract_bat, insert_bba, extract_bba,
	insert_bd, extract_bd, insert_bdm, extract_bdm,
	insert_bdp, extract_bdp, valid_bo,
	insert_bo, extract_bo, insert_boe, extract_boe,
	insert_ds, extract_ds, insert_de, extract_de,
	insert_des, extract_des, insert_li, extract_li,
	insert_mbe, extract_mbe, insert_mb6, extract_mb6,
	insert_nb, extract_nb, insert_nsi, extract_nsi,
	insert_ral, insert_ram, insert_ras,
	insert_rbs, extract_rbs, insert_sh6, extract_sh6,
	insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param.
	(extract_bd, extract_bdm, extract_bdp,
	extract_ds, extract_des,
	extract_li, extract_nsi): Implement sign extension without conditional.
	(insert_bdm, extract_bdm,
	insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints.
	(extract_bdm, extract_bdp): Correct 32 bit validation.
	(AT1_MASK, AT2_MASK): Define.
	(BBOAT_MASK): Define.
	(BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define.
	(BOFM64, BOFP64, BOTM64, BOTP64): Define.
	(BODNZM64, BODNZP64, BODZM64, BODZP64): Define.
	(PPCCOM32, PPCCOM64): Define.
	(powerpc_opcodes): Modify existing 32 bit insns with branch hints
	and add new patterns to implement 64 bit branches with hints.  Move
	booke instructions so they match before ppc64.
	* ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for
	64 bit default targets, and parse "32" and "64" in options.
	Formatting fixes.
	(print_insn_powerpc): Pass dialect to operand->extract.
 2001-11-15 01:08:53 +00:00
Timothy Wall
6e91790347 Fix tic54x testsuite failures and Lmem disassembly bugs. 2001-11-13 14:22:53 +00:00
Alan Modra
e5470cdc92 * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to 
accept WordReg.
	* i386-dis.c (grps): Change "sldt", "str", and "smsw" entries
	to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand
	category instead of Ew.
 2001-11-13 01:03:55 +00:00
Chris Demetriou
5d84d93fd8 2001-11-04 Chris Demetriou <cgd@broadcom.com> 
* mips.h (OPCODE_IS_MEMBER): Remove extra space.
 2001-11-05 03:07:26 +00:00
Nick Clifton
3c3bdf30e4 Add MMIX support 2001-10-30 15:20:14 +00:00
Chris Demetriou
e4432525bb 2001-10-18 Chris Demetriou <cgd@broadcom.com> 
* mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end
        of the expression, to make source code merging easier.
 2001-10-18 22:41:35 +00:00
Chris Demetriou
8ff529d836 2001-10-17 Chris Demetriou <cgd@broadcom.com> 
* mips.h: Sort coprocessor instruction argument characters
       in comment, add a few more words of description for "H".
 2001-10-18 01:50:26 +00:00
Chris Demetriou
2228315b47 [gas/testsuite/ChangeLog] 
2001-10-17  Chris Demetriou  <cgd@broadcom.com>

        * gas/mips/mips.exp (sb1-ext-ps): New test to test
        SB-1 core's paired-single extensions to the MIPS64 ISA.
        * gas/mips/sb1-ext-ps.d: New file.
        * gas/mips/sb1-ext-ps.s: New file.

[include/opcode/ChangeLog]
2001-10-17  Chris Demetriou  <cgd@broadcom.com>

        * mips.h (INSN_SB1): New cpu-specific instruction bit.
        (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
        if cpu is CPU_SB1.

[opcodes/ChangeLog]
2001-10-17  Chris Demetriou  <cgd@broadcom.com>

        * mips-dis.c (mips_isa_type): Make the ISA used to disassemble
        SB-1 binaries include instructions specific to the SB-1.
        * mips-opc.c (SB1): New definition.
        (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps",
        "recip.ps", "rsqrt.ps", and "sqrt.ps".
 2001-10-18 01:42:16 +00:00
Matthew Green
f5c120c5dc [gas/ChangeLog] 
* config/tc-ppc.c (md_show_usage): Add missing -maltivec, -m7400,
	-m7410, -m7450 and -m7455 options.

[gas/testsuite/ChangeLog]
	* gas/ppc/altivec.s: New test for AltiVec.
	* gas/ppc/altivec.d: New file.
	* gas/ppc/ppc.exp: Test altivec.s

[include/opcode/ChangeLog]
	* ppc.h (PPC_OPCODE_BOOKE64): Fix typo.

[opcodes/ChangeLog]
	* ppc-opc.c (STRM): New AltiVec operand.
	(XDSS): New AltiVec instruction form.
	(mtvscr): Correct operand list.
	(dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions.
 2001-10-17 13:13:16 +00:00
Matthew Green
0716ce0d22 oops, fix an error in the previous entry. 2001-10-13 02:27:25 +00:00
Matthew Green
418c174284 [gas/ChangeLog] 
* config/tc-ppc.c (md_parse_option): New -m7410, -m7450 and -m7455
	flags, equivalent to -m7400.  New -maltivec to enable AltiVec
	instructions.  New -mbook64 and -mbooke/-mbooke32 flags to enable
	64-bit and 32-bit BookE support, respectively.  Change -m403 and
	-m405 to set PPC403 option.
	(md_show_usage): Adjust for new options.
	* doc/all.texi: Set PPC.
	* doc/as.texinfo: Add PPC support and pull in c-ppc.texi.
	* doc/c-ppc.texi: New file.
	* doc/Makefile.am (CPU_DOCS): Add c-ppc.texi.
	* doc/Makefile.in: Regenerate.

[gas/testsuite/ChangeLog]
	* gas/ppc/booke.s: New test for Motorola BookE.
	* gas/ppc/booke.d: New file.
	* gas/ppc/ppc.exp: Test booke.s.

[include/opcode/ChangeLog]
	* ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_403): New opcode flags for
	BookE and PowerPC403 instructions.

[opcodes/ChangeLog]
	* ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New
	instruction field instruction/extraction functions for new BookE
	DE form instructions.
	(CT): New macro for CT field in an X form instruction.
	(DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form
	instructions.
	(PPC64): Don't include PPC_OPCODE_PPC.
	(403): New opcode macro for PPC403 processors.
	(BOOKE): New opcode macro for BookE processors.
	(bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions.
	(bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise.
	(dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise.
	(stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise.
	(mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise.
	(subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise.
	(subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise.
	(addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise.
	(lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise.
	(stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise.
	(tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise.
	(lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise.
	(stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise.
	(lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise.

	* ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look
	for a disassembler option of `booke', `booke32' or `booke64' to enable
	BookE support in the disassembler.
 2001-10-13 01:59:09 +00:00
Nick Clifton
6ff2f2ba11 Remove spurious comment 2001-09-27 07:45:32 +00:00
Nick Clifton
015cf42817 fix compile time warning messages 2001-09-21 06:52:20 +00:00
Richard Henderson
847b8b3176 * alpha.h (struct alpha_operand): Pack elements into bitfields. 2001-09-05 02:52:17 +00:00
Eric Christopher
a98b9439f9 mips3264 support 2001-08-31 21:21:54 +00:00
Alan Modra
a695901141 * ppc.h (PPC_OPERAND_DS): Define. 2001-08-27 10:26:57 +00:00
Andreas Jaeger
d83c654853 For include/opcode: 
* d30v.h: Fix declaration of reg_name_cnt.

	* d10v.h: Fix declaration of d10v_reg_name_cnt.

	* arc.h: Add prototypes from opcodes/arc-opc.c.

For opcodes:
	* tic54x-dis.c: Add unused attributes where needed.

	* z8k-dis.c (output_instr): Add unused attribute.

	* h8300-dis.c: Add missing prototypes.
	(bfd_h8_disassemble): Make static.

	* cris-dis.c: Add missing prototype.
	* h8500-dis.c: Likewise.
	* m68hc11-dis.c: Likewise.
	* pj-dis.c: Likewise.
	* tic54x-dis.c: Likewise.
	* v850-dis.c: Likewise.
	* vax-dis.c: Likewise.
	* w65-dis.c: Likewise.
	* z8k-dis.c: Likewise.

	* d10v-dis.c: Add missing prototype.
	(dis_long): Remove unused variable.
	(dis_2_short): Likewise.

	* sh-dis.c: Add missing prototypes.
	* v850-opc.c: Likewise.
	Add unused attributes where needed.

	* ns32k-dis.c: Add missing prototypes.
	(bit_extract_simple): Remove unused variable.
 2001-08-26 11:47:39 +00:00
Thiemo Seufer
99c14723f3 Add support for MIPS R1[02]000 performance counter opcodes. 2001-08-16 19:24:33 +00:00
Alan Modra
11b37b7b84 Revert 2001-08-08 changes. 2001-08-10 01:34:47 +00:00
Alan Modra
0f1bac05bb * ppc.h (struct powerpc_operand): New field `reloc'. 
* ppc-opc.c: Include "bfd.h".
	(powerpc_operands): Add new field for reloc type.
 2001-08-08 13:19:36 +00:00
Frank Ch. Eigler
81f6038f98 * some support for funny-endian 16/32-bit insn sets 
[cgen/ChangeLog]
2001-07-11  Frank Ch. Eigler  <fche@redhat.com>

        * desc-cpu.scm (-gen-mach-table-defns): Emit fourth field: the
        mach->cpu insn-chunk-bitsize.
        (-gen-cpu-open): In @arch@_cgen_rebuild_tables, process above new
        field toward CGEN_CPU_TABLE->insn_chunk_bitsize.
        * mach.scm (<cpu>): New field insn-chunk-bitsize.
        (-cpu-parse, -cpu-read): Parse/initialize it.
        * doc/rtl.texi (define-cpu): Document it.

[opcodes/ChangeLog]
2001-07-11  Frank Ch. Eigler  <fche@redhat.com>

        * cgen-dis.in (print_insn): Use cgen_get_insn_value instead of
        bfd_get_bits.
        * cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect
        non-zero CGEN_CPU_DESC->insn_chunk_bitsize.

[include/opcode/ChangeLog]
2001-07-11  Frank Ch. Eigler  <fche@redhat.com>

        * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
        (cgen_cpu_desc): Ditto.
 2001-07-12 02:32:25 +00:00
Ben Elliston
32cfffe316 2001-07-07 Ben Elliston <bje@redhat.com> 
* m88k.h: Clean up and reformat. Remove unused code.
 2001-07-06 22:14:07 +00:00
Geoffrey Keating
3e89004774 Index: opcodes/ChangeLog 
2001-06-13  Geoffrey Keating  <geoffk@redhat.com>

	* cgen-asm.c (cgen_parse_keyword): When looking for the
	boundaries of a keyword, allow any special characters
	that are actually in one of the allowed keyword.
	* cgen-opc.c (cgen_keyword_add): Add any special characters
	to the nonalpha_chars field.

Index: cgen/ChangeLog
2001-06-13  Geoffrey Keating  <geoffk@redhat.com>

	* desc.scm (<keyword> 'gen-defn): Add extra zero into
	CGEN_KEYWORD_ENTRY initializers.

Index: include/opcode/ChangeLog
2001-06-13  Geoffrey Keating  <geoffk@redhat.com>

	* cgen.h (cgen_keyword): Add nonalpha_chars field.
 2001-06-14 20:38:42 +00:00
Alan Modra
5a109b6767 Fix some entries. 2001-05-28 10:37:50 +00:00
Nick Clifton
d1cf510e5e Add MIPS r12k support 2001-05-23 17:26:40 +00:00
John Healy
e281c45770 2001-05-23 John Healy <jhealy@redhat.com> 
* cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
 2001-05-23 15:34:43 +00:00
Nick Clifton
aa5f19f2b9 Fix MIPS disassembler so that it produces reassemblable code. 2001-05-15 12:11:13 +00:00
Alan Modra
67d6227df7 Correct cvtps2dq, movdq2q, movq2dq, and movq problems. 2001-05-12 09:52:40 +00:00
Alan Modra
992aaec9a9 Assorted fixes to pinsrw, pextrw, pmovmskb, movmskp, maskmovq. 2001-05-04 11:10:55 +00:00
Hans-Peter Nilsson
4ef7f0bf1c * cris.h (enum cris_insn_version_usage): Correct comment for 
cris_ver_v3p.
 2001-04-05 19:35:17 +00:00
Alan Modra
0f17484fd3 Small tweaks to sse2 instructions. 2001-03-24 06:29:16 +00:00
Hans-Peter Nilsson
7ccb52381a * cris.h (ADD_PC_INCR_OPCODE): New macro. 2001-03-22 16:09:20 +00:00
Kazu Hirata
361bfa20e5 2001-03-21 Kazu Hirata <kazu@hxi.com> 
* h8300.h: Fix formatting.
 2001-03-22 02:51:19 +00:00
Alan Modra
87890af05c paddq and psubq support. 2001-03-22 02:27:54 +00:00
Alan Modra
2e98d2de04 Fix register name printed in warning message. 2001-03-19 11:28:20 +00:00
Nick Clifton
4f1d9bd8e2 Fix typos in ChangeLogs; add coff/external.h; fix copyright dates 2001-03-14 02:27:44 +00:00
Nick Clifton
80a523c2e1 new defines for Coldfire V4. 2001-02-28 23:47:10 +00:00
Nick Clifton
e135f41bc2 Add PDP-11 support 2001-02-18 23:33:11 +00:00
Jan Hubicka
76f227a511 * i386.h (i386_optab): SSE integer converison instructions have 
64bit versions on x86-64.
	* i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison
	instructions.
	(putop): Handle 'Y'
 2001-02-12 16:42:49 +00:00
Nick Clifton
8eaec934e2 Remove extraneous whitespace 2001-02-10 22:26:55 +00:00
Nick Clifton
a85d7ed0f0 Add s390 support 2001-02-10 00:58:38 +00:00
Patrick Macdonald
0715dc88cf Binutils portion of fix for syntax array elements when max 
operands is greater than 127.

	2001-02-02  Patrick Macdonald  <patrickm@redhat.com>

	* cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
	(CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
	(CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.

	* fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS.
	* m32r-desc.h: Regenerate.
 2001-02-02 23:04:40 +00:00
Alan Modra
296bc5686a Fix swapgs instruction. 2001-01-24 07:32:34 +00:00
Alan Modra
1328dc9844 Adds assembly and dis-assembly support for the HPPA wide 
mode, 16 bit forms of ldi, ldo, ldw and stw instructions.
 2001-01-14 05:14:45 +00:00
Jan Hubicka
e2914f484e * i386.c (md_assemble): Check cpu_flags even for nullary instructions. 
* i386.h (i386_optab): Fix pusha and ret templates.

	* i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret
	templates.
 2001-01-13 09:05:55 +00:00
Nick Clifton
0d2bcfafbf Updated ARC assembler from arccores.com 2001-01-11 21:20:20 +00:00
Jan Hubicka
7c2b079e27 * i386.h (pinsrw): Add. 
(pshufw): Remove.
	(cvttpd2dq): Fix operands.
	(cvttps2dq): Likewise.
	(movq2q): Rename to movdq2q.
 2001-01-10 14:31:46 +00:00
Alan Modra
079966a8ad Fix "movnti" 2001-01-10 00:24:43 +00:00
Jeff Johnston
8c1f9e76d2 2001-01-09 Jeff Johnston <jjohnstn@redhat.com> 
* cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number
        of operands (unsigned char or unsigned short).
        (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
        (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
 2001-01-09 17:01:07 +00:00
Jan Hubicka
7bc70a8e57 * tc-i386.c (md_assemble): Handle third byte of the opcode as prefix. 
* i386.h (i386_optab): Make [sml]fence template to use immext field.
 2001-01-05 12:30:12 +00:00
Jan Hubicka
6f8c0c4ccc * tc-i386.h (CpuK6, CpuAthlon, CpuSledgehammer, CpuMMX, Cpu3dnow, 
CpuUnknown): Renumber
	(CpuP4, CpuSSE2): New.
	(CpuUnknownFlags): Add CpuP4 and CpuSSE2

	* i386.h (i386_optab): Fix 64bit pushf template; Add instructions
	introduced by Pentium4
 2001-01-03 15:36:26 +00:00
Jan Hubicka
c0d8940f87 * configure.in: Add support for x86_64 and x86_64-*-linux-gnu* 
* NEWS: Add x86_64.

	* i386.h (i386_optab): Add "rex*" instructions;
	add swapgs; disable jmp/call far direct instructions for
	64bit mode; add syscall and sysret; disable registers for 0xc6
	template.  Add 'q' suffixes to extendable instructions, disable
	obsoletted instructions, add new sign/zero extension ones.
	(i386_regtab): Add extended registers.
	(*Suf): Add No_qSuf.
	(q_Suf, wlq_Suf, bwlq_Suf): New.
 2000-12-30 18:05:10 +00:00
Jan Hubicka
3e73aa7c95 * tc-i386.h (i386_target_format): Define even for ELFs. 
(QWORD_MNEM_SUFFIX): New macro.
	(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
	New macros
	(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
	(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
	ImmExt): Renumber.
	(Size64, No_qSuf, NoRex64, Rex64): New macros.
	(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
	(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
	InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
	SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
	(Reg, WordReg): Add Reg64.
	(Imm): Add Imm32S and Imm64.
	(EncImm): New.
	(Disp): Add Disp64 and Disp32S.
	(AnyMem): Add Disp32S.
	(RegRex, RegRex64): New macros.
	(rex_byte): New type.
	* tc-i386.c (set_16bit_code_flag): Kill.
	(fits_in_unsigned_long, fits_in_signed_long): New functions.
	(reloc): New parameter "signed"; support x86_64.
	(set_code_flag): New.
	(DEFAULT_ARCH): New macro; default to "i386".
	(default_arch): New static variable.
	(struct _i386_insn): New fields Operand_PCrel; rex.
	(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
	(flag_code): New enum and static variable.
	(use_rela_relocations): New static variable.
	(flag_code_names): New static variable.
	(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
	(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
	K6 and Athlon.
	(i386_align_code): Return plain "nop" for x86_64.
	(mode_from_disp_size): Support Disp32S.
	(smallest_imm_type): Support Imm32S and Imm64.
	(offset_in_range): Support size of 8.
	(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
	(md_pseudo_table): Add "code64"; use set_code_flat.
	(md_begin): Emit sane error message on hash failure.
	(tc_i386_fix_adjustable): Support x86_64 relocations.
	(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
	instructions supported on particular arch just partially,
	output of 64bit immediates, handling of Imm32S and Disp32S type.
	(i386_immedaite): Support x86_64 relocations; support 64bit constants.
	(i386_displacement): Likewise.
	(i386_index_check): Cleanup; support 64bit addresses.
	(md_apply_fix3): Support x86_64 relocation and rela.
	(md_longopts): Add "32" and "64".
	(md_parse_option): Add OPTION_32 and OPTION_64.
	(i386_target_format): Call even for ELFs; choose between
	elf64-x86-64 and elf32-i386.
	(i386_validate_fix): Refuse GOTOFF in 64bit mode.
	(tc_gen_reloc): Support rela relocations and x86_64.
	(intel_e09_1): Support QWORD.

	* i386.h (i386_optab): Replace "Imm" with "EncImm".
	(i386_regtab): Add flags field.
 2000-12-20 13:24:13 +00:00
Nick Clifton
bf40d919f9 Fix Formatting. 2000-12-12 19:25:07 +00:00
Nick Clifton
c6c98b3833 Add MIPS SB1 machine 2000-12-02 01:10:33 +00:00
Nick Clifton
84ea6cf2c5 Add MIPS V and MIPS 64 machine numbers 2000-12-02 00:55:22 +00:00
Nick Clifton
e7af610e14 Add MIPS32 as a seperate MIPS architecture 2000-12-01 21:35:38 +00:00
Nick Clifton
4372b67322 Improve MIPS32 support 2000-12-01 20:05:32 +00:00
Jakub Jelinek
19f7b01094 gas/ 
* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
	instructions to loose any special insn->architecture mask.

	* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
	(sparc_md_end, sparc_arch_types, sparc_arch,
	sparc_elf_final_processing): Handle v8plusb and v9b architectures.
	(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
	request v9b architecture if they are used).

bfd/
	* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
	elf32_sparc_object_p, elf32_sparc_final_write_processing):
	Support v8plusb.
	* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
	sparc64_elf_object_p): Support v9b.
	* archures.c: Declare v8plusb and v9b machines.
	* bfd-in2.h: Ditto.
	* cpu-sparc.c: Ditto.

include/opcode/
	* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
	Note that '3' is used for siam operand.

opcodes/
	* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
	(compute_arch_mask): Add v8plusb and v9b machines.
	(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
	* opcodes/sparc-opc.c: Support for Cheetah instruction set.
	(prefetch_table): Add #invalidate.
 2000-10-20 10:38:47 +00:00
Jim Wilson
139368c9f3 Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again. 
gas/ChangeLog
	* config/tc-ia64.c (dv_sem): Add "stop".
	(specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now.
	(specify_resource, case IA64_RS_PRr): New for regs 16 to 62.
	(specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to
	match above.
	(mark_resources): Check IA64_RS_PRr.
gas/testsuite/ChangeLog
	* gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62.
	* gas/ia64/dv-waw-err.s: Likewise.
	* gas/ia64/dv-imply.d: Regenerate.
	* gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d,
	gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l,
	gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise.
include/opcode/ChangeLog
	* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
opcodes/ChangeLog
	* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
	* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
	(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
	* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
	* ia64-asmtab.c: Regnerate.
 2000-09-22 19:43:50 +00:00
Nick Clifton
156c2f8bf7 Add support for the MIPS32 2000-09-14 01:47:38 +00:00
Alan Modra
3c5ce02eb8 doco addition. 2000-09-05 05:22:24 +00:00
Jim Wilson
50b81f1903 Fix 3 DV bugs, and a few minor cleanups. 
gas/
	* config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle
	postincrement modified registers.  Handle IA64_OPND_R3_2 addl
	source registers.
	(note_register_values): Handle IA64_OPND_R3_2 operands.
gas/testsuite/
	* gas/ia64/dv-raw-err.s: Add new tests for addl and postinc.
	* gas/ia64/dv-raw-err.l: Likewise.
	* gas/ia64/dv-waw-err.l: Update sed pattern.
	* gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment.
	* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
include/opcode/
	* ia64.h (IA64_OPCODE_POSTINC): New.
opcodes/
	* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds.  Delete
	break, mov-immediate, nop.
	* ia64-opc-f.c: Delete fpsub instructions.
	* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
	address operand.  Rewrite using macros to avoid long lines.
	* ia64-opc.h (POSTINC): Define.
	* ia64-asmtab.c: Regenerate.
 2000-08-16 23:20:15 +00:00
H.J. Lu
fc29466dba 2000-08-15 H.J. Lu <hjl@gnu.org> 
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
	IgnoreSize change.
 2000-08-16 17:29:23 +00:00
Denis Chertykov
45ee1401ab * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros. 
Move related opcodes closer to each other.
	Minor changes in comments, list undefined opcodes.
 2000-08-06 14:09:14 +00:00
Dave Brolley
9d551405de 2000-07-26 Dave Brolley <brolley@redhat.com> 
* cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
 2000-07-26 22:44:42 +00:00
Hans-Peter Nilsson
c848861769 cris.h: New file. 2000-07-20 15:39:41 +00:00
Nick Clifton
65aa24b6e8 Applied Marek Michalkiewicz <marekm@linux.org.pl>'s patch to ehance the AVR port. 2000-06-27 01:45:30 +00:00
Nick Clifton
60bcf0fa8c Applied Stephane Carrez <Stephane.Carrez@worldnet.fr> patches to add support 
for m68hc11 and m68hc12 processors.
 2000-06-19 01:22:44 +00:00
Denis Chertykov
60a2978a70 * avr.h: clr,lsl,rol, ... moved after add,adc, ... 2000-06-09 18:02:05 +00:00
Denis Chertykov
68ab2dd99e * avr.h: New file with AVR opcodes. 2000-06-07 17:48:35 +00:00
Donald Lindsay
f0662e279c Define the ALONE flag bit, for use in the opcode table. 2000-05-25 22:23:45 +00:00
Alan Modra
b722f2be22 Allow d suffix on iret 2000-05-23 00:36:39 +00:00
Alan Modra
f9e0cf0b83 Fix fild. 2000-05-17 00:47:51 +00:00
Frank Ch. Eigler
f660ee8b2e * cgen/opcodes fix 
* approved by nickc

[opcodes/ChangeLog]
2000-05-16  Frank Ch. Eigler  <fche@redhat.com>

	* fr30-desc.h: Partially regenerated to account for changed
	CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
	* m32r-desc.h: Ditto.

[include/opcode/ChangeLog]
2000-05-16  Frank Ch. Eigler  <fche@redhat.com>

	* cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32.  Check that
	it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set.
	(CGEN_MAX_IFMT_OPERANDS): Increase to 16.  Check that it exceeds
	CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
 2000-05-16 19:28:07 +00:00
Alan Modra
558b0a60a8 Fix cpu_flags for sys{enter,exit} fx{save,restore} 2000-05-13 14:01:54 +00:00
Alan Modra
e413e4e996 `.arch cpu_type' pseudo for x86. 2000-05-13 09:26:23 +00:00
Timothy Wall
5c84d377b6 Support for tic54x target. 2000-05-06 17:14:34 +00:00
J.T. Conklin
966f959b21 * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit. 
(PPC_OPERAND_VR): New operand flag for vector registers.
 2000-05-03 22:19:45 +00:00
Jeff Law
c5d05dbb5e * h8300.h (EOP): Add missing initializer. 2000-05-01 16:55:50 +00:00
Jeff Law
a7fba0e099 * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode 
forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements).
        New operand types l,y,&,fe,fE,fx added to support above forms.
        (pa_opcodes): Replaced usage of 'x' as source/target for
        floating point double-word loads/stores with 'fx'.

Fr
 2000-04-21 21:04:04 +00:00
Jim Wilson
800eeca487 IA-64 ELF support. 2000-04-21 20:22:24 +00:00
Nick Clifton
ba23e138c9 Fix value of SHORT_A1. 
Move SHORT_AR to end of list of short instructions.
 2000-03-27 20:17:02 +00:00
Alan Modra
d0b4722035 Mostly cosmetic. Fixes to comments. Don't start as_bad and as_warn 
messages with capital.  Don't malign Unixware, malign SysV386 instead.
 2000-03-26 14:13:02 +00:00
Nick Clifton
866afedcb4 Apply patch for 100679 2000-03-02 23:01:40 +00:00
Alan Modra
cc5ca5ce51 Extend the i386 gas testsuite to do some tests for intel_syntax. Fix all 
the errors exposed by this addition.  These were intel mode
"fi... word ptr", "fi... dword ptr", "jmp Imm seg, Imm offset", "out dx,al".
The failure with intel "out dx,al" was also present in att "out al,dx".
Extend testsuite to catch this case too.
 2000-02-25 11:41:12 +00:00
Nick Clifton
68e324a2b8 Rename 'flags' to 'signed_overflow_ok_p' 2000-02-24 23:57:23 +00:00
Andrew Haley
60f036a265 2000-02-24 Andrew Haley <aph@cygnus.com> 
* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
        (CGEN_CPU_TABLE): flags: new field.
        Add prototypes for new functions.
 2000-02-24 21:56:53 +00:00
Alan Modra
9b9b5cd47d Forgot Changelog for last i386.h change. 2000-02-24 12:41:54 +00:00
Alan Modra
5b93d8bb51 Add IBM 370 support. 2000-02-23 13:52:23 +00:00
Andrew Haley
87f398dd6a g2000-02-22 Andrew Haley <aph@cygnus.com> 
* mips.h: (OPCODE_IS_MEMBER): Add comment.
 2000-02-22 19:01:25 +00:00
Andrew Haley
9a1e79ca63 ChangeLog change only. 2000-02-22 16:59:39 +00:00
Andrew Haley
367c01aff9 1999-12-30 Andrew Haley <aph@cygnus.com> 
* mips.h (OPCODE_IS_MEMBER): Add gp32 arg.
 2000-02-22 14:39:20 +00:00
Alan Modra
add0c67765 Cosmetic changes to tc-i386.[ch] + extend x86 gas testsuite jmp and 
call tests + tweak intel mode far call and jmp.
 2000-01-15 12:06:03 +00:00
Alan Modra
3138f287b1 x86 indirect jump/call syntax fixes. Disassembly fix for lcall. 1999-12-27 16:10:31 +00:00
Jeff Law
ccecd07b7e * mn10300.h: Add new operand types. Add new instruction formats. 1999-12-01 10:05:24 +00:00
Jeff Law
b37e19e99a * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb" 
instruction.
 1999-11-25 03:28:22 +00:00
Gavin Romig-Koch
5fce5ddfd3 For include/opcode: 
* mips.h (INSN_ISA5): New.

For opcodes:

	* mips-opc.c (I5): New.
	(abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s
	madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps,
	pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
 1999-11-18 19:53:48 +00:00
Gavin Romig-Koch
2bd7f1f332 For include/opcode: 
* mips.h (OPCODE_IS_MEMBER): New.

For gas:

	* config/tc-mips.c (macro_build): Use OPCODE_IS_MEMBER.
	(mips_ip): Use OPCODE_IS_MEMBER.

For opcodes:

	* mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
 1999-11-01 19:29:55 +00:00
Nick Clifton
4df2b5c55e Define SHORT_AR (fix for CR: 101340) 1999-10-29 09:49:04 +00:00
Michael Meissner
446a06c9b8 Add md expression support; Cleanup alpha warnings 1999-10-18 22:29:15 +00:00
Jeff Law
eca04c6a4a * hppa.h (pa_opcodes): Add load and store cache control to 
instructions.  Add ordered access load and store.

        * hppa.h (pa_opcode): Add new entries for addb and addib.

        * hppa.h (pa_opcodes): Fix cmpb and cmpib entries.

        * hppa.h (pa_opcodes):  Add entries for cmpb and cmpib.
 1999-10-10 07:55:25 +00:00
Diego Novillo
c43185deeb Added seven new instructions ld, ld2w, sac, sachi, slae, st and 
st2w for d10v. Created new testsuite for d10v to verify new
instructions.
 1999-10-07 06:17:04 +00:00
Jeff Law
390f858d11 * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve" 
and "be" using completer prefixes.
 1999-09-23 14:29:10 +00:00
Jeff Law
8c47ebd96b * hppa.h (pa_opcodes): Add initializers to silence compiler. 1999-09-23 13:14:33 +00:00
Jeff Law
ec3533da58 * hppa.h: Update comments about character usage. 1999-09-23 13:10:07 +00:00
Jeff Law
18369bea46 * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning 
up the new fstw & bve instructions.
 1999-09-20 09:57:19 +00:00
Jeff Law
d3ffb03249 * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store 
instructions.
 1999-09-19 20:05:00 +00:00
Jeff Law
c49ec3da04 * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. 1999-09-19 19:43:06 +00:00
Jeff Law
5d2e7eccb2 * hppa.h (pa_opcodes): Add long offset double word load/store 
instructions.
 1999-09-19 19:19:50 +00:00
Jeff Law
6397d1a2e8 * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and 
stores.
 1999-09-19 18:54:23 +00:00
Jeff Law
142f0fe0fb * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns. 1999-09-19 18:44:13 +00:00
Jeff Law
f5a68b4510 * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions. 1999-09-19 18:10:28 +00:00
Jeff Law
8235801e55 * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions. 1999-09-19 17:39:17 +00:00
Jeff Law
35184366b0 * hppa.h (pa_opcodes): Add new syntax "be" instructions. 1999-09-19 17:16:08 +00:00
Jeff Law
f0bfde5ebf * hppa.h (pa_opcodes): Note use of 'M' and 'L'. 1999-09-19 17:12:55 +00:00
Jeff Law
27bbbb582a * hppa.h (pa_opcodes): Add support for "b,l". 1999-09-19 16:55:09 +00:00
Jeff Law
c36efdd208 * hppa.h (pa_opcodes): Add support for "b,gate". 1999-09-19 16:41:51 +00:00
Jeff Law
9392fb1136 * hppa.h (pa_opcodes): Use 'fX' for first register operand 
in xmpyu.
 1999-09-18 18:08:34 +00:00
Jeff Law
e0c52e9997 * hppa.h (pa_opcodes): Fix mask for probe and probei. 1999-09-18 17:49:43 +00:00
Jeff Law
f2727d047c * hppa.h (pa_opcodes): Fix mask for depwi. 1999-09-18 17:43:47 +00:00
Jeff Law
52d836e28f * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as 
an explicit output argument.
 1999-09-07 19:46:47 +00:00
Jeff Law
90765e3a9e * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores. 
Add a few PA2.0 loads and store variants.
 1999-09-06 10:42:11 +00:00
Ian Lance Taylor
8340b17f41 1999-09-04 Steve Chamberlain <sac@pobox.com> 
* pj.h: New file.
 1999-09-04 17:16:21 +00:00
Alan Modra
5f47d35be1 Allow spaces in i386 FP reg names, eg. %st ( 1 ). 1999-08-29 23:44:27 +00:00
Jeff Law
7d8fdb64f6 * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args 
by 'f'.
 1999-08-29 07:51:43 +00:00
Jeff Law
90927b9c0e * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi. 
Add supporting args.
 1999-08-28 10:58:26 +00:00
Jeff Law
1d16bf9c3b * hppa.h: Document new completers and args. 
* hppa.h (pa_opcodes):  Add 64 bit patterns and pa2.0 syntax for uxor,
        uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe.  Add pa2.0
        extensions for ssm, rsm, pdtlb, pitlb.  Add performance instructions
        pmenb and pmdis.
 1999-08-28 10:16:15 +00:00
Jeff Law
96226a686f * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl, 
hshr, hsub, mixh, mixw, permh.
 1999-08-28 08:46:57 +00:00
Jeff Law
5d4ba527e1 * hppa.h (pa_opcodes): Change completers in instructions to 
use 'c' prefix.
 1999-08-28 08:16:55 +00:00
Jeff Law
e9fc28c6b6 * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg, 
hshladd, hshradd, shrpd, and shrpw instructions.  Update arg comments.
 1999-08-28 06:41:11 +00:00
Jeff Law
1c1432026f * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg, 
fnegabs to use 'I' instead of 'F'.
 1999-08-28 06:27:12 +00:00
Alan Modra
9e525108fe Add AMD athlon support to x86 assembler and disassembler. 1999-08-21 12:40:39 +00:00
Doug Evans
e8da1bf1bd * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. 1999-08-19 05:45:30 +00:00
Jeff Law
5696871a98 * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, 
and andcm.  Add 32 and 64 bit version of cmpclr, cmpiclr.
 1999-08-06 16:03:53 +00:00
Jeff Law
7d62725820 * hppa.h: Document 64 bit condition completers. 1999-08-06 15:49:29 +00:00
Jeff Law
c5e5291642 * hppa.h (pa_opcodes): Change condition args to use '?' prefix. 1999-08-05 22:58:08 +00:00
Alan Modra
eecb386cd7 Support for gcc to generate 16-bit i386 code. (.code16gcc) 1999-08-04 10:07:41 +00:00
Jeff Law
88a380f31e * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". 
* hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
 1999-07-28 10:31:15 +00:00
Jeff Law
d60e8dcabe * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, 
and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
 1999-07-28 08:06:30 +00:00
Alan Modra
145cf1f06b o 
include/opcode/i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw
 1999-07-13 07:41:46 +00:00
Jeff Law
7382664060 * hppa.h (struct pa_opcode): Add new field "flags". 
(FLAGS_STRICT): Define.
 1999-06-30 23:20:56 +00:00
Jeff Law
f7fc668b8e * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. 1999-06-25 03:29:45 +00:00
Jeff Law
b65db25218 * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. 1999-06-25 03:23:12 +00:00
Alan Modra
1008451944 P 
include/opcode/i386.h: Allow bswapl, arplw, and other dodgy insns.
opcodes/i386-dis.c: Fix a comment
 1999-06-23 06:00:14 +00:00
Jeff Law
cd8a80baf2 * hppa.h (pa_opcodes): Move integer arithmetic instructions after 
integer logical instructions.
 1999-05-28 14:26:52 +00:00
Ian Lance Taylor
1fca749bd1 1999-05-28 Linus Nordberg <linus.nordberg@canit.se> 
* m68k.h: Document new formats `E', `G', `H' and new places `N',
	`n', `o'.
	* m68k.h: Define mcf5206e, mcf5307, mcf.  Document new format `u'
	and new places `m', `M', `h'.
 1999-05-27 22:31:03 +00:00
Jeff Law
aa00890758 * hppa.h (pa_opcodes): Add several processor specific system 
instructions.
 1999-05-27 03:19:32 +00:00
Jeff Law
e26b85f069 * hppa.h (pa_opcodes): Add second entry for "comb", "comib", 
"addb", and "addib" to be used by the disassembler.
 1999-05-26 16:04:11 +00:00
Alan Modra
c608c12e5e P 
i386 PIII SIMD support, remove ReverseRegRegmem kludge
tidy a few things in i386 intel mode disassembly
 1999-05-13 06:00:30 +00:00
Richard Henderson
45c18104f8 * ppc.h (PPC_OPCODE_64_BRIDGE): New. 1999-05-08 23:28:34 +00:00
Richard Henderson
252b5132c7 19990502 sourceware import 1999-05-03 07:29:11 +00:00