[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
This commit is contained in:
Chris Demetriou
parent
2f2c3626c9
commit
deec17343c
13 changed files with 889 additions and 15 deletions
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@ -1,3 +1,29 @@
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2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
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Ed Satterthwaite <ehs@broadcom.com>
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* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
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(mips_opts): Initialize "ase_mdmx" member.
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(file_ase_mdmx): New variable.
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(CPU_HAS_MDMX): New macro.
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(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
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based on command line options and configuration defaults.
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(macro_build): Note in comment that use of MDMX in macros is
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not currently allowed.
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(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
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"Z" MDMX operand types.
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(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
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and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
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types.
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(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
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Add support for "-mdmx" and "-no-mdmx" options.
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(OPTION_ELF_BASE): Move to accomodate new options.
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(s_mipsset): Support ".set mdmx" and ".set nomdmx".
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(mips_elf_final_processing): Set MDMX ASE ELF header flag if
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file_ase_mdmx was set.
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* doc/as.texinfo: Document -mdmx and -no-mdmx options.
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* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
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nomdmx" directives.
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2002-05-31 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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* config/tc-mips.c (OPTION_NO_M7000_HILO_FIX): Rename to
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@ -141,6 +141,7 @@ struct mips_set_options
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if they have not been initialized. Changed by `.set <asename>', by
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command line options, and based on the default architecture. */
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int ase_mips3d;
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int ase_mdmx;
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/* Whether we are assembling for the mips16 processor. 0 if we are
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not, 1 if we are, and -1 if the value has not been initialized.
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Changed by `.set mips16' and `.set nomips16', and the -mips16 and
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@ -189,7 +190,7 @@ static int file_mips_fp32 = -1;
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static struct mips_set_options mips_opts =
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{
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ISA_UNKNOWN, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
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ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
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};
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/* These variables are filled in with the masks of registers used.
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@ -205,6 +206,10 @@ static int file_mips_isa = ISA_UNKNOWN;
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command line (e.g., by -march). */
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static int file_ase_mips3d;
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/* True if -mdmx was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_mdmx;
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/* The argument of the -mcpu= flag. Historical for code generation. */
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static int mips_cpu = CPU_UNKNOWN;
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@ -275,6 +280,10 @@ static int mips_32bitmode = 0;
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#define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
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)
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/* Return true if the given CPU supports the MDMX ASE. */
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#define CPU_HAS_MDMX(cpu) (0 \
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)
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/* Whether the processor uses hardware interlocks to protect
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reads from the HI and LO registers, and thus does not
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require nops to be inserted. */
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@ -1241,6 +1250,8 @@ md_begin ()
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generation of code for them. */
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if (mips_opts.ase_mips3d == -1 && CPU_HAS_MIPS3D (mips_arch))
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mips_opts.ase_mips3d = 1;
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if (mips_opts.ase_mdmx == -1 && CPU_HAS_MDMX (mips_arch))
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mips_opts.ase_mdmx = 1;
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if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
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as_warn (_("Could not set architecture and machine"));
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@ -1253,6 +1264,7 @@ md_begin ()
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file_mips_isa = mips_opts.isa;
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file_mips_abi = mips_opts.abi;
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file_ase_mips3d = mips_opts.ase_mips3d;
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file_ase_mdmx = mips_opts.ase_mdmx;
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mips_opts.gp32 = file_mips_gp32;
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mips_opts.fp32 = file_mips_fp32;
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@ -2917,8 +2929,8 @@ macro_build (place, counter, ep, name, fmt, va_alist)
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/* Search until we get a match for NAME. */
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while (1)
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{
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/* It is assumed here that macros will never generate
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MIPS-3D instructions. */
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/* It is assumed here that macros will never generate
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MDMX or MIPS-3D instructions. */
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if (strcmp (fmt, insn.insn_mo->args) == 0
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&& insn.insn_mo->pinfo != INSN_MACRO
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&& OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
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@ -7795,11 +7807,17 @@ validate_mips_insn (opc)
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case 'L': break;
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case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
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case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
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case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
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case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
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USE_BITS (OP_MASK_FT, OP_SH_FT); break;
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case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
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case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
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case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
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case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
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case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
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case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
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case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
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case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
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case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
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case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
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case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
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@ -7918,6 +7936,7 @@ mips_ip (str, ip)
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if (OPCODE_IS_MEMBER (insn,
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(mips_opts.isa
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| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
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mips_arch))
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ok = true;
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@ -7961,7 +7980,10 @@ mips_ip (str, ip)
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insn_error = NULL;
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for (args = insn->args;; ++args)
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{
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int is_mdmx;
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s += strspn (s, " \t");
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is_mdmx = 0;
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switch (*args)
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{
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case '\0': /* end of args */
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@ -8310,6 +8332,47 @@ mips_ip (str, ip)
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}
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break;
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case 'O': /* MDMX alignment immediate constant. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
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{
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as_warn ("Improper align amount (%ld), using low bits",
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(long) imm_expr.X_add_number);
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imm_expr.X_add_number &= OP_MASK_ALN;
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}
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ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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case 'Q': /* MDMX vector, element sel, or const. */
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if (s[0] != '$')
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{
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/* MDMX Immediate. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
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{
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as_warn (_("Invalid MDMX Immediate (%ld)"),
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(long) imm_expr.X_add_number);
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imm_expr.X_add_number &= OP_MASK_FT;
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}
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imm_expr.X_add_number &= OP_MASK_FT;
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if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
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ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
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else
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ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
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ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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}
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/* Not MDMX Immediate. Fall through. */
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case 'X': /* MDMX destination register. */
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case 'Y': /* MDMX source register. */
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case 'Z': /* MDMX target register. */
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is_mdmx = 1;
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case 'D': /* floating point destination register */
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case 'S': /* floating point source register */
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case 'T': /* floating point target register */
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@ -8317,8 +8380,11 @@ mips_ip (str, ip)
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case 'V':
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case 'W':
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s_reset = s;
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if (s[0] == '$' && s[1] == 'f'
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&& ISDIGIT (s[2]))
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/* Accept $fN for FP and MDMX register numbers, and in
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addition accept $vN for MDMX register numbers. */
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if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
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|| (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
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&& ISDIGIT (s[2])))
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{
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s += 2;
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regno = 0;
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@ -8359,14 +8425,51 @@ mips_ip (str, ip)
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switch (c)
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{
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case 'D':
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case 'X':
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ip->insn_opcode |= regno << OP_SH_FD;
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break;
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case 'V':
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case 'S':
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case 'Y':
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ip->insn_opcode |= regno << OP_SH_FS;
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break;
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case 'Q':
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/* This is like 'Z', but also needs to fix the MDMX
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vector/scalar select bits. Note that the
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scalar immediate case is handled above. */
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if (*s == '[')
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{
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int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
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int max_el = (is_qh ? 3 : 7);
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s++;
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my_getExpression(&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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s = expr_end;
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if (imm_expr.X_add_number > max_el)
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as_bad(_("Bad element selector %ld"),
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(long) imm_expr.X_add_number);
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imm_expr.X_add_number &= max_el;
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ip->insn_opcode |= (imm_expr.X_add_number
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<< (OP_SH_VSEL +
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(is_qh ? 2 : 1)));
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if (*s != ']')
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as_warn(_("Expecting ']' found '%s'"), s);
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else
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s++;
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}
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else
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{
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if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
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ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
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<< OP_SH_VSEL);
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else
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ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
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OP_SH_VSEL);
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}
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/* Fall through */
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case 'W':
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case 'T':
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case 'Z':
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ip->insn_opcode |= regno << OP_SH_FT;
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break;
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case 'R':
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@ -9992,8 +10095,12 @@ struct option md_longopts[] =
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{"mips3d", no_argument, NULL, OPTION_MIPS3D},
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#define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
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{"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
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#define OPTION_MDMX (OPTION_MD_BASE + 35)
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{"mdmx", no_argument, NULL, OPTION_MDMX},
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#define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
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{"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
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#ifdef OBJ_ELF
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#define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
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#define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
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#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
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{"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
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{"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
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@ -10198,6 +10305,14 @@ md_parse_option (c, arg)
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case OPTION_NO_M3900:
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break;
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case OPTION_MDMX:
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mips_opts.ase_mdmx = 1;
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break;
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case OPTION_NO_MDMX:
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mips_opts.ase_mdmx = 0;
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break;
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case OPTION_MIPS16:
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mips_opts.mips16 = 1;
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mips_no_prev_insn (false);
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@ -11532,6 +11647,10 @@ s_mipsset (x)
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{
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mips_opts.nobopt = 1;
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}
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else if (strcmp (name, "mdmx") == 0)
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mips_opts.ase_mdmx = 1;
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else if (strcmp (name, "nomdmx") == 0)
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mips_opts.ase_mdmx = 0;
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else if (strcmp (name, "mips16") == 0
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|| strcmp (name, "MIPS-16") == 0)
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mips_opts.mips16 = 1;
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@ -13021,6 +13140,8 @@ mips_elf_final_processing ()
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if (file_ase_mips3d)
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elf_elfheader (stdoutput)->e_flags |= ???;
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#endif
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if (file_ase_mdmx)
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elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
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/* Set the MIPS ELF ABI flags. */
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if (file_mips_abi == NO_ABI)
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@ -375,6 +375,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-mips32}] [@b{-mips64}]
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[@b{-m4650}] [@b{-no-m4650}]
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[@b{-mips3d}] [@b{-no-mips3d}]
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[@b{-mdmx}] [@b{-no-mdmx}]
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[@b{--trap}] [@b{--break}] [@b{-n}]
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[@b{--emulation}=@var{name} ]
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@end ifset
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@ -888,6 +889,12 @@ Generate code for the MIPS-3D Application Specific Extension.
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This tells the assembler to accept MIPS-3D instructions.
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@samp{-no-mips3d} turns off this option.
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@item -mdmx
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@itemx -no-mdmx
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Generate code for the MDMX Application Specific Extension.
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This tells the assembler to accept MDMX instructions.
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@samp{-no-mdmx} turns off this option.
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@item -mcpu=@var{CPU}
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Generate code for a particular MIPS cpu. It is exactly equivalent to
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@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
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|
|
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|
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@ -105,6 +105,12 @@ Generate code for the MIPS-3D Application Specific Extension.
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This tells the assembler to accept MIPS-3D instructions.
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@samp{-no-mips3d} turns off this option.
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@item -mdmx
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@itemx -no-mdmx
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Generate code for the MDMX Application Specific Extension.
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This tells the assembler to accept MDMX instructions.
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@samp{-no-mdmx} turns off this option.
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@item -mfix7000
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@itemx -mno-fix7000
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Cause nops to be inserted if the read of the destination register
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|
|
@ -343,4 +349,12 @@ from the MIPS-3D Application Specific Extension from that point on
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in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
|
||||
instructions from being accepted.
|
||||
|
||||
@cindex MIPS MDMX instruction generation override
|
||||
@kindex @code{.set mdmx}
|
||||
@kindex @code{.set nomdmx}
|
||||
The directive @code{.set mdmx} makes the assembler accept instructions
|
||||
from the MDMX Application Specific Extension from that point on
|
||||
in the assembly. The @code{.set nomdmx} directive prevents MDMX
|
||||
instructions from being accepted.
|
||||
|
||||
Traditional @sc{mips} assemblers do not support these directives.
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
|
||||
|
||||
* gas/mips/mips64-mdmx.s: New file.
|
||||
* gas/mips/mips64-mdmx.d: Likewise.
|
||||
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
|
||||
|
||||
2002-05-30 Richard Henderson <rth@redhat.com>
|
||||
|
||||
* gas/alpha/elf-tls-1.s, gas/alpha/elf-tls-1.d: New.
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ if { [istarget mips*-*-*] } then {
|
|||
run_dump_test "mips32"
|
||||
run_dump_test "mips64"
|
||||
run_dump_test "mips64-mips3d"
|
||||
run_dump_test "mips64-mdmx"
|
||||
run_dump_test "sb1-ext-ps"
|
||||
|
||||
# It will always fail until someone fixes it.
|
||||
|
|
|
|||
215
gas/testsuite/gas/mips/mips64-mdmx.d
Normal file
215
gas/testsuite/gas/mips/mips64-mdmx.d
Normal file
|
|
@ -0,0 +1,215 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa64
|
||||
#name: MIPS MIPS64 MDMX ASE instructions
|
||||
#as: -mips64 -mdmx
|
||||
|
||||
# Check MIPS64 MDMX ASE instruction assembly and disassembly
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 46b46051 movf\.l \$f1,\$f12,\$fcc5
|
||||
0+0004 <[^>]*> 46b26053 movn\.l \$f1,\$f12,s2
|
||||
0+0008 <[^>]*> 46b56051 movt\.l \$f1,\$f12,\$fcc5
|
||||
0+000c <[^>]*> 46b26052 movz\.l \$f1,\$f12,s2
|
||||
0+0010 <[^>]*> 7ad2604b add\.ob \$v1,\$v12,\$v18
|
||||
0+0014 <[^>]*> 7ad2604b add\.ob \$v1,\$v12,\$v18
|
||||
0+0018 <[^>]*> 7992604b add\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+001c <[^>]*> 7bb2604b add\.qh \$v1,\$v12,0x12
|
||||
0+0020 <[^>]*> 7932604b add\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+0024 <[^>]*> 7bb2604b add\.qh \$v1,\$v12,0x12
|
||||
0+0028 <[^>]*> 7ad26037 adda\.ob \$v12,\$v18
|
||||
0+002c <[^>]*> 7ad26037 adda\.ob \$v12,\$v18
|
||||
0+0030 <[^>]*> 79926037 adda\.ob \$v12,\$v18\[6\]
|
||||
0+0034 <[^>]*> 7ab26037 adda\.qh \$v12,\$v18
|
||||
0+0038 <[^>]*> 7ab26037 adda\.qh \$v12,\$v18
|
||||
0+003c <[^>]*> 79326037 adda\.qh \$v12,\$v18\[2\]
|
||||
0+0040 <[^>]*> 7ad26437 addl\.ob \$v12,\$v18
|
||||
0+0044 <[^>]*> 7ad26437 addl\.ob \$v12,\$v18
|
||||
0+0048 <[^>]*> 79926437 addl\.ob \$v12,\$v18\[6\]
|
||||
0+004c <[^>]*> 7ab26437 addl\.qh \$v12,\$v18
|
||||
0+0050 <[^>]*> 7ab26437 addl\.qh \$v12,\$v18
|
||||
0+0054 <[^>]*> 79326437 addl\.qh \$v12,\$v18\[2\]
|
||||
0+0058 <[^>]*> 78d26058 alni\.ob \$v1,\$v12,\$v18,6
|
||||
0+005c <[^>]*> 7852605a alni\.qh \$v1,\$v12,\$v18,2
|
||||
0+0060 <[^>]*> 7ab26059 alnv\.ob \$v1,\$v12,\$v18,s5
|
||||
0+0064 <[^>]*> 7ab2605b alnv\.qh \$v1,\$v12,\$v18,s5
|
||||
0+0068 <[^>]*> 7ad2604c and\.ob \$v1,\$v12,\$v18
|
||||
0+006c <[^>]*> 7ad2604c and\.ob \$v1,\$v12,\$v18
|
||||
0+0070 <[^>]*> 7992604c and\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+0074 <[^>]*> 7bb2604c and\.qh \$v1,\$v12,0x12
|
||||
0+0078 <[^>]*> 7932604c and\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+007c <[^>]*> 7bb2604c and\.qh \$v1,\$v12,0x12
|
||||
0+0080 <[^>]*> 7ad26001 c\.eq\.ob \$v12,\$v18
|
||||
0+0084 <[^>]*> 7ad26001 c\.eq\.ob \$v12,\$v18
|
||||
0+0088 <[^>]*> 79926001 c\.eq\.ob \$v12,\$v18\[6\]
|
||||
0+008c <[^>]*> 7ab26001 c\.eq\.qh \$v12,\$v18
|
||||
0+0090 <[^>]*> 7ab26001 c\.eq\.qh \$v12,\$v18
|
||||
0+0094 <[^>]*> 79326001 c\.eq\.qh \$v12,\$v18\[2\]
|
||||
0+0098 <[^>]*> 7ad26005 c\.le\.ob \$v12,\$v18
|
||||
0+009c <[^>]*> 7ad26005 c\.le\.ob \$v12,\$v18
|
||||
0+00a0 <[^>]*> 79926005 c\.le\.ob \$v12,\$v18\[6\]
|
||||
0+00a4 <[^>]*> 7ab26005 c\.le\.qh \$v12,\$v18
|
||||
0+00a8 <[^>]*> 7ab26005 c\.le\.qh \$v12,\$v18
|
||||
0+00ac <[^>]*> 79326005 c\.le\.qh \$v12,\$v18\[2\]
|
||||
0+00b0 <[^>]*> 7ad26004 c\.lt\.ob \$v12,\$v18
|
||||
0+00b4 <[^>]*> 7ad26004 c\.lt\.ob \$v12,\$v18
|
||||
0+00b8 <[^>]*> 79926004 c\.lt\.ob \$v12,\$v18\[6\]
|
||||
0+00bc <[^>]*> 7ab26004 c\.lt\.qh \$v12,\$v18
|
||||
0+00c0 <[^>]*> 7ab26004 c\.lt\.qh \$v12,\$v18
|
||||
0+00c4 <[^>]*> 79326004 c\.lt\.qh \$v12,\$v18\[2\]
|
||||
0+00c8 <[^>]*> 7ad26047 max\.ob \$v1,\$v12,\$v18
|
||||
0+00cc <[^>]*> 7ad26047 max\.ob \$v1,\$v12,\$v18
|
||||
0+00d0 <[^>]*> 79926047 max\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+00d4 <[^>]*> 7bb26047 max\.qh \$v1,\$v12,0x12
|
||||
0+00d8 <[^>]*> 79326047 max\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+00dc <[^>]*> 7bb26047 max\.qh \$v1,\$v12,0x12
|
||||
0+00e0 <[^>]*> 7ad26046 min\.ob \$v1,\$v12,\$v18
|
||||
0+00e4 <[^>]*> 7ad26046 min\.ob \$v1,\$v12,\$v18
|
||||
0+00e8 <[^>]*> 79926046 min\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+00ec <[^>]*> 7bb26046 min\.qh \$v1,\$v12,0x12
|
||||
0+00f0 <[^>]*> 79326046 min\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+00f4 <[^>]*> 7bb26046 min\.qh \$v1,\$v12,0x12
|
||||
0+00f8 <[^>]*> 7bb26040 msgn\.qh \$v1,\$v12,0x12
|
||||
0+00fc <[^>]*> 79326040 msgn\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+0100 <[^>]*> 7bb26040 msgn\.qh \$v1,\$v12,0x12
|
||||
0+0104 <[^>]*> 7ad26070 mul\.ob \$v1,\$v12,\$v18
|
||||
0+0108 <[^>]*> 7ad26070 mul\.ob \$v1,\$v12,\$v18
|
||||
0+010c <[^>]*> 79926070 mul\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+0110 <[^>]*> 7bb26070 mul\.qh \$v1,\$v12,0x12
|
||||
0+0114 <[^>]*> 79326070 mul\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+0118 <[^>]*> 7bb26070 mul\.qh \$v1,\$v12,0x12
|
||||
0+011c <[^>]*> 7ad26033 mula\.ob \$v12,\$v18
|
||||
0+0120 <[^>]*> 7ad26033 mula\.ob \$v12,\$v18
|
||||
0+0124 <[^>]*> 79926033 mula\.ob \$v12,\$v18\[6\]
|
||||
0+0128 <[^>]*> 7ab26033 mula\.qh \$v12,\$v18
|
||||
0+012c <[^>]*> 7ab26033 mula\.qh \$v12,\$v18
|
||||
0+0130 <[^>]*> 79326033 mula\.qh \$v12,\$v18\[2\]
|
||||
0+0134 <[^>]*> 7ad26433 mull\.ob \$v12,\$v18
|
||||
0+0138 <[^>]*> 7ad26433 mull\.ob \$v12,\$v18
|
||||
0+013c <[^>]*> 79926433 mull\.ob \$v12,\$v18\[6\]
|
||||
0+0140 <[^>]*> 7ab26433 mull\.qh \$v12,\$v18
|
||||
0+0144 <[^>]*> 7ab26433 mull\.qh \$v12,\$v18
|
||||
0+0148 <[^>]*> 79326433 mull\.qh \$v12,\$v18\[2\]
|
||||
0+014c <[^>]*> 7ad26032 muls\.ob \$v12,\$v18
|
||||
0+0150 <[^>]*> 7ad26032 muls\.ob \$v12,\$v18
|
||||
0+0154 <[^>]*> 79926032 muls\.ob \$v12,\$v18\[6\]
|
||||
0+0158 <[^>]*> 7ab26032 muls\.qh \$v12,\$v18
|
||||
0+015c <[^>]*> 7ab26032 muls\.qh \$v12,\$v18
|
||||
0+0160 <[^>]*> 79326032 muls\.qh \$v12,\$v18\[2\]
|
||||
0+0164 <[^>]*> 7ad26432 mulsl\.ob \$v12,\$v18
|
||||
0+0168 <[^>]*> 7ad26432 mulsl\.ob \$v12,\$v18
|
||||
0+016c <[^>]*> 79926432 mulsl\.ob \$v12,\$v18\[6\]
|
||||
0+0170 <[^>]*> 7ab26432 mulsl\.qh \$v12,\$v18
|
||||
0+0174 <[^>]*> 7ab26432 mulsl\.qh \$v12,\$v18
|
||||
0+0178 <[^>]*> 79326432 mulsl\.qh \$v12,\$v18\[2\]
|
||||
0+017c <[^>]*> 7ad2604f nor\.ob \$v1,\$v12,\$v18
|
||||
0+0180 <[^>]*> 7ad2604f nor\.ob \$v1,\$v12,\$v18
|
||||
0+0184 <[^>]*> 7992604f nor\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+0188 <[^>]*> 7bb2604f nor\.qh \$v1,\$v12,0x12
|
||||
0+018c <[^>]*> 7932604f nor\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+0190 <[^>]*> 7bb2604f nor\.qh \$v1,\$v12,0x12
|
||||
0+0194 <[^>]*> 7ad2604e or\.ob \$v1,\$v12,\$v18
|
||||
0+0198 <[^>]*> 7ad2604e or\.ob \$v1,\$v12,\$v18
|
||||
0+019c <[^>]*> 7992604e or\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+01a0 <[^>]*> 7bb2604e or\.qh \$v1,\$v12,0x12
|
||||
0+01a4 <[^>]*> 7932604e or\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+01a8 <[^>]*> 7bb2604e or\.qh \$v1,\$v12,0x12
|
||||
0+01ac <[^>]*> 7ad26042 pickf\.ob \$v1,\$v12,\$v18
|
||||
0+01b0 <[^>]*> 7ad26042 pickf\.ob \$v1,\$v12,\$v18
|
||||
0+01b4 <[^>]*> 79926042 pickf\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+01b8 <[^>]*> 7bb26042 pickf\.qh \$v1,\$v12,0x12
|
||||
0+01bc <[^>]*> 79326042 pickf\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+01c0 <[^>]*> 7bb26042 pickf\.qh \$v1,\$v12,0x12
|
||||
0+01c4 <[^>]*> 7ad26043 pickt\.ob \$v1,\$v12,\$v18
|
||||
0+01c8 <[^>]*> 7ad26043 pickt\.ob \$v1,\$v12,\$v18
|
||||
0+01cc <[^>]*> 79926043 pickt\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+01d0 <[^>]*> 7bb26043 pickt\.qh \$v1,\$v12,0x12
|
||||
0+01d4 <[^>]*> 79326043 pickt\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+01d8 <[^>]*> 7bb26043 pickt\.qh \$v1,\$v12,0x12
|
||||
0+01dc <[^>]*> 7a00007f rach\.ob \$v1
|
||||
0+01e0 <[^>]*> 7a20007f rach\.qh \$v1
|
||||
0+01e4 <[^>]*> 7800007f racl\.ob \$v1
|
||||
0+01e8 <[^>]*> 7820007f racl\.qh \$v1
|
||||
0+01ec <[^>]*> 7900007f racm\.ob \$v1
|
||||
0+01f0 <[^>]*> 7920007f racm\.qh \$v1
|
||||
0+01f4 <[^>]*> 7bb20065 rnas\.qh \$v1,0x12
|
||||
0+01f8 <[^>]*> 79320065 rnas\.qh \$v1,\$v18\[2\]
|
||||
0+01fc <[^>]*> 7bb20065 rnas\.qh \$v1,0x12
|
||||
0+0200 <[^>]*> 7bd20061 rnau\.ob \$v1,0x12
|
||||
0+0204 <[^>]*> 78920061 rnau\.ob \$v1,\$v18\[2\]
|
||||
0+0208 <[^>]*> 7bd20061 rnau\.ob \$v1,0x12
|
||||
0+020c <[^>]*> 7bb20061 rnau\.qh \$v1,0x12
|
||||
0+0210 <[^>]*> 79320061 rnau\.qh \$v1,\$v18\[2\]
|
||||
0+0214 <[^>]*> 7bb20061 rnau\.qh \$v1,0x12
|
||||
0+0218 <[^>]*> 7bb20066 rnes\.qh \$v1,0x12
|
||||
0+021c <[^>]*> 79320066 rnes\.qh \$v1,\$v18\[2\]
|
||||
0+0220 <[^>]*> 7bb20066 rnes\.qh \$v1,0x12
|
||||
0+0224 <[^>]*> 7bd20062 rneu\.ob \$v1,0x12
|
||||
0+0228 <[^>]*> 78920062 rneu\.ob \$v1,\$v18\[2\]
|
||||
0+022c <[^>]*> 7bd20062 rneu\.ob \$v1,0x12
|
||||
0+0230 <[^>]*> 7bb20062 rneu\.qh \$v1,0x12
|
||||
0+0234 <[^>]*> 79320062 rneu\.qh \$v1,\$v18\[2\]
|
||||
0+0238 <[^>]*> 7bb20062 rneu\.qh \$v1,0x12
|
||||
0+023c <[^>]*> 7bb20064 rzs\.qh \$v1,0x12
|
||||
0+0240 <[^>]*> 79320064 rzs\.qh \$v1,\$v18\[2\]
|
||||
0+0244 <[^>]*> 7bb20064 rzs\.qh \$v1,0x12
|
||||
0+0248 <[^>]*> 7bd20060 rzu\.ob \$v1,0x12
|
||||
0+024c <[^>]*> 78920060 rzu\.ob \$v1,\$v18\[2\]
|
||||
0+0250 <[^>]*> 7bd20060 rzu\.ob \$v1,0x12
|
||||
0+0254 <[^>]*> 7bb20060 rzu\.qh \$v1,0x12
|
||||
0+0258 <[^>]*> 79320060 rzu\.qh \$v1,\$v18\[2\]
|
||||
0+025c <[^>]*> 7bb20060 rzu\.qh \$v1,0x12
|
||||
0+0260 <[^>]*> 7a32605f shfl\.bfla\.qh \$v1,\$v12,\$v18
|
||||
0+0264 <[^>]*> 7992605f shfl\.mixh\.ob \$v1,\$v12,\$v18
|
||||
0+0268 <[^>]*> 7832605f shfl\.mixh\.qh \$v1,\$v12,\$v18
|
||||
0+026c <[^>]*> 79d2605f shfl\.mixl\.ob \$v1,\$v12,\$v18
|
||||
0+0270 <[^>]*> 78b2605f shfl\.mixl\.qh \$v1,\$v12,\$v18
|
||||
0+0274 <[^>]*> 7912605f shfl\.pach\.ob \$v1,\$v12,\$v18
|
||||
0+0278 <[^>]*> 7932605f shfl\.pach\.qh \$v1,\$v12,\$v18
|
||||
0+027c <[^>]*> 7b32605f shfl\.repa\.qh \$v1,\$v12,\$v18
|
||||
0+0280 <[^>]*> 7bb2605f shfl\.repb\.qh \$v1,\$v12,\$v18
|
||||
0+0284 <[^>]*> 78d2605f shfl\.upsl\.ob \$v1,\$v12,\$v18
|
||||
0+0288 <[^>]*> 7ad26050 sll\.ob \$v1,\$v12,\$v18
|
||||
0+028c <[^>]*> 7ad26050 sll\.ob \$v1,\$v12,\$v18
|
||||
0+0290 <[^>]*> 79926050 sll\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+0294 <[^>]*> 7bb26050 sll\.qh \$v1,\$v12,0x12
|
||||
0+0298 <[^>]*> 79326050 sll\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+029c <[^>]*> 7bb26050 sll\.qh \$v1,\$v12,0x12
|
||||
0+02a0 <[^>]*> 7bb26053 sra\.qh \$v1,\$v12,0x12
|
||||
0+02a4 <[^>]*> 79326053 sra\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+02a8 <[^>]*> 7bb26053 sra\.qh \$v1,\$v12,0x12
|
||||
0+02ac <[^>]*> 7ad26052 srl\.ob \$v1,\$v12,\$v18
|
||||
0+02b0 <[^>]*> 7ad26052 srl\.ob \$v1,\$v12,\$v18
|
||||
0+02b4 <[^>]*> 79926052 srl\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+02b8 <[^>]*> 7bb26052 srl\.qh \$v1,\$v12,0x12
|
||||
0+02bc <[^>]*> 79326052 srl\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+02c0 <[^>]*> 7bb26052 srl\.qh \$v1,\$v12,0x12
|
||||
0+02c4 <[^>]*> 7ad2604a sub\.ob \$v1,\$v12,\$v18
|
||||
0+02c8 <[^>]*> 7ad2604a sub\.ob \$v1,\$v12,\$v18
|
||||
0+02cc <[^>]*> 7992604a sub\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+02d0 <[^>]*> 7bb2604a sub\.qh \$v1,\$v12,0x12
|
||||
0+02d4 <[^>]*> 7932604a sub\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+02d8 <[^>]*> 7bb2604a sub\.qh \$v1,\$v12,0x12
|
||||
0+02dc <[^>]*> 7ad26036 suba\.ob \$v12,\$v18
|
||||
0+02e0 <[^>]*> 7ad26036 suba\.ob \$v12,\$v18
|
||||
0+02e4 <[^>]*> 79926036 suba\.ob \$v12,\$v18\[6\]
|
||||
0+02e8 <[^>]*> 7ab26036 suba\.qh \$v12,\$v18
|
||||
0+02ec <[^>]*> 7ab26036 suba\.qh \$v12,\$v18
|
||||
0+02f0 <[^>]*> 79326036 suba\.qh \$v12,\$v18\[2\]
|
||||
0+02f4 <[^>]*> 7ad26436 subl\.ob \$v12,\$v18
|
||||
0+02f8 <[^>]*> 7ad26436 subl\.ob \$v12,\$v18
|
||||
0+02fc <[^>]*> 79926436 subl\.ob \$v12,\$v18\[6\]
|
||||
0+0300 <[^>]*> 7ab26436 subl\.qh \$v12,\$v18
|
||||
0+0304 <[^>]*> 7ab26436 subl\.qh \$v12,\$v18
|
||||
0+0308 <[^>]*> 79326436 subl\.qh \$v12,\$v18\[2\]
|
||||
0+030c <[^>]*> 7a00603e wach\.ob \$v12
|
||||
0+0310 <[^>]*> 7a20603e wach\.qh \$v12
|
||||
0+0314 <[^>]*> 7812603e wacl\.ob \$v12,\$v18
|
||||
0+0318 <[^>]*> 7832603e wacl\.qh \$v12,\$v18
|
||||
0+031c <[^>]*> 7ad2604d xor\.ob \$v1,\$v12,\$v18
|
||||
0+0320 <[^>]*> 7ad2604d xor\.ob \$v1,\$v12,\$v18
|
||||
0+0324 <[^>]*> 7992604d xor\.ob \$v1,\$v12,\$v18\[6\]
|
||||
0+0328 <[^>]*> 7bb2604d xor\.qh \$v1,\$v12,0x12
|
||||
0+032c <[^>]*> 7932604d xor\.qh \$v1,\$v12,\$v18\[2\]
|
||||
0+0330 <[^>]*> 7bb2604d xor\.qh \$v1,\$v12,0x12
|
||||
\.\.\.
|
||||
299
gas/testsuite/gas/mips/mips64-mdmx.s
Normal file
299
gas/testsuite/gas/mips/mips64-mdmx.s
Normal file
|
|
@ -0,0 +1,299 @@
|
|||
# source file to test assembly of MIPS64 MDMX ASE instructions
|
||||
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.globl text_label .text
|
||||
text_label:
|
||||
|
||||
movf.l $v1, $v12, $fcc5
|
||||
|
||||
movn.l $v1, $v12, $18
|
||||
|
||||
movt.l $v1, $v12, $fcc5
|
||||
|
||||
movz.l $v1, $v12, $18
|
||||
|
||||
add.ob $v1, $v12, $v18
|
||||
add.ob $v1, $v12, $v18
|
||||
add.ob $v1, $v12, $v18[6]
|
||||
|
||||
add.qh $v1, $v12, 18
|
||||
add.qh $v1, $v12, $v18[2]
|
||||
add.qh $v1, $v12, 18
|
||||
|
||||
adda.ob $v12, $v18
|
||||
adda.ob $v12, $v18
|
||||
adda.ob $v12, $v18[6]
|
||||
|
||||
adda.qh $v12, $v18
|
||||
adda.qh $v12, $v18
|
||||
adda.qh $v12, $v18[2]
|
||||
|
||||
addl.ob $v12, $v18
|
||||
addl.ob $v12, $v18
|
||||
addl.ob $v12, $v18[6]
|
||||
|
||||
addl.qh $v12, $v18
|
||||
addl.qh $v12, $v18
|
||||
addl.qh $v12, $v18[2]
|
||||
|
||||
alni.ob $v1, $v12, $v18, 6
|
||||
|
||||
alni.qh $v1, $v12, $v18, 2
|
||||
|
||||
alnv.ob $v1, $v12, $v18, $21
|
||||
|
||||
alnv.qh $v1, $v12, $v18, $21
|
||||
|
||||
and.ob $v1, $v12, $v18
|
||||
and.ob $v1, $v12, $v18
|
||||
and.ob $v1, $v12, $v18[6]
|
||||
|
||||
and.qh $v1, $v12, 18
|
||||
and.qh $v1, $v12, $v18[2]
|
||||
and.qh $v1, $v12, 18
|
||||
|
||||
c.eq.ob $v12, $v18
|
||||
c.eq.ob $v12, $v18
|
||||
c.eq.ob $v12, $v18[6]
|
||||
|
||||
c.eq.qh $v12, $v18
|
||||
c.eq.qh $v12, $v18
|
||||
c.eq.qh $v12, $v18[2]
|
||||
|
||||
c.le.ob $v12, $v18
|
||||
c.le.ob $v12, $v18
|
||||
c.le.ob $v12, $v18[6]
|
||||
|
||||
c.le.qh $v12, $v18
|
||||
c.le.qh $v12, $v18
|
||||
c.le.qh $v12, $v18[2]
|
||||
|
||||
c.lt.ob $v12, $v18
|
||||
c.lt.ob $v12, $v18
|
||||
c.lt.ob $v12, $v18[6]
|
||||
|
||||
c.lt.qh $v12, $v18
|
||||
c.lt.qh $v12, $v18
|
||||
c.lt.qh $v12, $v18[2]
|
||||
|
||||
max.ob $v1, $v12, $v18
|
||||
max.ob $v1, $v12, $v18
|
||||
max.ob $v1, $v12, $v18[6]
|
||||
|
||||
max.qh $v1, $v12, 18
|
||||
max.qh $v1, $v12, $v18[2]
|
||||
max.qh $v1, $v12, 18
|
||||
|
||||
min.ob $v1, $v12, $v18
|
||||
min.ob $v1, $v12, $v18
|
||||
min.ob $v1, $v12, $v18[6]
|
||||
|
||||
min.qh $v1, $v12, 18
|
||||
min.qh $v1, $v12, $v18[2]
|
||||
min.qh $v1, $v12, 18
|
||||
|
||||
msgn.qh $v1, $v12, 18
|
||||
msgn.qh $v1, $v12, $v18[2]
|
||||
msgn.qh $v1, $v12, 18
|
||||
|
||||
mul.ob $v1, $v12, $v18
|
||||
mul.ob $v1, $v12, $v18
|
||||
mul.ob $v1, $v12, $v18[6]
|
||||
|
||||
mul.qh $v1, $v12, 18
|
||||
mul.qh $v1, $v12, $v18[2]
|
||||
mul.qh $v1, $v12, 18
|
||||
|
||||
mula.ob $v12, $v18
|
||||
mula.ob $v12, $v18
|
||||
mula.ob $v12, $v18[6]
|
||||
|
||||
mula.qh $v12, $v18
|
||||
mula.qh $v12, $v18
|
||||
mula.qh $v12, $v18[2]
|
||||
|
||||
mull.ob $v12, $v18
|
||||
mull.ob $v12, $v18
|
||||
mull.ob $v12, $v18[6]
|
||||
|
||||
mull.qh $v12, $v18
|
||||
mull.qh $v12, $v18
|
||||
mull.qh $v12, $v18[2]
|
||||
|
||||
muls.ob $v12, $v18
|
||||
muls.ob $v12, $v18
|
||||
muls.ob $v12, $v18[6]
|
||||
|
||||
muls.qh $v12, $v18
|
||||
muls.qh $v12, $v18
|
||||
muls.qh $v12, $v18[2]
|
||||
|
||||
mulsl.ob $v12, $v18
|
||||
mulsl.ob $v12, $v18
|
||||
mulsl.ob $v12, $v18[6]
|
||||
|
||||
mulsl.qh $v12, $v18
|
||||
mulsl.qh $v12, $v18
|
||||
mulsl.qh $v12, $v18[2]
|
||||
|
||||
nor.ob $v1, $v12, $v18
|
||||
nor.ob $v1, $v12, $v18
|
||||
nor.ob $v1, $v12, $v18[6]
|
||||
|
||||
nor.qh $v1, $v12, 18
|
||||
nor.qh $v1, $v12, $v18[2]
|
||||
nor.qh $v1, $v12, 18
|
||||
|
||||
or.ob $v1, $v12, $v18
|
||||
or.ob $v1, $v12, $v18
|
||||
or.ob $v1, $v12, $v18[6]
|
||||
|
||||
or.qh $v1, $v12, 18
|
||||
or.qh $v1, $v12, $v18[2]
|
||||
or.qh $v1, $v12, 18
|
||||
|
||||
pickf.ob $v1, $v12, $v18
|
||||
pickf.ob $v1, $v12, $v18
|
||||
pickf.ob $v1, $v12, $v18[6]
|
||||
|
||||
pickf.qh $v1, $v12, 18
|
||||
pickf.qh $v1, $v12, $v18[2]
|
||||
pickf.qh $v1, $v12, 18
|
||||
|
||||
pickt.ob $v1, $v12, $v18
|
||||
pickt.ob $v1, $v12, $v18
|
||||
pickt.ob $v1, $v12, $v18[6]
|
||||
|
||||
pickt.qh $v1, $v12, 18
|
||||
pickt.qh $v1, $v12, $v18[2]
|
||||
pickt.qh $v1, $v12, 18
|
||||
|
||||
rach.ob $v1
|
||||
|
||||
rach.qh $v1
|
||||
|
||||
racl.ob $v1
|
||||
|
||||
racl.qh $v1
|
||||
|
||||
racm.ob $v1
|
||||
|
||||
racm.qh $v1
|
||||
|
||||
rnas.qh $v1, 18
|
||||
rnas.qh $v1, $v18[2]
|
||||
rnas.qh $v1, 18
|
||||
|
||||
rnau.ob $v1, 18
|
||||
rnau.ob $v1, $v18[2]
|
||||
rnau.ob $v1, 18
|
||||
|
||||
rnau.qh $v1, 18
|
||||
rnau.qh $v1, $v18[2]
|
||||
rnau.qh $v1, 18
|
||||
|
||||
rnes.qh $v1, 18
|
||||
rnes.qh $v1, $v18[2]
|
||||
rnes.qh $v1, 18
|
||||
|
||||
rneu.ob $v1, 18
|
||||
rneu.ob $v1, $v18[2]
|
||||
rneu.ob $v1, 18
|
||||
|
||||
rneu.qh $v1, 18
|
||||
rneu.qh $v1, $v18[2]
|
||||
rneu.qh $v1, 18
|
||||
|
||||
rzs.qh $v1, 18
|
||||
rzs.qh $v1, $v18[2]
|
||||
rzs.qh $v1, 18
|
||||
|
||||
rzu.ob $v1, 18
|
||||
rzu.ob $v1, $v18[2]
|
||||
rzu.ob $v1, 18
|
||||
|
||||
rzu.qh $v1, 18
|
||||
rzu.qh $v1, $v18[2]
|
||||
rzu.qh $v1, 18
|
||||
|
||||
shfl.bfla.qh $v1, $v12, $v18
|
||||
|
||||
shfl.mixh.ob $v1, $v12, $v18
|
||||
shfl.mixh.qh $v1, $v12, $v18
|
||||
|
||||
shfl.mixl.ob $v1, $v12, $v18
|
||||
shfl.mixl.qh $v1, $v12, $v18
|
||||
|
||||
shfl.pach.ob $v1, $v12, $v18
|
||||
shfl.pach.qh $v1, $v12, $v18
|
||||
|
||||
shfl.repa.qh $v1, $v12, $v18
|
||||
|
||||
shfl.repb.qh $v1, $v12, $v18
|
||||
|
||||
shfl.upsl.ob $v1, $v12, $v18
|
||||
|
||||
sll.ob $v1, $v12, $v18
|
||||
sll.ob $v1, $v12, $v18
|
||||
sll.ob $v1, $v12, $v18[6]
|
||||
|
||||
sll.qh $v1, $v12, 18
|
||||
sll.qh $v1, $v12, $v18[2]
|
||||
sll.qh $v1, $v12, 18
|
||||
|
||||
sra.qh $v1, $v12, 18
|
||||
sra.qh $v1, $v12, $v18[2]
|
||||
sra.qh $v1, $v12, 18
|
||||
|
||||
srl.ob $v1, $v12, $v18
|
||||
srl.ob $v1, $v12, $v18
|
||||
srl.ob $v1, $v12, $v18[6]
|
||||
|
||||
srl.qh $v1, $v12, 18
|
||||
srl.qh $v1, $v12, $v18[2]
|
||||
srl.qh $v1, $v12, 18
|
||||
|
||||
sub.ob $v1, $v12, $v18
|
||||
sub.ob $v1, $v12, $v18
|
||||
sub.ob $v1, $v12, $v18[6]
|
||||
|
||||
sub.qh $v1, $v12, 18
|
||||
sub.qh $v1, $v12, $v18[2]
|
||||
sub.qh $v1, $v12, 18
|
||||
|
||||
suba.ob $v12, $v18
|
||||
suba.ob $v12, $v18
|
||||
suba.ob $v12, $v18[6]
|
||||
|
||||
suba.qh $v12, $v18
|
||||
suba.qh $v12, $v18
|
||||
suba.qh $v12, $v18[2]
|
||||
|
||||
subl.ob $v12, $v18
|
||||
subl.ob $v12, $v18
|
||||
subl.ob $v12, $v18[6]
|
||||
|
||||
subl.qh $v12, $v18
|
||||
subl.qh $v12, $v18
|
||||
subl.qh $v12, $v18[2]
|
||||
|
||||
wach.ob $v12
|
||||
|
||||
wach.qh $v12
|
||||
|
||||
wacl.ob $v12, $v18
|
||||
|
||||
wacl.qh $v12, $v18
|
||||
|
||||
xor.ob $v1, $v12, $v18
|
||||
xor.ob $v1, $v12, $v18
|
||||
xor.ob $v1, $v12, $v18[6]
|
||||
|
||||
xor.qh $v1, $v12, 18
|
||||
xor.qh $v1, $v12, $v18[2]
|
||||
xor.qh $v1, $v12, 18
|
||||
|
||||
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 8
|
||||
|
|
@ -1,3 +1,11 @@
|
|||
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
|
||||
|
||||
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
|
||||
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
|
||||
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
|
||||
(INSN_MDMX): New constants, for MDMX support.
|
||||
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
|
||||
|
||||
2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net>
|
||||
|
||||
* dlx.h: New file.
|
||||
|
|
|
|||
|
|
@ -133,6 +133,16 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
|||
#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
|
||||
#define OP_SH_CODE19 6 /* 19 bit wait code. */
|
||||
#define OP_MASK_CODE19 0x7ffff
|
||||
#define OP_SH_ALN 21
|
||||
#define OP_MASK_ALN 0x7
|
||||
#define OP_SH_VSEL 21
|
||||
#define OP_MASK_VSEL 0x1f
|
||||
|
||||
/* Values in the 'VSEL' field. */
|
||||
#define MDMX_FMTSEL_IMM_QH 0x1d
|
||||
#define MDMX_FMTSEL_IMM_OB 0x1e
|
||||
#define MDMX_FMTSEL_VEC_QH 0x15
|
||||
#define MDMX_FMTSEL_VEC_OB 0x16
|
||||
|
||||
/* This structure holds information for a particular instruction. */
|
||||
|
||||
|
|
@ -220,13 +230,21 @@ struct mips_opcode
|
|||
"f" 32 bit floating point constant
|
||||
"l" 32 bit floating point constant in .lit4
|
||||
|
||||
MDMX instruction operands (note that while these use the FP register
|
||||
fields, they accept both $fN and $vN names for the registers):
|
||||
"O" MDMX alignment offset (OP_*_ALN)
|
||||
"Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
|
||||
"X" MDMX destination register (OP_*_FD)
|
||||
"Y" MDMX source register (OP_*_FS)
|
||||
"Z" MDMX source register (OP_*_FT)
|
||||
|
||||
Other:
|
||||
"()" parens surrounding optional value
|
||||
"," separates operands
|
||||
|
||||
Characters used so far, for quick reference when adding more:
|
||||
"<>(),"
|
||||
"ABCDEFGHIJLMNPRSTUVW"
|
||||
"ABCDEFGHIJLMNOPQRSTUVWXYZ"
|
||||
"abcdfhijklopqrstuvwxz"
|
||||
*/
|
||||
|
||||
|
|
@ -297,6 +315,10 @@ struct mips_opcode
|
|||
#define INSN_MULT 0x40000000
|
||||
/* Instruction synchronize shared memory. */
|
||||
#define INSN_SYNC 0x80000000
|
||||
/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
|
||||
#define INSN_READ_MDMX_ACC 0
|
||||
/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
|
||||
#define INSN_WRITE_MDMX_ACC 0
|
||||
|
||||
/* Instruction is actually a macro. It should be ignored by the
|
||||
disassembler, and requires special treatment by the assembler. */
|
||||
|
|
@ -320,6 +342,8 @@ struct mips_opcode
|
|||
|
||||
/* MIPS-3D ASE */
|
||||
#define INSN_MIPS3D 0x00004000
|
||||
/* MDMX ASE */
|
||||
#define INSN_MDMX 0x00008000
|
||||
|
||||
/* Chip specific instructions. These are bitmasks. */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,15 @@
|
|||
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
|
||||
Ed Satterthwaite <ehs@broadcom.com>
|
||||
|
||||
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
|
||||
and 'Z' formats, for MDMX.
|
||||
(mips_isa_type): Add MDMX instructions to the ISA
|
||||
bit mask for bfd_mach_mipsisa64.
|
||||
* mips-opc.c: Add support for MDMX instructions.
|
||||
(MX): New definition.
|
||||
|
||||
* mips-dis.c: Update copyright years to include 2002.
|
||||
|
||||
2002-05-30 Diego Novillo <dnovillo@redhat.com>
|
||||
|
||||
* d10v-opc.c (d10v_opcodes): `btsti' does not modify its
|
||||
|
|
|
|||
|
|
@ -284,6 +284,53 @@ print_insn_arg (d, l, pc, info)
|
|||
(l >> OP_SH_SEL) & OP_MASK_SEL);
|
||||
break;
|
||||
|
||||
case 'O':
|
||||
(*info->fprintf_func) (info->stream, "%d",
|
||||
(l >> OP_SH_ALN) & OP_MASK_ALN);
|
||||
break;
|
||||
|
||||
case 'Q':
|
||||
{
|
||||
unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
|
||||
if ((vsel & 0x10) == 0)
|
||||
{
|
||||
int fmt;
|
||||
vsel &= 0x0f;
|
||||
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
|
||||
if ((vsel & 1) == 0)
|
||||
break;
|
||||
(*info->fprintf_func) (info->stream, "$v%d[%d]",
|
||||
(l >> OP_SH_FT) & OP_MASK_FT,
|
||||
vsel >> 1);
|
||||
}
|
||||
else if ((vsel & 0x08) == 0)
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "$v%d",
|
||||
(l >> OP_SH_FT) & OP_MASK_FT);
|
||||
}
|
||||
else
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "0x%x",
|
||||
(l >> OP_SH_FT) & OP_MASK_FT);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case 'X':
|
||||
(*info->fprintf_func) (info->stream, "$v%d",
|
||||
(l >> OP_SH_FD) & OP_MASK_FD);
|
||||
break;
|
||||
|
||||
case 'Y':
|
||||
(*info->fprintf_func) (info->stream, "$v%d",
|
||||
(l >> OP_SH_FS) & OP_MASK_FS);
|
||||
break;
|
||||
|
||||
case 'Z':
|
||||
(*info->fprintf_func) (info->stream, "$v%d",
|
||||
(l >> OP_SH_FT) & OP_MASK_FT);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* xgettext:c-format */
|
||||
(*info->fprintf_func) (info->stream,
|
||||
|
|
@ -378,8 +425,8 @@ mips_isa_type (mach, isa, cputype)
|
|||
case bfd_mach_mipsisa32:
|
||||
*cputype = CPU_MIPS32;
|
||||
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
|
||||
Note that MIPS-3D is not applicable to MIPS32. (See _MIPS32
|
||||
Architecture For Programmers Volume I: Introduction to the
|
||||
Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
|
||||
_MIPS32 Architecture For Programmers Volume I: Introduction to the
|
||||
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
|
||||
page 1. */
|
||||
*isa = ISA_MIPS32;
|
||||
|
|
@ -387,7 +434,7 @@ mips_isa_type (mach, isa, cputype)
|
|||
case bfd_mach_mipsisa64:
|
||||
*cputype = CPU_MIPS64;
|
||||
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
|
||||
*isa = ISA_MIPS64 | INSN_MIPS3D;
|
||||
*isa = ISA_MIPS64 | INSN_MDMX | INSN_MIPS3D;
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
Contributed by Ralph Campbell and OSF
|
||||
Commented and modified by Ian Lance Taylor, Cygnus Support
|
||||
Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
|
||||
MIPS-3D support added by Broadcom Corporation (SiByte).
|
||||
MIPS-3D and MDMX support added by Broadcom Corporation (SiByte).
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
|
|
@ -75,6 +75,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
|||
|
||||
#define IS_M INSN_MULT
|
||||
|
||||
#define WR_MACC INSN_WRITE_MDMX_ACC
|
||||
#define RD_MACC INSN_READ_MDMX_ACC
|
||||
|
||||
#define I1 INSN_ISA1
|
||||
#define I2 INSN_ISA2
|
||||
#define I3 INSN_ISA3
|
||||
|
|
@ -86,6 +89,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
|||
/* MIPS64 MIPS-3D ASE support. */
|
||||
#define M3D INSN_MIPS3D
|
||||
|
||||
/* MIPS64 MDMX ASE support. */
|
||||
#define MX INSN_MDMX
|
||||
|
||||
#define P3 INSN_4650
|
||||
#define L1 INSN_4010
|
||||
#define V1 INSN_4100
|
||||
|
|
@ -144,15 +150,27 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 },
|
||||
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
|
||||
{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
|
||||
{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
|
||||
{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 },
|
||||
{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX },
|
||||
{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX },
|
||||
{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 },
|
||||
{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
/* b is at the top of the table. */
|
||||
/* bal is at the top of the table. */
|
||||
|
|
@ -256,8 +274,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
|
||||
{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
|
||||
{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
|
||||
{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
|
||||
{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
|
||||
{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
|
|
@ -316,8 +336,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
|
||||
{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
|
||||
{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
|
||||
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
|
||||
{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
|
||||
{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
|
|
@ -328,8 +350,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
|
||||
{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
|
||||
{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
|
||||
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
|
||||
{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
|
||||
{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
|
|
@ -626,6 +650,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
|
||||
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
|
||||
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, V1 },
|
||||
{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
|
||||
{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
|
||||
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
|
||||
|
|
@ -638,28 +664,39 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
|
||||
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
|
||||
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
|
||||
{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
|
||||
{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 },
|
||||
{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32},
|
||||
{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
|
||||
{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX },
|
||||
{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX },
|
||||
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
|
||||
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
|
||||
{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 },
|
||||
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 },
|
||||
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
|
||||
{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX },
|
||||
{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX },
|
||||
{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
|
||||
{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 },
|
||||
{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32 },
|
||||
{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
|
||||
{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX },
|
||||
{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX },
|
||||
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
|
||||
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
|
||||
{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 },
|
||||
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 },
|
||||
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
|
||||
{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX },
|
||||
{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX },
|
||||
{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
|
||||
{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 },
|
||||
/* move is at the top of the table. */
|
||||
{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
|
||||
{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
|
||||
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
|
||||
|
|
@ -681,15 +718,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
|
||||
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
|
||||
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
|
||||
{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3 },
|
||||
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
|
||||
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
|
||||
{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
|
||||
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
|
||||
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
|
||||
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
|
||||
{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
|
||||
{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
|
||||
{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
|
||||
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
|
||||
|
|
@ -708,19 +755,29 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
/* nop is at the start of the table. */
|
||||
{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 },
|
||||
{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
|
||||
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 },
|
||||
{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
|
||||
{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
|
||||
/* pref and prefx are at the start of the table. */
|
||||
|
||||
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
|
||||
{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
|
||||
{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
|
||||
{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
|
||||
{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
|
||||
{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
|
||||
{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
|
||||
{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
|
||||
{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
|
||||
{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
|
||||
|
|
@ -737,6 +794,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 },
|
||||
{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 },
|
||||
{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
|
||||
{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
|
||||
{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
|
||||
{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
|
||||
{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
|
||||
{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
|
||||
{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
|
||||
{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 },
|
||||
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 },
|
||||
{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 },
|
||||
|
|
@ -754,6 +817,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
|
||||
{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
|
||||
{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
|
||||
{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
|
||||
{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
|
||||
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
|
||||
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
|
||||
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 },
|
||||
{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 },
|
||||
|
|
@ -798,6 +864,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 },
|
||||
{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 },
|
||||
{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 },
|
||||
{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 },
|
||||
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 },
|
||||
{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 },
|
||||
|
|
@ -805,6 +881,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
|
||||
{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */
|
||||
{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 },
|
||||
{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 },
|
||||
{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
|
|
@ -819,16 +897,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
|
||||
{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */
|
||||
{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 },
|
||||
{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
|
||||
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
|
||||
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
|
||||
{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
/* ssnop is at the start of the table. */
|
||||
{"standby", "", 0x42000021, 0xffffffff, 0, V1 },
|
||||
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
|
||||
{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
|
||||
{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
|
||||
{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 },
|
||||
{"suspend", "", 0x42000022, 0xffffffff, 0, V1 },
|
||||
|
|
@ -919,11 +1006,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 },
|
||||
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
|
||||
{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
|
||||
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX },
|
||||
{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX },
|
||||
{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
|
||||
{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|I32 },
|
||||
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 },
|
||||
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
|
||||
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
|
||||
|
||||
/* No hazard protection on coprocessor instructions--they shouldn't
|
||||
change the state of the processor and if they do it's up to the
|
||||
user to put in nops as necessary. These are at the end so that the
|
||||
|
|
|
|||
Loading…
Reference in a new issue