Add MIPS V and MIPS 64 machine numbers
This commit is contained in:
Nick Clifton
parent
481294f002
commit
84ea6cf2c5
21 changed files with 216 additions and 70 deletions
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@ -23,6 +23,19 @@
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(_bfd_mips_elf_print_private_bfd_data): Print ISA name for
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MIPS32.
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* aoutx.h (NAME(aout,machine_type)): Add cases for
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bfd_mach_mips5 and bfd_mach_mips64.
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* archures.c (bfd_mach_mips5, bfd_mach_mips64): New constants.
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* bfd-in2.h (bfd_mach_mips5, bfd_mach_mips64): Likewise.
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* cpu_mips.c (I_mips5, I_mips64): New definitions.
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(arch_info_struct): Add entries for bfd_mach_mips5 and
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bfd_mach_mips64.
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* elf32-mips.c (elf_mips_isa, elf_mips_mach,
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_bfd_mips_elf_print_private_bfd_data): Add cases for
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E_MIPS_ARCH_5 and E_MIPS_ARCH_64.
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(_bfd_mips_elf_final_write_processing): Add cases for
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bfd_mach_mips5 and bfd_mach_mips64.
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2000-12-01 Joel Sherrill <joel@OARcorp.com>
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* config.bfd (arm-*-rtems*, a29k-*rtems*): New targets.
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@ -778,6 +778,8 @@ NAME(aout,machine_type) (arch, machine, unknown)
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case bfd_mach_mips16:
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case bfd_mach_mips32:
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case bfd_mach_mips32_4k:
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case bfd_mach_mips5:
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case bfd_mach_mips64:
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/* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
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arch_flags = M_MIPS2;
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break;
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@ -133,6 +133,8 @@ DESCRIPTION
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.#define bfd_mach_mips16 16
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.#define bfd_mach_mips32 32
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.#define bfd_mach_mips32_4k 3204113 {* 32, 04, octal 'K' *}
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.#define bfd_mach_mips5 5
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.#define bfd_mach_mips64 64
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. bfd_arch_i386, {* Intel 386 *}
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.#define bfd_mach_i386_i386 0
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.#define bfd_mach_i386_i8086 1
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@ -1401,6 +1401,8 @@ enum bfd_architecture
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#define bfd_mach_mips16 16
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#define bfd_mach_mips32 32
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#define bfd_mach_mips32_4k 3204113 /* 32, 04, octal 'K' */
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#define bfd_mach_mips5 5
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#define bfd_mach_mips64 64
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bfd_arch_i386, /* Intel 386 */
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#define bfd_mach_i386_i386 0
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#define bfd_mach_i386_i8086 1
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@ -57,29 +57,33 @@ enum
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I_mips16,
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I_mips32,
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I_mips32_4k,
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I_mips5,
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I_mips64,
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};
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#define NN(index) (&arch_info_struct[(index) + 1])
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static const bfd_arch_info_type arch_info_struct[] =
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{
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N (32, 32, bfd_mach_mips3000, "mips:3000", false, NN(I_mips3000)),
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N (32, 32, bfd_mach_mips3900, "mips:3900", false, NN(I_mips3900)),
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N (64, 64, bfd_mach_mips4000, "mips:4000", false, NN(I_mips4000)),
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N (64, 64, bfd_mach_mips4010, "mips:4010", false, NN(I_mips4010)),
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N (64, 64, bfd_mach_mips4100, "mips:4100", false, NN(I_mips4100)),
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N (64, 64, bfd_mach_mips4111, "mips:4111", false, NN(I_mips4111)),
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N (64, 64, bfd_mach_mips4300, "mips:4300", false, NN(I_mips4300)),
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N (64, 64, bfd_mach_mips4400, "mips:4400", false, NN(I_mips4400)),
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N (64, 64, bfd_mach_mips4600, "mips:4600", false, NN(I_mips4600)),
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N (64, 64, bfd_mach_mips4650, "mips:4650", false, NN(I_mips4650)),
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N (64, 64, bfd_mach_mips5000, "mips:5000", false, NN(I_mips5000)),
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N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
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N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
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N (64, 64, bfd_mach_mips10000,"mips:10000",false, NN(I_mips10000)),
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N (64, 64, bfd_mach_mips16, "mips:16", false, NN(I_mips16)),
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N (32, 32, bfd_mach_mips32, "mips:mips32", false, NN(I_mips32)),
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N (32, 32, bfd_mach_mips32_4k,"mips:mips32-4k", false, 0),
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N (32, 32, bfd_mach_mips3000, "mips:3000", false, NN(I_mips3000)),
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N (32, 32, bfd_mach_mips3900, "mips:3900", false, NN(I_mips3900)),
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N (64, 64, bfd_mach_mips4000, "mips:4000", false, NN(I_mips4000)),
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N (64, 64, bfd_mach_mips4010, "mips:4010", false, NN(I_mips4010)),
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N (64, 64, bfd_mach_mips4100, "mips:4100", false, NN(I_mips4100)),
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N (64, 64, bfd_mach_mips4111, "mips:4111", false, NN(I_mips4111)),
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N (64, 64, bfd_mach_mips4300, "mips:4300", false, NN(I_mips4300)),
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N (64, 64, bfd_mach_mips4400, "mips:4400", false, NN(I_mips4400)),
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N (64, 64, bfd_mach_mips4600, "mips:4600", false, NN(I_mips4600)),
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N (64, 64, bfd_mach_mips4650, "mips:4650", false, NN(I_mips4650)),
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N (64, 64, bfd_mach_mips5000, "mips:5000", false, NN(I_mips5000)),
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N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
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N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
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N (64, 64, bfd_mach_mips10000,"mips:10000", false, NN(I_mips10000)),
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N (64, 64, bfd_mach_mips16, "mips:16", false, NN(I_mips16)),
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N (32, 32, bfd_mach_mips32, "mips:mips32", false, NN(I_mips32)),
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N (32, 32, bfd_mach_mips32_4k,"mips:mips32-4k", false, NN(I_mips32_4k)),
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N (64, 64, bfd_mach_mips5, "mips:mips5", false, NN(I_mips5)),
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N (64, 64, bfd_mach_mips64, "mips:mips64", false, 0),
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};
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/* The default architecture is mips:3000, but with a machine number of
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@ -1810,8 +1810,12 @@ elf_mips_isa (flags)
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return 3;
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case E_MIPS_ARCH_4:
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return 4;
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case E_MIPS_ARCH_5:
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return 5;
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case E_MIPS_ARCH_32:
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return 32;
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case E_MIPS_ARCH_64:
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return 64;
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}
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return 4;
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}
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@ -1862,9 +1866,17 @@ elf_mips_mach (flags)
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return bfd_mach_mips8000;
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break;
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case E_MIPS_ARCH_5:
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return bfd_mach_mips5;
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break;
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case E_MIPS_ARCH_32:
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return bfd_mach_mips32;
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break;
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case E_MIPS_ARCH_64:
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return bfd_mach_mips64;
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break;
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}
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}
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@ -2349,6 +2361,14 @@ _bfd_mips_elf_final_write_processing (abfd, linker)
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case bfd_mach_mips32_4k:
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val = E_MIPS_ARCH_32 | E_MIPS_MACH_MIPS32_4K;
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break;
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case bfd_mach_mips5:
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val = E_MIPS_ARCH_5;
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break;
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case bfd_mach_mips64:
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val = E_MIPS_ARCH_64;
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break;
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}
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elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH);
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@ -2656,8 +2676,12 @@ _bfd_mips_elf_print_private_bfd_data (abfd, ptr)
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fprintf (file, _(" [mips3]"));
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else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
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fprintf (file, _(" [mips4]"));
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else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_5)
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fprintf (file, _ (" [mips5]"));
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else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
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fprintf (file, _ (" [mips32]"));
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else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
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fprintf (file, _ (" [mips64]"));
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else
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fprintf (file, _(" [unknown ISA]"));
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@ -6,7 +6,7 @@
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msgid ""
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msgstr ""
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"Project-Id-Version: PACKAGE VERSION\n"
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"POT-Creation-Date: 2000-12-01 13:12-0800\n"
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"POT-Creation-Date: 2000-12-01 16:44-0800\n"
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"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
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"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
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"Language-Team: LANGUAGE <LL@li.org>\n"
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@ -34,22 +34,22 @@ msgstr ""
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msgid "%s: Bad relocation record imported: %d"
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msgstr ""
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#: aoutx.h:1256 aoutx.h:1670
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#: aoutx.h:1258 aoutx.h:1672
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#, c-format
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msgid "%s: can not represent section `%s' in a.out object file format"
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msgstr ""
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#: aoutx.h:1640
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#: aoutx.h:1642
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#, c-format
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msgid ""
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"%s: can not represent section for symbol `%s' in a.out object file format"
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msgstr ""
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#: aoutx.h:1642
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#: aoutx.h:1644
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msgid "*unknown*"
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msgstr ""
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#: aoutx.h:3681
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#: aoutx.h:3683
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#, c-format
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msgid "%s: relocateable link from %s to %s not supported"
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msgstr ""
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@ -660,7 +660,7 @@ msgstr ""
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#. Ignore init flag - it may not be set, despite the flags field
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#. containing valid data.
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#: elf32-arm.h:2195 elf32-cris.c:615 elf32-m68k.c:430 elf32-mips.c:2632
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#: elf32-arm.h:2195 elf32-cris.c:615 elf32-m68k.c:430 elf32-mips.c:2652
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#, c-format
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msgid "private flags = %lx:"
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msgstr ""
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@ -854,124 +854,132 @@ msgstr ""
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msgid "Linking mips16 objects into %s format is not supported"
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msgstr ""
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#: elf32-mips.c:2519
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#: elf32-mips.c:2539
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#, c-format
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msgid "%s: linking PIC files with non-PIC files"
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msgstr ""
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#: elf32-mips.c:2529
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#: elf32-mips.c:2549
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#, c-format
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msgid "%s: linking abicalls files with non-abicalls files"
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msgstr ""
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#: elf32-mips.c:2558
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#: elf32-mips.c:2578
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#, c-format
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msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"
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msgstr ""
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#: elf32-mips.c:2567
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#: elf32-mips.c:2587
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#, c-format
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msgid "%s: ISA mismatch (%d) with previous modules (%d)"
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msgstr ""
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#: elf32-mips.c:2590
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#: elf32-mips.c:2610
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#, c-format
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msgid "%s: ABI mismatch: linking %s module with previous %s modules"
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msgstr ""
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#: elf32-mips.c:2604 elf32-ppc.c:1481 elf64-sparc.c:2974
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#: elf32-mips.c:2624 elf32-ppc.c:1481 elf64-sparc.c:2974
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#, c-format
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msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
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msgstr ""
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#: elf32-mips.c:2635
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#: elf32-mips.c:2655
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msgid " [abi=O32]"
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msgstr ""
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#: elf32-mips.c:2637
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#: elf32-mips.c:2657
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msgid " [abi=O64]"
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msgstr ""
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#: elf32-mips.c:2639
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#: elf32-mips.c:2659
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msgid " [abi=EABI32]"
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msgstr ""
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#: elf32-mips.c:2641
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#: elf32-mips.c:2661
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msgid " [abi=EABI64]"
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msgstr ""
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#: elf32-mips.c:2643
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#: elf32-mips.c:2663
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msgid " [abi unknown]"
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msgstr ""
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#: elf32-mips.c:2645
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#: elf32-mips.c:2665
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msgid " [abi=N32]"
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msgstr ""
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#: elf32-mips.c:2647
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#: elf32-mips.c:2667
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msgid " [abi=64]"
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msgstr ""
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#: elf32-mips.c:2649
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#: elf32-mips.c:2669
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msgid " [no abi set]"
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msgstr ""
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#: elf32-mips.c:2652
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#: elf32-mips.c:2672
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msgid " [mips1]"
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msgstr ""
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#: elf32-mips.c:2654
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#: elf32-mips.c:2674
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msgid " [mips2]"
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msgstr ""
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#: elf32-mips.c:2656
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#: elf32-mips.c:2676
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msgid " [mips3]"
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msgstr ""
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#: elf32-mips.c:2658
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#: elf32-mips.c:2678
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msgid " [mips4]"
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msgstr ""
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#: elf32-mips.c:2660
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#: elf32-mips.c:2680
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msgid " [mips5]"
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msgstr ""
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#: elf32-mips.c:2682
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msgid " [mips32]"
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msgstr ""
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#: elf32-mips.c:2662
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#: elf32-mips.c:2684
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msgid " [mips64]"
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msgstr ""
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#: elf32-mips.c:2686
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msgid " [unknown ISA]"
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msgstr ""
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#: elf32-mips.c:2665
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#: elf32-mips.c:2689
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msgid " [32bitmode]"
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msgstr ""
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#: elf32-mips.c:2667
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#: elf32-mips.c:2691
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msgid " [not 32bitmode]"
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msgstr ""
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#: elf32-mips.c:4316
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#: elf32-mips.c:4340
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msgid "static procedure (no name)"
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msgstr ""
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#: elf32-mips.c:4931 elf64-alpha.c:4378
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#: elf32-mips.c:4955 elf64-alpha.c:4378
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#, c-format
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msgid "%s: illegal section name `%s'"
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msgstr ""
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#: elf32-mips.c:5495
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#: elf32-mips.c:5519
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msgid "not enough GOT space for local GOT entries"
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msgstr ""
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#: elf32-mips.c:6612
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#: elf32-mips.c:6636
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#, c-format
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msgid "%s: %s+0x%lx: jump to stub routine which is not jal"
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msgstr ""
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#: elf32-mips.c:7599
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#: elf32-mips.c:7623
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#, c-format
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msgid "Malformed reloc detected for section %s"
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msgstr ""
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#: elf32-mips.c:7676
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#: elf32-mips.c:7700
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#, c-format
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msgid "%s: CALL16 reloc at 0x%lx not against global symbol"
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msgstr ""
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@ -4,6 +4,9 @@
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EF_MIPS_ARCH. Replace use of E_MIPS_MACH_MIPS32 with
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E_MIPS_MACH_MIPS32_4K and adjust printed CPU name similarly.
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* readelf.c (get_machine_flags): Add cases for E_MIPS_ARCH_5,
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and E_MIPS_ARCH_64.
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2000-11-30 Richard Earnshaw <rearnsha@arm.com>
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* readelf.c (frame_display_row): Output 's' for DW_CFA_same_value.
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@ -1471,9 +1471,15 @@ get_machine_flags (e_flags, e_machine)
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if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
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strcat (buf, ", mips4");
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if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_5)
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strcat (buf, ", mips5");
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if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
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strcat (buf, ", mips32");
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if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
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strcat (buf, ", mips64");
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switch ((e_flags & EF_MIPS_MACH))
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{
|
||||
case E_MIPS_MACH_3900: strcat (buf, ", 3900"); break;
|
||||
|
|
|
|||
|
|
@ -52,6 +52,21 @@
|
|||
4Kp entries with a single mips32-4k entry. Note that you can
|
||||
use ".set mips32".
|
||||
|
||||
* tc-mips.c (ISA_HAS_64BIT_REGS): Add checks for ISA_MIPS5 and
|
||||
ISA_MIPS64.
|
||||
(md_longopts, OPTION_MIPS5, OPTION_MIPS64): Add options for
|
||||
-mips5 and -mips64.
|
||||
(md_parse_option): Add cases for OPTION_MIPS5 and
|
||||
OPTION_MIPS64.
|
||||
(md_show_usage): Mention -mips5 and -mips64 arguments.
|
||||
(s_mipsset): Add cases for MIPS5 and MIPS64.
|
||||
(mips_cpu_info_table): Add entries for MIPS5 and MIPS64 ISAs
|
||||
and pseudo-CPUs.
|
||||
* doc/as.texinfo: Mention -mips5 and -mips64 options
|
||||
and their meanings.
|
||||
* doc/c-mips.texi: Likewise. Also update introduction
|
||||
and ".set" usage information.
|
||||
|
||||
2000-12-01 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* configure.in (arm-*-rtems*, a29k-*rtems*, h8300-*-rtems*):
|
||||
|
|
|
|||
|
|
@ -238,6 +238,8 @@ static int mips_gp32 = 0;
|
|||
#define ISA_HAS_64BIT_REGS(ISA) ( \
|
||||
(ISA) == ISA_MIPS3 \
|
||||
|| (ISA) == ISA_MIPS4 \
|
||||
|| (ISA) == ISA_MIPS5 \
|
||||
|| (ISA) == ISA_MIPS32 \
|
||||
)
|
||||
|
||||
/* Whether the processor uses hardware interlocks to protect
|
||||
|
|
@ -8884,6 +8886,10 @@ struct option md_longopts[] =
|
|||
{"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
|
||||
#define OPTION_MIPS32 (OPTION_MD_BASE + 28)
|
||||
{"mips32", no_argument, NULL, OPTION_MIPS32},
|
||||
#define OPTION_MIPS5 (OPTION_MD_BASE + 29)
|
||||
{"mips5", no_argument, NULL, OPTION_MIPS5},
|
||||
#define OPTION_MIPS64 (OPTION_MD_BASE + 30)
|
||||
{"mips64", no_argument, NULL, OPTION_MIPS64},
|
||||
#ifdef OBJ_ELF
|
||||
#define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
|
||||
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
|
||||
|
|
@ -8969,10 +8975,18 @@ md_parse_option (c, arg)
|
|||
mips_opts.isa = ISA_MIPS4;
|
||||
break;
|
||||
|
||||
case OPTION_MIPS5:
|
||||
mips_opts.isa = ISA_MIPS5;
|
||||
break;
|
||||
|
||||
case OPTION_MIPS32:
|
||||
mips_opts.isa = ISA_MIPS32;
|
||||
break;
|
||||
|
||||
case OPTION_MIPS64:
|
||||
mips_opts.isa = ISA_MIPS64;
|
||||
break;
|
||||
|
||||
case OPTION_MCPU:
|
||||
{
|
||||
/* Identify the processor type. */
|
||||
|
|
@ -9206,7 +9220,9 @@ MIPS options:\n\
|
|||
-mips2 generate MIPS ISA II instructions\n\
|
||||
-mips3 generate MIPS ISA III instructions\n\
|
||||
-mips4 generate MIPS ISA IV instructions\n\
|
||||
-mips5 generate MIPS ISA V instructions\n\
|
||||
-mips32 generate MIPS32 ISA instructions\n\
|
||||
-mips64 generate MIPS64 ISA instructions\n\
|
||||
-mcpu=CPU generate code for CPU, where CPU is one of:\n"));
|
||||
|
||||
first = 1;
|
||||
|
|
@ -10234,15 +10250,15 @@ s_mipsset (x)
|
|||
isa = atoi (name + 4);
|
||||
switch (isa)
|
||||
{
|
||||
case 0: mips_opts.isa = file_mips_isa; break;
|
||||
case 1: mips_opts.isa = ISA_MIPS1; break;
|
||||
case 2: mips_opts.isa = ISA_MIPS2; break;
|
||||
case 3: mips_opts.isa = ISA_MIPS3; break;
|
||||
case 4: mips_opts.isa = ISA_MIPS4; break;
|
||||
case 32: mips_opts.isa = ISA_MIPS32; break;
|
||||
default:
|
||||
as_bad (_("unknown ISA level"));
|
||||
break;
|
||||
case 0: mips_opts.isa = file_mips_isa; break;
|
||||
case 1: mips_opts.isa = ISA_MIPS1; break;
|
||||
case 2: mips_opts.isa = ISA_MIPS2; break;
|
||||
case 3: mips_opts.isa = ISA_MIPS3; break;
|
||||
case 5: mips_opts.isa = ISA_MIPS5; break;
|
||||
case 4: mips_opts.isa = ISA_MIPS4; break;
|
||||
case 32: mips_opts.isa = ISA_MIPS32; break;
|
||||
case 64: mips_opts.isa = ISA_MIPS64; break;
|
||||
default: as_bad (_("unknown ISA level")); break;
|
||||
}
|
||||
}
|
||||
else if (strcmp (name, "autoextend") == 0)
|
||||
|
|
@ -11914,12 +11930,23 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
|
|||
/* MIPS4 ISA */
|
||||
{ "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
|
||||
|
||||
/* MIPS5 ISA */
|
||||
{ "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, },
|
||||
{ "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, },
|
||||
|
||||
/* MIPS32 ISA */
|
||||
{ "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, },
|
||||
{ "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, },
|
||||
|
||||
#if 1
|
||||
/* XXX for now, MIPS64 -> MIPS3 because of history */
|
||||
{ "MIPS64", 1, ISA_MIPS3, CPU_R4000 }, /* XXX! */
|
||||
#else
|
||||
/* MIPS64 ISA */
|
||||
{ "MIPS64", 1, ISA_MIPS64, CPU_MIPS64 },
|
||||
#endif
|
||||
{ "mips64isa", 1, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, },
|
||||
|
||||
/* R2000 CPU */
|
||||
{ "R2000", 0, ISA_MIPS1, CPU_R2000, },
|
||||
|
|
|
|||
|
|
@ -276,7 +276,8 @@ Here is a brief summary of how to invoke @code{@value{AS}}. For details,
|
|||
@end ifset
|
||||
@ifset MIPS
|
||||
[ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
|
||||
[ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips32 ]
|
||||
[ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips5 ]
|
||||
[ -mips32 ] [ -mips64 ]
|
||||
[ -m4650 ] [ -no-m4650 ]
|
||||
[ --trap ] [ --break ]
|
||||
[ --emulation=@var{name} ]
|
||||
|
|
@ -674,8 +675,11 @@ Generate ``little endian'' format output.
|
|||
@itemx -mips32
|
||||
Generate code for a particular MIPS Instruction Set Architecture level.
|
||||
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
|
||||
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000}
|
||||
processor, @samp{-mips32} to a generic @sc{MIPS32} processor.
|
||||
@samp{-mips2} to the @sc{r6000} processor, and @samp{-mips3} to the @sc{r4000}
|
||||
processor.
|
||||
@samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
|
||||
to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
|
||||
processors, respectively.
|
||||
|
||||
@item -m4650
|
||||
@itemx -no-m4650
|
||||
|
|
|
|||
|
|
@ -13,7 +13,8 @@
|
|||
|
||||
@cindex MIPS processor
|
||||
@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
|
||||
different @sc{mips} processors, and MIPS ISA levels I through IV. For
|
||||
different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
|
||||
and MIPS64. For
|
||||
information about the @sc{mips} instruction set, see @cite{MIPS RISC
|
||||
Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview
|
||||
of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
|
||||
|
|
@ -60,13 +61,18 @@ to select big-endian output, and @samp{-EL} for little-endian.
|
|||
@itemx -mips2
|
||||
@itemx -mips3
|
||||
@itemx -mips4
|
||||
@itemx -mips5
|
||||
@itemx -mips32
|
||||
@itemx -mips64
|
||||
Generate code for a particular MIPS Instruction Set Architecture level.
|
||||
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
|
||||
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
|
||||
@sc{r4000} processor, @samp{-mips4} to the @sc{r8000} and
|
||||
@sc{r10000} processors, and @samp{-mips32} to a generic @sc(MIPS32)
|
||||
processor. You can also switch instruction sets during the
|
||||
@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
|
||||
@sc{r10000} processors.
|
||||
@samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
|
||||
to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
|
||||
processors, respectively.
|
||||
You can also switch instruction sets during the
|
||||
assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
|
||||
|
||||
@item -mgp32
|
||||
|
|
@ -239,8 +245,9 @@ assembly language programmers!
|
|||
@kindex @code{.set mips@var{n}}
|
||||
@sc{gnu} @code{@value{AS}} supports an additional directive to change
|
||||
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
|
||||
mips@var{n}}. @var{n} should be a number from 0 to 4, or 32. The values 1
|
||||
to 4 and 32 make the assembler accept instructions for the corresponding
|
||||
mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64.
|
||||
The values 1 to 5, 32, and 64 make the assembler accept instructions
|
||||
for the corresponding
|
||||
@sc{isa} level, from that point on in the assembly. @code{.set
|
||||
mips@var{n}} affects not only which instructions are permitted, but also
|
||||
how certain macros are expanded. @code{.set mips0} restores the
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
(E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the
|
||||
former with the latter.
|
||||
|
||||
* mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions.
|
||||
|
||||
2000-11-30 Jan Hubicka <jh@suse.cz>
|
||||
|
||||
* common.h (EM_X86_64): New macro.
|
||||
|
|
|
|||
|
|
@ -121,9 +121,15 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
|
|||
/* -mips4 code. */
|
||||
#define E_MIPS_ARCH_4 0x30000000
|
||||
|
||||
/* -mips5 code. */
|
||||
#define E_MIPS_ARCH_5 0x40000000
|
||||
|
||||
/* -mips32 code. */
|
||||
#define E_MIPS_ARCH_32 0x50000000
|
||||
|
||||
/* -mips64 code. */
|
||||
#define E_MIPS_ARCH_64 0x60000000
|
||||
|
||||
/* The ABI of the file. Also see EF_MIPS_ABI2 above. */
|
||||
#define EF_MIPS_ABI 0x0000F000
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,9 @@
|
|||
(OPCODE_IS_MEMBER): Update for new ISA membership-related
|
||||
constant meanings.
|
||||
|
||||
* mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
|
||||
definitions.
|
||||
|
||||
2000-10-20 Jakub Jelinek <jakub@redhat.com>
|
||||
|
||||
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
|
||||
|
|
|
|||
|
|
@ -313,6 +313,7 @@ struct mips_opcode
|
|||
#define INSN_ISA4 0x00000080
|
||||
#define INSN_ISA5 0x00000100
|
||||
#define INSN_ISA32 0x00000200
|
||||
#define INSN_ISA64 0x00000400
|
||||
|
||||
/* Chip specific instructions. These are bitmasks. */
|
||||
|
||||
|
|
@ -334,7 +335,9 @@ struct mips_opcode
|
|||
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
|
||||
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
|
||||
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
|
||||
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
|
||||
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
|
||||
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
|
||||
|
||||
/* CPU defines, use instead of hardcoding processor number. Keep this
|
||||
in sync with bfd/archures.c in order for machine selection to work. */
|
||||
|
|
@ -357,6 +360,8 @@ struct mips_opcode
|
|||
#define CPU_MIPS16 16
|
||||
#define CPU_MIPS32 32
|
||||
#define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K' */
|
||||
#define CPU_MIPS5 5
|
||||
#define CPU_MIPS64 64
|
||||
|
||||
/* Test for membership in an ISA including chip specific ISAs.
|
||||
INSN is pointer to an element of the opcode table; ISA is the
|
||||
|
|
|
|||
|
|
@ -25,6 +25,10 @@
|
|||
(P4): Delete.
|
||||
(mips_builtin_opcodes) Replace all uses of P4 with I32.
|
||||
|
||||
* mips-dis.c (set_mips_isa_type): Add cases for
|
||||
bfd_mach_mips5 and bfd_mach_mips64.
|
||||
* mips-opc.c (I64): New definitions.
|
||||
|
||||
2000-11-28 Hans-Peter Nilsson <hp@bitrange.com>
|
||||
|
||||
* sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.
|
||||
|
|
|
|||
|
|
@ -363,6 +363,14 @@ set_mips_isa_type (mach, isa, cputype)
|
|||
target_processor = CPU_MIPS32_4K;
|
||||
mips_isa = ISA_MIPS32;
|
||||
break;
|
||||
case bfd_mach_mips5:
|
||||
target_processor = CPU_MIPS5;
|
||||
mips_isa = ISA_MIPS5;
|
||||
break;
|
||||
case bfd_mach_mips64:
|
||||
target_processor = CPU_MIPS64;
|
||||
mips_isa = ISA_MIPS64;
|
||||
break;
|
||||
default:
|
||||
target_processor = CPU_R3000;
|
||||
mips_isa = ISA_MIPS3;
|
||||
|
|
|
|||
|
|
@ -78,6 +78,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
|||
#define I4 INSN_ISA4
|
||||
#define I5 INSN_ISA5
|
||||
#define I32 INSN_ISA32
|
||||
#define I64 INSN_ISA64
|
||||
|
||||
#define P3 INSN_4650
|
||||
#define L1 INSN_4010
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
msgid ""
|
||||
msgstr ""
|
||||
"Project-Id-Version: PACKAGE VERSION\n"
|
||||
"POT-Creation-Date: 2000-12-01 13:18-0800\n"
|
||||
"POT-Creation-Date: 2000-12-01 16:51-0800\n"
|
||||
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
|
||||
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
|
||||
"Language-Team: LANGUAGE <LL@li.org>\n"
|
||||
|
|
|
|||
Loading…
Reference in a new issue