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Applied Stephane Carrez <Stephane.Carrez@worldnet.fr> patches to add support

Browse source 
for m68hc11 and m68hc12 processors.
This commit is contained in:
Nick Clifton 2000-06-19 01:22:44 +00:00
parent 58781cd0ba
commit 60bcf0fa8c
98 changed files with 11823 additions and 2665 deletions
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2
.cvsignore
View file

@ -28,3 +28,5 @@ configure.vrs
dir.info
Makefile
lost+found
update.out

20
bfd/ChangeLog
View file

@ -1,3 +1,23 @@
2000-06-18 Stephane Carrez <stcarrez@worldnet.fr>
* Makefile.in, bfd-in2.h, libbfd.h, configure: Rebuild.
* Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES, BFD32_BACKENDS,
BFD32_BACKENDS_CFILES): Add 68hc12, 68hc11 files.
* configure.in (bfd_elf32_m68hc12_vec): Recognize.
(bfd_elf32_m68hc11_vec): Likewise.
* config.bfd (targ_cpu): Recognize 68hc12 and 68hc11.
Supports 68hc11 & 68hc12 at the same time.
* targets.c (bfd_elf32_m68hc12_vec): Declare and put in
bfd_target_vector.
(bfd_elf32_m68hc11_vec): Likewise.
* elf.c (prep_headers): Recognize bfd_arch_m68hc12 and 68hc11.
* archures.c (bfd_m68hc12_arch): Define and register in global list
(bfd_m68hc11_arch): Likewise.
* reloc.c (BFD_RELOC_M68HC11_HI8, BFD_RELOC_M68HC11_LO8,
BFD_RELOC_M68HC11_3B): Define.
* cpu-m68hc12.c, elf32-m68hc12.c: New files for 68hc12 support.
* cpu-m68hc11.c, elf32-m68hc11.c: New files for 68hc11 support.
2000-06-18 Ulf Carlsson <ulfc@engr.sgi.com>
* elf_bfd.h (struct elf_backend_data): Add info argument to

14
bfd/Makefile.am
View file

@ -57,6 +57,8 @@ ALL_MACHINES = \
cpu-i860.lo \
cpu-i960.lo \
cpu-m32r.lo \
cpu-m68hc11.lo \
cpu-m68hc12.lo \
cpu-m68k.lo \
cpu-m88k.lo \
cpu-m10200.lo \
@ -96,6 +98,8 @@ ALL_MACHINES_CFILES = \
cpu-i860.c \
cpu-i960.c \
cpu-m32r.c \
cpu-m68hc11.c \
cpu-m68hc12.c \
cpu-m68k.c \
cpu-m88k.c \
cpu-m10200.c \
@ -179,6 +183,8 @@ BFD32_BACKENDS = \
elf32-i860.lo \
elf32-i960.lo \
elf32-m32r.lo \
elf32-m68hc11.lo \
elf32-m68hc12.lo \
elf32-m68k.lo \
elf32-m88k.lo \
elf-m10200.lo \
@ -313,6 +319,8 @@ BFD32_BACKENDS_CFILES = \
elf32-i960.c \
elf32-m32r.c \
elf32-m68k.c \
elf32-m68hc11.c \
elf32-m68hc12.c \
elf32-m88k.c \
elf-m10200.c \
elf-m10300.c \
@ -721,6 +729,8 @@ cpu-i860.lo: cpu-i860.c $(INCDIR)/filenames.h
cpu-i960.lo: cpu-i960.c $(INCDIR)/filenames.h
cpu-m32r.lo: cpu-m32r.c $(INCDIR)/filenames.h
cpu-m68k.lo: cpu-m68k.c $(INCDIR)/filenames.h
cpu-m68hc11.lo: cpu-m68hc11.c $(INCDIR)/filenames.h
cpu-m68hc12.lo: cpu-m68hc12.c $(INCDIR)/filenames.h
cpu-m88k.lo: cpu-m88k.c $(INCDIR)/filenames.h
cpu-m10200.lo: cpu-m10200.c $(INCDIR)/filenames.h
cpu-m10300.lo: cpu-m10300.c $(INCDIR)/filenames.h
@ -913,6 +923,10 @@ elf32-fr30.lo: elf32-fr30.c $(INCDIR)/filenames.h elf-bfd.h \
elf32-gen.lo: elf32-gen.c $(INCDIR)/filenames.h elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h elf32-target.h
elf32-m68hc11.lo: elf32-m68hc11.c $(INCDIR)/bfdlink.h elf-bfd.h \
$(INCDIR)/elf/m68hc11.h elf32-target.h
elf32-m68hc12.lo: elf32-m68hc12.c $(INCDIR)/bfdlink.h elf-bfd.h \
$(INCDIR)/elf/m68hc11.h elf32-target.h
elf32-hppa.lo: elf32-hppa.c $(INCDIR)/filenames.h elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/reloc-macros.h \

16
bfd/Makefile.in
View file

@ -172,6 +172,8 @@ ALL_MACHINES = \
cpu-i860.lo \
cpu-i960.lo \
cpu-m32r.lo \
cpu-m68hc11.lo \
cpu-m68hc12.lo \
cpu-m68k.lo \
cpu-m88k.lo \
cpu-m10200.lo \
@ -212,6 +214,8 @@ ALL_MACHINES_CFILES = \
cpu-i860.c \
cpu-i960.c \
cpu-m32r.c \
cpu-m68hc11.c \
cpu-m68hc12.c \
cpu-m68k.c \
cpu-m88k.c \
cpu-m10200.c \
@ -296,6 +300,8 @@ BFD32_BACKENDS = \
elf32-i860.lo \
elf32-i960.lo \
elf32-m32r.lo \
elf32-m68hc11.lo \
elf32-m68hc12.lo \
elf32-m68k.lo \
elf32-m88k.lo \
elf-m10200.lo \
@ -431,6 +437,8 @@ BFD32_BACKENDS_CFILES = \
elf32-i960.c \
elf32-m32r.c \
elf32-m68k.c \
elf32-m68hc11.c \
elf32-m68hc12.c \
elf32-m88k.c \
elf-m10200.c \
elf-m10300.c \
@ -663,7 +671,7 @@ configure.in
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
TAR = tar
TAR = gtar
GZIP_ENV = --best
SOURCES = $(libbfd_a_SOURCES) $(libbfd_la_SOURCES)
OBJECTS = $(libbfd_a_OBJECTS) $(libbfd_la_OBJECTS)
@ -1249,6 +1257,8 @@ cpu-i860.lo: cpu-i860.c $(INCDIR)/filenames.h
cpu-i960.lo: cpu-i960.c $(INCDIR)/filenames.h
cpu-m32r.lo: cpu-m32r.c $(INCDIR)/filenames.h
cpu-m68k.lo: cpu-m68k.c $(INCDIR)/filenames.h
cpu-m68hc11.lo: cpu-m68hc11.c $(INCDIR)/filenames.h
cpu-m68hc12.lo: cpu-m68hc12.c $(INCDIR)/filenames.h
cpu-m88k.lo: cpu-m88k.c $(INCDIR)/filenames.h
cpu-m10200.lo: cpu-m10200.c $(INCDIR)/filenames.h
cpu-m10300.lo: cpu-m10300.c $(INCDIR)/filenames.h
@ -1441,6 +1451,10 @@ elf32-fr30.lo: elf32-fr30.c $(INCDIR)/filenames.h elf-bfd.h \
elf32-gen.lo: elf32-gen.c $(INCDIR)/filenames.h elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h elf32-target.h
elf32-m68hc11.lo: elf32-m68hc11.c $(INCDIR)/bfdlink.h elf-bfd.h \
$(INCDIR)/elf/m68hc11.h elf32-target.h
elf32-m68hc12.lo: elf32-m68hc12.c $(INCDIR)/bfdlink.h elf-bfd.h \
$(INCDIR)/elf/m68hc11.h elf32-target.h
elf32-hppa.lo: elf32-hppa.c $(INCDIR)/filenames.h elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/reloc-macros.h \

6
bfd/archures.c
View file

@ -174,6 +174,8 @@ DESCRIPTION
.#define bfd_mach_d10v_ts2 2
.#define bfd_mach_d10v_ts3 3
. bfd_arch_d30v, {* Mitsubishi D30V *}
. bfd_arch_m68hc11, {* Motorola 68HC11 *}
. bfd_arch_m68hc12, {* Motorola 68HC12 *}
. bfd_arch_z8k, {* Zilog Z8000 *}
.#define bfd_mach_z8001 1
.#define bfd_mach_z8002 2
@ -279,6 +281,8 @@ extern const bfd_arch_info_type bfd_i386_arch;
extern const bfd_arch_info_type bfd_i860_arch;
extern const bfd_arch_info_type bfd_i960_arch;
extern const bfd_arch_info_type bfd_m32r_arch;
extern const bfd_arch_info_type bfd_m68hc11_arch;
extern const bfd_arch_info_type bfd_m68hc12_arch;
extern const bfd_arch_info_type bfd_m68k_arch;
extern const bfd_arch_info_type bfd_m88k_arch;
extern const bfd_arch_info_type bfd_mips_arch;
@ -322,6 +326,8 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_i860_arch,
&bfd_i960_arch,
&bfd_m32r_arch,
&bfd_m68hc11_arch,
&bfd_m68hc12_arch,
&bfd_m68k_arch,
&bfd_m88k_arch,
&bfd_mips_arch,

16
bfd/bfd-in.h
View file

@ -23,7 +23,7 @@ You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* bfd.h -- The only header file required by users of the bfd library
/* bfd.h -- The only header file required by users of the bfd library
The bfd.h file is generated from bfd-in.h and various .c files; if you
change it, your changes will probably be lost.
@ -109,7 +109,7 @@ typedef enum bfd_boolean {bfd_fffalse, bfd_tttrue} boolean;
/* FIXME: This should be using off_t from <sys/types.h>.
For now, try to avoid breaking stuff by not including <sys/types.h> here.
This will break on systems with 64-bit file offsets (e.g. 4.4BSD).
Probably the best long-term answer is to avoid using file_ptr AND off_t
Probably the best long-term answer is to avoid using file_ptr AND off_t
in this header file, and to handle this in the BFD implementation
rather than in its interface. */
/* typedef off_t file_ptr; */
@ -284,11 +284,11 @@ typedef struct carsym {
file_ptr file_offset; /* look here to find the file */
} carsym; /* to make these you call a carsymogen */
/* Used in generating armaps (archive tables of contents).
Perhaps just a forward definition would do? */
struct orl { /* output ranlib */
char **name; /* symbol name */
char **name; /* symbol name */
file_ptr pos; /* bfd* or file position */
int namidx; /* index into string table */
};
@ -296,7 +296,7 @@ struct orl { /* output ranlib */
/* Linenumber stuff */
typedef struct lineno_cache_entry {
unsigned int line_number; /* Linenumber from start of function*/
unsigned int line_number; /* Linenumber from start of function*/
union {
struct symbol_cache_entry *sym; /* Function name */
unsigned long offset; /* Offset into section */
@ -327,15 +327,15 @@ typedef struct sec *sec_ptr;
#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),true)
#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),true)
typedef struct stat stat_type;
typedef struct stat stat_type;
typedef enum bfd_print_symbol
{
{
bfd_print_symbol_name,
bfd_print_symbol_more,
bfd_print_symbol_all
} bfd_print_symbol_type;
/* Information about a symbol that nm needs. */
typedef struct _symbol_info

30
bfd/bfd-in2.h
View file

@ -23,7 +23,7 @@ You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* bfd.h -- The only header file required by users of the bfd library
/* bfd.h -- The only header file required by users of the bfd library
The bfd.h file is generated from bfd-in.h and various .c files; if you
change it, your changes will probably be lost.
@ -109,7 +109,7 @@ typedef enum bfd_boolean {bfd_fffalse, bfd_tttrue} boolean;
/* FIXME: This should be using off_t from <sys/types.h>.
For now, try to avoid breaking stuff by not including <sys/types.h> here.
This will break on systems with 64-bit file offsets (e.g. 4.4BSD).
Probably the best long-term answer is to avoid using file_ptr AND off_t
Probably the best long-term answer is to avoid using file_ptr AND off_t
in this header file, and to handle this in the BFD implementation
rather than in its interface. */
/* typedef off_t file_ptr; */
@ -284,11 +284,11 @@ typedef struct carsym {
file_ptr file_offset; /* look here to find the file */
} carsym; /* to make these you call a carsymogen */
/* Used in generating armaps (archive tables of contents).
Perhaps just a forward definition would do? */
struct orl { /* output ranlib */
char **name; /* symbol name */
char **name; /* symbol name */
file_ptr pos; /* bfd* or file position */
int namidx; /* index into string table */
};
@ -296,7 +296,7 @@ struct orl { /* output ranlib */
/* Linenumber stuff */
typedef struct lineno_cache_entry {
unsigned int line_number; /* Linenumber from start of function*/
unsigned int line_number; /* Linenumber from start of function*/
union {
struct symbol_cache_entry *sym; /* Function name */
unsigned long offset; /* Offset into section */
@ -327,15 +327,15 @@ typedef struct sec *sec_ptr;
#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),true)
#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),true)
typedef struct stat stat_type;
typedef struct stat stat_type;
typedef enum bfd_print_symbol
{
{
bfd_print_symbol_name,
bfd_print_symbol_more,
bfd_print_symbol_all
} bfd_print_symbol_type;
/* Information about a symbol that nm needs. */
typedef struct _symbol_info
@ -1413,6 +1413,8 @@ enum bfd_architecture
#define bfd_mach_d10v_ts2 2
#define bfd_mach_d10v_ts3 3
bfd_arch_d30v, /* Mitsubishi D30V */
bfd_arch_m68hc11, /* Motorola 68HC11 */
bfd_arch_m68hc12, /* Motorola 68HC12 */
bfd_arch_z8k, /* Zilog Z8000 */
#define bfd_mach_z8001 1
#define bfd_mach_z8002 2
@ -2545,6 +2547,18 @@ this offset in the reloc's section offset. */
BFD_RELOC_IA64_LTOFF_TP22,
BFD_RELOC_IA64_LTOFF22X,
BFD_RELOC_IA64_LDXMOV,
/* Motorola 68HC11 reloc.
This is the 8 bits high part of an absolute address. */
BFD_RELOC_M68HC11_HI8,
/* Motorola 68HC11 reloc.
This is the 8 bits low part of an absolute address. */
BFD_RELOC_M68HC11_LO8,
/* Motorola 68HC11 reloc.
This is the 3 bits of a value. */
BFD_RELOC_M68HC11_3B,
BFD_RELOC_UNUSED };
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
reloc_howto_type *

4
bfd/coff-i386.c
View file

@ -176,19 +176,17 @@ coff_i386_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd,
}
#ifdef COFF_WITH_PE
/* Return true if this relocation should appear in the output .reloc
section. */
static boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *));
static boolean in_reloc_p (abfd, howto)
bfd *abfd ATTRIBUTE_UNUSED;
bfd * abfd ATTRIBUTE_UNUSED;
reloc_howto_type *howto;
{
return ! howto->pc_relative && howto->type != R_IMAGEBASE;
}
#endif /* COFF_WITH_PE */
#ifndef PCRELOFFSET

8
bfd/coff-mcore.c
View file

@ -582,5 +582,9 @@ coff_mcore_relocate_section (output_bfd, info, input_bfd, input_section,
extern const bfd_target TARGET_LITTLE_SYM;
/* The transfer vectors that lead the outside world to all of the above. */
CREATE_BIG_COFF_TARGET_VEC (TARGET_BIG_SYM, TARGET_BIG_NAME, D_PAGED, (SEC_LINK_ONCE | SEC_LINK_DUPLICATES), 0, & TARGET_LITTLE_SYM)
CREATE_LITTLE_COFF_TARGET_VEC (TARGET_LITTLE_SYM, TARGET_LITTLE_NAME, D_PAGED, (SEC_LINK_ONCE | SEC_LINK_DUPLICATES), 0, & TARGET_BIG_SYM)
CREATE_BIG_COFF_TARGET_VEC (TARGET_BIG_SYM, TARGET_BIG_NAME, D_PAGED,
(SEC_CODE | SEC_DATA | SEC_DEBUGGING | SEC_READONLY | SEC_LINK_ONCE | SEC_LINK_DUPLICATES),
0, & TARGET_LITTLE_SYM)
CREATE_LITTLE_COFF_TARGET_VEC (TARGET_LITTLE_SYM, TARGET_LITTLE_NAME, D_PAGED,
(SEC_CODE | SEC_DATA | SEC_DEBUGGING | SEC_READONLY | SEC_LINK_ONCE | SEC_LINK_DUPLICATES),
0, & TARGET_BIG_SYM)

12
bfd/coffcode.h
View file

@ -1466,8 +1466,8 @@ static const unsigned int coff_section_alignment_table_size =
static boolean
coff_new_section_hook (abfd, section)
bfd *abfd;
asection *section;
bfd * abfd;
asection * section;
{
combined_entry_type *native;
@ -3342,7 +3342,7 @@ coff_write_object_contents (abfd)
&& ! is_reloc_section)
hasdebug = true;
#ifdef RS6000COFF_C
#ifdef RS6000COFF_C
#ifndef XCOFF64
/* Indicate the use of an XCOFF overflow section header. */
if (current->reloc_count >= 0xffff || current->lineno_count >= 0xffff)
@ -3395,7 +3395,7 @@ coff_write_object_contents (abfd)
SCNHDR buff;
if (coff_swap_scnhdr_out (abfd, &section, &buff) == 0
|| bfd_write ((PTR) (&buff), 1, bfd_coff_scnhsz (abfd), abfd)
!= bfd_coff_scnhsz (abfd))
!= bfd_coff_scnhsz (abfd))
return false;
}
@ -3517,7 +3517,7 @@ coff_write_object_contents (abfd)
scnhdr.s_flags = STYP_OVRFLO;
if (coff_swap_scnhdr_out (abfd, &scnhdr, &buff) == 0
|| bfd_write ((PTR) &buff, 1, bfd_coff_scnhsz (abfd), abfd)
!= bfd_coff_scnhsz (abfd))
!= bfd_coff_scnhsz (abfd))
return false;
}
}
@ -4438,7 +4438,7 @@ coff_slurp_symbol_table (abfd)
#endif
case C_BLOCK: /* ".bb" or ".eb" */
case C_FCN: /* ".bf" or ".ef" (or PE ".lf") */
case C_FCN: /* ".bf" or ".ef" (or PE ".lf") */
case C_EFCN: /* physical end of function */
#if defined COFF_WITH_PE
/* PE sets the symbol to a value relative to the start

2
bfd/cofflink.c
View file

@ -2201,7 +2201,7 @@ _bfd_coff_link_input_bfd (finfo, input_bfd)
is.n_numaux, auxptr);
}
skipping = false;
skipping = false;
}
iline.l_addr.l_symndx = indx;

17
bfd/config.bfd
View file

@ -37,6 +37,8 @@ c54x*) targ_archs=bfd_tic54x_arch ;;
hppa*) targ_archs=bfd_hppa_arch ;;
i[3456]86) targ_archs=bfd_i386_arch ;;
i370) targ_archs=bfd_i370_arch ;;
m6811*|m68hc11*) targ_archs="bfd_m68hc11_arch bfd_m68hc12_arch" ;;
m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch" ;;
m68*) targ_archs=bfd_m68k_arch ;;
m88*) targ_archs=bfd_m88k_arch ;;
mips*) targ_archs=bfd_mips_arch ;;
@ -118,7 +120,7 @@ case "${targ}" in
targ_selvecs="armpe_little_vec armpe_big_vec armpei_little_vec armpei_big_vec"
targ_underscore=yes
;;
arm-*-aout | armel-*-aout)
arm-*-aout | armel-*-aout)
targ_defvec=aout_arm_little_vec
targ_selvecs=aout_arm_big_vec
;;
@ -231,7 +233,7 @@ case "${targ}" in
hppa*-*-*elf* | hppa*-*-linux-gnu* | hppa*-*-lites* | hppa*-*-sysv4* | hppa*-*-rtems*)
targ_defvec=bfd_elf32_hppa_vec
;;
#ifdef BFD64
#ifdef BFD64
hppa*64*-*-hpux11*)
targ_defvec=bfd_elf64_hppa_vec
targ_cflags=-DHPUX_LARGE_AR_IDS
@ -404,6 +406,15 @@ case "${targ}" in
targ_defvec=bfd_elf32_m32r_vec
;;
m68hc11-*-* | m6811-*-*)
targ_defvec=bfd_elf32_m68hc11_vec
targ_selvecs="bfd_elf32_m68hc11_vec bfd_elf32_m68hc12_vec"
;;
m68hc12-*-* | m6812-*-*)
targ_defvec=bfd_elf32_m68hc12_vec
targ_selvecs="bfd_elf32_m68hc11_vec bfd_elf32_m68hc12_vec"
;;
m68*-apollo-*)
targ_defvec=apollocoff_vec
;;
@ -740,7 +751,7 @@ case "${targ}" in
sparc64-*-elf*)
targ_defvec=bfd_elf64_sparc_vec
targ_selvecs=bfd_elf32_sparc_vec
;;
;;
#endif /* BFD64 */
sparc*-*-coff*)
targ_defvec=sparccoff_vec

30
bfd/configure vendored
View file

@ -5144,6 +5144,8 @@ do
bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elf32-mips.lo elf32.lo $elf ecofflink.lo"
target64=true ;;
bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m68hc11_vec) tb="$tb elf32-m68hc11.lo elf32.lo $elf" ;;
bfd_elf32_m68hc12_vec) tb="$tb elf32-m68hc12.lo elf32.lo $elf" ;;
bfd_elf32_m68k_vec) tb="$tb elf32-m68k.lo elf32.lo $elf" ;;
bfd_elf32_m88k_vec) tb="$tb elf32-m88k.lo elf32.lo $elf" ;;
bfd_elf32_mcore_big_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;;
@ -5236,8 +5238,8 @@ do
shlcoff_vec) tb="$tb coff-sh.lo cofflink.lo" ;;
shcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;;
shlcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;;
shlpe_vec) tb="$tb pe-sh.lo coff-sh.lo cofflink.lo" ;;
shlpei_vec) tb="$tb pei-sh.lo coff-sh.lo cofflink.lo" ;;
shlpe_vec) tb="$tb pe-sh.lo coff-sh.lo peigen.lo cofflink.lo" ;;
shlpei_vec) tb="$tb pei-sh.lo coff-sh.lo peigen.lo cofflink.lo" ;;
som_vec) tb="$tb som.lo" ;;
sparcle_aout_vec) tb="$tb aout-sparcle.lo aout32.lo" ;;
sparclinux_vec) tb="$tb sparclinux.lo aout32.lo" ;;
@ -5346,17 +5348,17 @@ for ac_hdr in unistd.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
echo "configure:5350: checking for $ac_hdr" >&5
echo "configure:5352: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 5355 "configure"
#line 5357 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:5360: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:5362: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -5385,12 +5387,12 @@ done
for ac_func in getpagesize
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:5389: checking for $ac_func" >&5
echo "configure:5391: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 5394 "configure"
#line 5396 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@ -5413,7 +5415,7 @@ $ac_func();
; return 0; }
EOF
if { (eval echo configure:5417: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:5419: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@ -5438,7 +5440,7 @@ fi
done
echo $ac_n "checking for working mmap""... $ac_c" 1>&6
echo "configure:5442: checking for working mmap" >&5
echo "configure:5444: checking for working mmap" >&5
if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -5446,7 +5448,7 @@ else
ac_cv_func_mmap_fixed_mapped=no
else
cat > conftest.$ac_ext <<EOF
#line 5450 "configure"
#line 5452 "configure"
#include "confdefs.h"
/* Thanks to Mike Haertel and Jim Avera for this test.
@ -5586,7 +5588,7 @@ main()
}
EOF
if { (eval echo configure:5590: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
if { (eval echo configure:5592: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_func_mmap_fixed_mapped=yes
else
@ -5611,12 +5613,12 @@ fi
for ac_func in madvise mprotect
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:5615: checking for $ac_func" >&5
echo "configure:5617: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 5620 "configure"
#line 5622 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@ -5639,7 +5641,7 @@ $ac_func();
; return 0; }
EOF
if { (eval echo configure:5643: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:5645: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else

6
bfd/configure.in
View file

@ -501,6 +501,8 @@ do
bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elf32-mips.lo elf32.lo $elf ecofflink.lo"
target64=true ;;
bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m68hc11_vec) tb="$tb elf32-m68hc11.lo elf32.lo $elf" ;;
bfd_elf32_m68hc12_vec) tb="$tb elf32-m68hc12.lo elf32.lo $elf" ;;
bfd_elf32_m68k_vec) tb="$tb elf32-m68k.lo elf32.lo $elf" ;;
bfd_elf32_m88k_vec) tb="$tb elf32-m88k.lo elf32.lo $elf" ;;
bfd_elf32_mcore_big_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;;
@ -593,8 +595,8 @@ do
shlcoff_vec) tb="$tb coff-sh.lo cofflink.lo" ;;
shcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;;
shlcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;;
shlpe_vec) tb="$tb pe-sh.lo coff-sh.lo cofflink.lo" ;;
shlpei_vec) tb="$tb pei-sh.lo coff-sh.lo cofflink.lo" ;;
shlpe_vec) tb="$tb pe-sh.lo coff-sh.lo peigen.lo cofflink.lo" ;;
shlpei_vec) tb="$tb pei-sh.lo coff-sh.lo peigen.lo cofflink.lo" ;;
som_vec) tb="$tb som.lo" ;;
sparcle_aout_vec) tb="$tb aout-sparcle.lo aout32.lo" ;;
sparclinux_vec) tb="$tb sparclinux.lo aout32.lo" ;;

39
bfd/cpu-m68hc11.c Normal file
View file

@ -0,0 +1,39 @@
/* BFD support for the Motorola 68HC11 processor
Copyright 1999, 2000 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
const bfd_arch_info_type bfd_m68hc11_arch =
{
16, /* 16 bits in a word */
16, /* 16 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_m68hc11,
0,
"m68hc11",
"m68hc11",
4, /* section alignment power */
true,
bfd_default_compatible,
bfd_default_scan,
0,
};

38
bfd/cpu-m68hc12.c Normal file
View file

@ -0,0 +1,38 @@
/* BFD support for the Motorola 68HC12 processor
Copyright 1999, 2000 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
const bfd_arch_info_type bfd_m68hc12_arch =
{
16, /* 16 bits in a word */
16, /* 16 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_m68hc12,
0,
"m68hc12",
"m68hc12",
4, /* section alignment power */
true,
bfd_default_compatible,
bfd_default_scan,
0,
};

2
bfd/doc/Makefile.in
View file

@ -188,7 +188,7 @@ DIST_COMMON = ChangeLog Makefile.am Makefile.in
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
TAR = tar
TAR = gtar
GZIP_ENV = --best
all: all-redirect
.SUFFIXES:

20
bfd/elf-bfd.h
View file

@ -373,8 +373,8 @@ struct elf_backend_data
/* A function to set the type of the info field. Processor-specific
types should be handled here. */
int (*elf_backend_get_symbol_type) PARAMS (( Elf_Internal_Sym *, int));
int (*elf_backend_get_symbol_type) PARAMS (( Elf_Internal_Sym *, int));
/* A function to do additional processing on the ELF section header
just before writing it out. This is used to set the flags and
type fields for some sections, or to actually write out data for
@ -638,7 +638,7 @@ struct elf_backend_data
both REL and RELA relocations, and this flag is set for those
backends.) */
unsigned may_use_rel_p : 1;
/* Whether the backend may use RELA relocations. (Some backends use
both REL and RELA relocations, and this flag is set for those
backends.) */
@ -647,8 +647,8 @@ struct elf_backend_data
/* Whether the default relocation type is RELA. If a backend with
this flag set wants REL relocations for a particular section,
it must note that explicitly. Similarly, if this flag is clear,
and the backend wants RELA relocations for a particular
section. */
and the backend wants RELA relocations for a particular
section. */
unsigned default_use_rela_p : 1;
/* True if addresses "naturally" sign extend. This is used when
@ -1013,7 +1013,7 @@ extern boolean _bfd_elf_find_nearest_line PARAMS ((bfd *, asection *,
#define _bfd_elf_minisymbol_to_symbol _bfd_generic_minisymbol_to_symbol
extern int _bfd_elf_sizeof_headers PARAMS ((bfd *, boolean));
extern boolean _bfd_elf_new_section_hook PARAMS ((bfd *, asection *));
extern boolean _bfd_elf_init_reloc_shdr
extern boolean _bfd_elf_init_reloc_shdr
PARAMS ((bfd *, Elf_Internal_Shdr *, asection *, boolean));
/* If the target doesn't have reloc handling written yet: */
@ -1282,11 +1282,11 @@ extern boolean _bfd_mips_elf_finish_dynamic_symbol
Elf_Internal_Sym *));
extern boolean _bfd_mips_elf_finish_dynamic_sections
PARAMS ((bfd *, struct bfd_link_info *));
extern asection * _bfd_mips_elf_gc_mark_hook
extern asection * _bfd_mips_elf_gc_mark_hook
PARAMS ((bfd *, struct bfd_link_info *, Elf_Internal_Rela *,
struct elf_link_hash_entry *, Elf_Internal_Sym *));
extern boolean _bfd_mips_elf_gc_sweep_hook
PARAMS ((bfd *, struct bfd_link_info *, asection *,
extern boolean _bfd_mips_elf_gc_sweep_hook
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
extern boolean _bfd_mips_elf_always_size_sections
PARAMS ((bfd *, struct bfd_link_info *));
@ -1297,7 +1297,7 @@ extern boolean _bfd_mips_elf_check_relocs
const Elf_Internal_Rela *));
extern struct bfd_link_hash_table *_bfd_mips_elf_link_hash_table_create
PARAMS ((bfd *));
extern boolean _bfd_mips_elf_print_private_bfd_data
extern boolean _bfd_mips_elf_print_private_bfd_data
PARAMS ((bfd *, PTR));
extern boolean _bfd_mips_elf_link_output_symbol_hook
PARAMS ((bfd *, struct bfd_link_info *, const char *, Elf_Internal_Sym *,

12
bfd/elf.c
View file

@ -1333,8 +1333,10 @@ bfd_section_from_shdr (abfd, shindex)
/* If this reloc section does not use the main symbol table we
don't treat it as a reloc section. BFD can't adequately
represent such a section, so at least for now, we don't
try. We just present it as a normal section. */
if (hdr->sh_link != elf_onesymtab (abfd))
try. We just present it as a normal section. We also
can't use it as a reloc section if it points to the null
section. */
if (hdr->sh_link != elf_onesymtab (abfd) || hdr->sh_info == SHN_UNDEF)
return _bfd_elf_make_section_from_shdr (abfd, hdr, name);
if (! bfd_section_from_shdr (abfd, hdr->sh_info))
@ -3265,6 +3267,12 @@ prep_headers (abfd)
case bfd_arch_ia64:
i_ehdrp->e_machine = EM_IA_64;
break;
case bfd_arch_m68hc11:
i_ehdrp->e_machine = EM_68HC11;
break;
case bfd_arch_m68hc12:
i_ehdrp->e_machine = EM_68HC12;
break;
case bfd_arch_m68k:
i_ehdrp->e_machine = EM_68K;
break;

281
bfd/elf32-m68hc11.c Normal file
View file

@ -0,0 +1,281 @@
/* Motorola 68HC11-specific support for 32-bit ELF
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
Contributed by Stephane Carrez (stcarrez@worldnet.fr)
(Heavily copied from the D10V port by Martin Hunt (hunt@cygnus.com))
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
#include "elf-bfd.h"
#include "elf/m68hc11.h"
static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
PARAMS ((bfd * abfd, bfd_reloc_code_real_type code));
static void m68hc11_info_to_howto_rel
PARAMS ((bfd *, arelent *, Elf32_Internal_Rel *));
/* Use REL instead of RELA to save space */
#define USE_REL
/* The Motorola 68HC11 microcontroler only addresses 64Kb.
We must handle 8 and 16-bit relocations. The 32-bit relocation
is defined but not used except by gas when -gstabs is used (which
is wrong).
The 3-bit and 16-bit PC rel relocation is only used by 68HC12. */
static reloc_howto_type elf_m68hc11_howto_table[] = {
/* This reloc does nothing. */
HOWTO (R_M68HC11_NONE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_NONE", /* name */
false, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
false), /* pcrel_offset */
/* A 8 bit absolute relocation */
HOWTO (R_M68HC11_8, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_8", /* name */
false, /* partial_inplace */
0x00ff, /* src_mask */
0x00ff, /* dst_mask */
false), /* pcrel_offset */
/* A 8 bit absolute relocation (upper address) */
HOWTO (R_M68HC11_HI8, /* type */
8, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_HI8", /* name */
false, /* partial_inplace */
0x00ff, /* src_mask */
0x00ff, /* dst_mask */
false), /* pcrel_offset */
/* A 8 bit absolute relocation (upper address) */
HOWTO (R_M68HC11_LO8, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_LO8", /* name */
false, /* partial_inplace */
0x00ff, /* src_mask */
0x00ff, /* dst_mask */
false), /* pcrel_offset */
/* A 8 bit PC-rel relocation */
HOWTO (R_M68HC11_PCREL_8, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
true, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_PCREL_8", /* name */
false, /* partial_inplace */
0x0, /* src_mask */
0x00ff, /* dst_mask */
false), /* pcrel_offset */
/* A 16 bit absolute relocation */
HOWTO (R_M68HC11_16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont /*bitfield */ , /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_16", /* name */
false, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
false), /* pcrel_offset */
/* A 32 bit absolute relocation. This one is never used for the
code relocation. It's used by gas for -gstabs generation. */
HOWTO (R_M68HC11_32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_32", /* name */
false, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
false), /* pcrel_offset */
/* A 3 bit absolute relocation */
HOWTO (R_M68HC11_3B, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
3, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_4B", /* name */
false, /* partial_inplace */
0x003, /* src_mask */
0x003, /* dst_mask */
false), /* pcrel_offset */
/* A 16 bit PC-rel relocation */
HOWTO (R_M68HC11_PCREL_16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
true, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_PCREL_16", /* name */
false, /* partial_inplace */
0x0, /* src_mask */
0xffff, /* dst_mask */
false), /* pcrel_offset */
/* GNU extension to record C++ vtable hierarchy */
HOWTO (R_M68HC11_GNU_VTINHERIT, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
NULL, /* special_function */
"R_M68HC11_GNU_VTINHERIT", /* name */
false, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
false), /* pcrel_offset */
/* GNU extension to record C++ vtable member usage */
HOWTO (R_M68HC11_GNU_VTENTRY, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
_bfd_elf_rel_vtable_reloc_fn, /* special_function */
"R_M68HC11_GNU_VTENTRY", /* name */
false, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
false), /* pcrel_offset */
};
/* Map BFD reloc types to M68HC11 ELF reloc types. */
struct m68hc11_reloc_map
{
bfd_reloc_code_real_type bfd_reloc_val;
unsigned char elf_reloc_val;
};
static const struct m68hc11_reloc_map m68hc11_reloc_map[] = {
{BFD_RELOC_NONE, R_M68HC11_NONE,},
{BFD_RELOC_8, R_M68HC11_8},
{BFD_RELOC_M68HC11_HI8, R_M68HC11_HI8},
{BFD_RELOC_M68HC11_LO8, R_M68HC11_LO8},
{BFD_RELOC_8_PCREL, R_M68HC11_PCREL_8},
{BFD_RELOC_16_PCREL, R_M68HC11_PCREL_16},
{BFD_RELOC_16, R_M68HC11_16},
{BFD_RELOC_32, R_M68HC11_32},
{BFD_RELOC_M68HC11_3B, R_M68HC11_3B},
/* The following relocs are defined but they probably don't work yet. */
{BFD_RELOC_VTABLE_INHERIT, R_M68HC11_GNU_VTINHERIT},
{BFD_RELOC_VTABLE_ENTRY, R_M68HC11_GNU_VTENTRY},
};
static reloc_howto_type *
bfd_elf32_bfd_reloc_type_lookup (abfd, code)
bfd *abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
{
unsigned int i;
for (i = 0;
i < sizeof (m68hc11_reloc_map) / sizeof (struct m68hc11_reloc_map);
i++)
{
if (m68hc11_reloc_map[i].bfd_reloc_val == code)
return &elf_m68hc11_howto_table[m68hc11_reloc_map[i].elf_reloc_val];
}
return NULL;
}
/* Set the howto pointer for an M68HC11 ELF reloc. */
static void
m68hc11_info_to_howto_rel (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf32_Internal_Rel *dst;
{
unsigned int r_type;
r_type = ELF32_R_TYPE (dst->r_info);
BFD_ASSERT (r_type < (unsigned int) R_M68HC11_max);
cache_ptr->howto = &elf_m68hc11_howto_table[r_type];
}
/* Below is the only difference between elf32-m68hc12.c and elf32-m68hc11.c.
The Motorola spec says to use a different Elf machine code. */
#define ELF_ARCH bfd_arch_m68hc11
#define ELF_MACHINE_CODE EM_68HC11
#define ELF_MAXPAGESIZE 0x1000
#define TARGET_BIG_SYM bfd_elf32_m68hc11_vec
#define TARGET_BIG_NAME "elf32-m68hc11"
#define elf_info_to_howto 0
#define elf_info_to_howto_rel m68hc11_info_to_howto_rel
#define elf_backend_object_p 0
#define elf_backend_final_write_processing 0
#include "elf32-target.h"

281
bfd/elf32-m68hc12.c Normal file
View file

@ -0,0 +1,281 @@
/* Motorola 68HC12-specific support for 32-bit ELF
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
Contributed by Stephane Carrez (stcarrez@worldnet.fr)
(Heavily copied from the D10V port by Martin Hunt (hunt@cygnus.com))
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
#include "elf-bfd.h"
#include "elf/m68hc11.h"
static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
PARAMS ((bfd * abfd, bfd_reloc_code_real_type code));
static void m68hc11_info_to_howto_rel
PARAMS ((bfd *, arelent *, Elf32_Internal_Rel *));
/* Use REL instead of RELA to save space */
#define USE_REL
/* The Motorola 68HC11 microcontroler only addresses 64Kb.
We must handle 8 and 16-bit relocations. The 32-bit relocation
is defined but not used except by gas when -gstabs is used (which
is wrong).
The 3-bit and 16-bit PC rel relocation is only used by 68HC12. */
static reloc_howto_type elf_m68hc11_howto_table[] = {
/* This reloc does nothing. */
HOWTO (R_M68HC11_NONE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_NONE", /* name */
false, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
false), /* pcrel_offset */
/* A 8 bit absolute relocation */
HOWTO (R_M68HC11_8, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_8", /* name */
false, /* partial_inplace */
0x00ff, /* src_mask */
0x00ff, /* dst_mask */
false), /* pcrel_offset */
/* A 8 bit absolute relocation (upper address) */
HOWTO (R_M68HC11_HI8, /* type */
8, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_HI8", /* name */
false, /* partial_inplace */
0x00ff, /* src_mask */
0x00ff, /* dst_mask */
false), /* pcrel_offset */
/* A 8 bit absolute relocation (upper address) */
HOWTO (R_M68HC11_LO8, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_LO8", /* name */
false, /* partial_inplace */
0x00ff, /* src_mask */
0x00ff, /* dst_mask */
false), /* pcrel_offset */
/* A 8 bit PC-rel relocation */
HOWTO (R_M68HC11_PCREL_8, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
true, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_PCREL_8", /* name */
false, /* partial_inplace */
0x0, /* src_mask */
0x00ff, /* dst_mask */
false), /* pcrel_offset */
/* A 16 bit absolute relocation */
HOWTO (R_M68HC11_16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont /*bitfield */ , /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_16", /* name */
false, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
false), /* pcrel_offset */
/* A 32 bit absolute relocation. This one is never used for the
code relocation. It's used by gas for -gstabs generation. */
HOWTO (R_M68HC11_32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_32", /* name */
false, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
false), /* pcrel_offset */
/* A 3 bit absolute relocation */
HOWTO (R_M68HC11_3B, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
3, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_4B", /* name */
false, /* partial_inplace */
0x003, /* src_mask */
0x003, /* dst_mask */
false), /* pcrel_offset */
/* A 16 bit PC-rel relocation */
HOWTO (R_M68HC11_PCREL_16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
true, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_M68HC11_PCREL_16", /* name */
false, /* partial_inplace */
0x0, /* src_mask */
0xffff, /* dst_mask */
false), /* pcrel_offset */
/* GNU extension to record C++ vtable hierarchy */
HOWTO (R_M68HC11_GNU_VTINHERIT, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
NULL, /* special_function */
"R_M68HC11_GNU_VTINHERIT", /* name */
false, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
false), /* pcrel_offset */
/* GNU extension to record C++ vtable member usage */
HOWTO (R_M68HC11_GNU_VTENTRY, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
_bfd_elf_rel_vtable_reloc_fn, /* special_function */
"R_M68HC11_GNU_VTENTRY", /* name */
false, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
false), /* pcrel_offset */
};
/* Map BFD reloc types to M68HC11 ELF reloc types. */
struct m68hc11_reloc_map
{
bfd_reloc_code_real_type bfd_reloc_val;
unsigned char elf_reloc_val;
};
static const struct m68hc11_reloc_map m68hc11_reloc_map[] = {
{BFD_RELOC_NONE, R_M68HC11_NONE,},
{BFD_RELOC_8, R_M68HC11_8},
{BFD_RELOC_M68HC11_HI8, R_M68HC11_HI8},
{BFD_RELOC_M68HC11_LO8, R_M68HC11_LO8},
{BFD_RELOC_8_PCREL, R_M68HC11_PCREL_8},
{BFD_RELOC_16_PCREL, R_M68HC11_PCREL_16},
{BFD_RELOC_16, R_M68HC11_16},
{BFD_RELOC_32, R_M68HC11_32},
{BFD_RELOC_M68HC11_3B, R_M68HC11_3B},
/* The following relocs are defined but they probably don't work yet. */
{BFD_RELOC_VTABLE_INHERIT, R_M68HC11_GNU_VTINHERIT},
{BFD_RELOC_VTABLE_ENTRY, R_M68HC11_GNU_VTENTRY},
};
static reloc_howto_type *
bfd_elf32_bfd_reloc_type_lookup (abfd, code)
bfd *abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
{
unsigned int i;
for (i = 0;
i < sizeof (m68hc11_reloc_map) / sizeof (struct m68hc11_reloc_map);
i++)
{
if (m68hc11_reloc_map[i].bfd_reloc_val == code)
return &elf_m68hc11_howto_table[m68hc11_reloc_map[i].elf_reloc_val];
}
return NULL;
}
/* Set the howto pointer for an M68HC11 ELF reloc. */
static void
m68hc11_info_to_howto_rel (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf32_Internal_Rel *dst;
{
unsigned int r_type;
r_type = ELF32_R_TYPE (dst->r_info);
BFD_ASSERT (r_type < (unsigned int) R_M68HC11_max);
cache_ptr->howto = &elf_m68hc11_howto_table[r_type];
}
/* Below is the only difference between elf32-m68hc12.c and elf32-m68hc11.c.
The Motorola spec says to use a different Elf machine code. */
#define ELF_ARCH bfd_arch_m68hc12
#define ELF_MACHINE_CODE EM_68HC12
#define ELF_MAXPAGESIZE 0x1000
#define TARGET_BIG_SYM bfd_elf32_m68hc12_vec
#define TARGET_BIG_NAME "elf32-m68hc12"
#define elf_info_to_howto 0
#define elf_info_to_howto_rel m68hc11_info_to_howto_rel
#define elf_backend_object_p 0
#define elf_backend_final_write_processing 0
#include "elf32-target.h"

16
bfd/elfcode.h
View file

@ -167,7 +167,7 @@ static void elf_swap_shdr_out
#define section_from_elf_index bfd_section_from_elf_index
static boolean elf_slurp_reloc_table_from_section
static boolean elf_slurp_reloc_table_from_section
PARAMS ((bfd *, asection *, Elf_Internal_Shdr *, bfd_size_type,
arelent *, asymbol **, boolean));
@ -1224,7 +1224,7 @@ error_return:
return -1;
}
/* Read relocations for ASECT from REL_HDR. There are RELOC_COUNT of
/* Read relocations for ASECT from REL_HDR. There are RELOC_COUNT of
them. */
static boolean
@ -1349,7 +1349,7 @@ elf_slurp_reloc_table (abfd, asect, symbols, dynamic)
rel_hdr = &d->rel_hdr;
reloc_count = rel_hdr->sh_size / rel_hdr->sh_entsize;
rel_hdr2 = d->rel_hdr2;
reloc_count2 = (rel_hdr2
reloc_count2 = (rel_hdr2
? (rel_hdr2->sh_size / rel_hdr2->sh_entsize)
: 0);
@ -1373,8 +1373,8 @@ elf_slurp_reloc_table (abfd, asect, symbols, dynamic)
reloc_count2 = 0;
}
relents = ((arelent *)
bfd_alloc (abfd,
relents = ((arelent *)
bfd_alloc (abfd,
(reloc_count + reloc_count2) * sizeof (arelent)));
if (relents == NULL)
return false;
@ -1384,15 +1384,15 @@ elf_slurp_reloc_table (abfd, asect, symbols, dynamic)
relents,
symbols, dynamic))
return false;
if (rel_hdr2
if (rel_hdr2
&& !elf_slurp_reloc_table_from_section (abfd, asect,
rel_hdr2, reloc_count2,
relents + reloc_count,
symbols, dynamic))
return false;
asect->relocation = relents;
return true;
}

4
bfd/elfcore.h
View file

@ -99,9 +99,7 @@ elf_core_file_p (abfd)
/* Check the magic number. */
if (elf_file_p (&x_ehdr) == false)
{
goto wrong;
}
goto wrong;
/* FIXME: Check EI_VERSION here ! */

1
bfd/elfxx-target.h
View file

@ -313,7 +313,6 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define elf_backend_hide_symbol _bfd_elf_link_hash_hide_symbol
#endif
/* Previously, backends could only use SHT_REL or SHT_RELA relocation
sections, but not both. They defined USE_REL to indicate SHT_REL
sections, and left it undefined to indicated SHT_RELA sections.

3
bfd/libbfd.h
View file

@ -965,6 +965,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_IA64_LTOFF_TP22",
"BFD_RELOC_IA64_LTOFF22X",
"BFD_RELOC_IA64_LDXMOV",
"BFD_RELOC_M68HC11_HI8",
"BFD_RELOC_M68HC11_LO8",
"BFD_RELOC_M68HC11_3B",
"@@overflow: BFD_RELOC_UNUSED@@",
};
#endif

2
bfd/peicode.h
View file

@ -69,7 +69,6 @@ static boolean (*pe_saved_coff_bfd_print_private_bfd_data)
static boolean pe_print_private_bfd_data PARAMS ((bfd *, PTR));
#define coff_bfd_print_private_bfd_data pe_print_private_bfd_data
static boolean (*pe_saved_coff_bfd_copy_private_bfd_data)
PARAMS ((bfd *, bfd *)) =
#ifndef coff_bfd_copy_private_bfd_data
@ -243,7 +242,6 @@ coff_swap_filehdr_in (abfd, src, dst)
#define coff_swap_filehdr_out _bfd_pe_only_swap_filehdr_out
#endif
static void
coff_swap_scnhdr_in (abfd, ext, in)
bfd *abfd;

74
bfd/po/POTFILES.in
View file

@ -1,14 +1,14 @@
aix386-core.c
aout0.c
aout32.c
aout64.c
aout-adobe.c
aout-arm.c
aoutf1.h
aout-ns32k.c
aout-sparcle.c
aout-target.h
aout-tic30.c
aout0.c
aout32.c
aout64.c
aoutf1.h
aoutx.h
archive.c
archures.c
@ -21,17 +21,21 @@ cf-i386lynx.c
cf-m68klynx.c
cf-sparclynx.c
cisco-core.c
coff64-rs6000.c
coff-a29k.c
coff-alpha.c
coff-apollo.c
coff-arm.c
coff-aux.c
coffcode.h
coffgen.c
coff-go32.c
coff-h8300.c
coff-h8500.c
coff-i386.c
coff-i860.c
coff-i960.c
cofflink.c
coff-m68k.c
coff-m88k.c
coff-mips.c
@ -41,21 +45,20 @@ coff-sh.c
coff-sparc.c
coff-stgo32.c
coff-svm68k.c
coffswap.h
coff-tic30.c
coff-tic54x.c
coff-tic80.c
coff-u68k.c
coff-w65.c
coff-we32k.c
coff-z8k.c
coffcode.h
coffgen.c
cofflink.c
coffswap.h
corefile.c
cpu-a29k.c
cpu-alpha.c
cpu-arc.c
cpu-arm.c
cpu-avr.c
cpu-d10v.c
cpu-d30v.c
cpu-fr30.c
@ -66,9 +69,12 @@ cpu-i370.c
cpu-i386.c
cpu-i860.c
cpu-i960.c
cpu-ia64.c
cpu-m10200.c
cpu-m10300.c
cpu-m32r.c
cpu-m68hc11.c
cpu-m68hc12.c
cpu-m68k.c
cpu-m88k.c
cpu-mcore.c
@ -80,6 +86,7 @@ cpu-rs6000.c
cpu-sh.c
cpu-sparc.c
cpu-tic30.c
cpu-tic54x.c
cpu-tic80.c
cpu-v850.c
cpu-vax.c
@ -92,21 +99,25 @@ dwarf2.c
ecoff.c
ecofflink.c
ecoffswap.h
elf-bfd.h
elf-m10200.c
elf-m10300.c
elf.c
efi-app-ia32.c
efi-app-ia64.c
elf32-arc.c
elf32-arm.h
elf32-avr.c
elf32.c
elf32-d10v.c
elf32-d30v.c
elf32-fr30.c
elf32-gen.c
elf32-hppa.c
elf32-hppa.h
elf32-i370.c
elf32-i386.c
elf32-i860.c
elf32-i960.c
elf32-m32r.c
elf32-m68hc11.c
elf32-m68hc12.c
elf32-m68k.c
elf32-m88k.c
elf32-mcore.c
@ -116,20 +127,25 @@ elf32-ppc.c
elf32-sh.c
elf32-sparc.c
elf32-v850.c
elf32.c
elf64-alpha.c
elf64.c
elf64-gen.c
elf64-hppa.c
elf64-hppa.h
elf64-ia64.c
elf64-mips.c
elf64-sparc.c
elf64.c
elfarm-nabi.c
elfarm-oabi.c
elf-bfd.h
elf.c
elfcode.h
elfcore.h
elf-hppa.h
elflink.c
elflink.h
elf-m10200.c
elf-m10300.c
epoc-pe-arm.c
epoc-pei-arm.c
format.c
@ -139,6 +155,7 @@ go32stub.h
hash.c
hp300bsd.c
hp300hpux.c
hppa_stubs.h
hpux-core.c
i386aout.c
i386bsd.c
@ -174,16 +191,16 @@ m88kmach3.c
mipsbsd.c
netbsd.h
newsos3.c
nlm-target.h
nlm.c
nlm32-alpha.c
nlm32.c
nlm32-i386.c
nlm32-ppc.c
nlm32-sparc.c
nlm32.c
nlm64.c
nlm.c
nlmcode.h
nlmswap.h
nlm-target.h
ns32k.h
ns32knetbsd.c
oasys.c
@ -192,17 +209,21 @@ osf-core.c
pc532-mach.c
pe-arm.c
pe-i386.c
pe-mcore.c
pe-ppc.c
pei-arm.c
pei-i386.c
pei-mcore.c
pei-ppc.c
peicode.h
peigen.c
pei-i386.c
pei-mcore.c
pei-mips.c
pei-ppc.c
pei-sh.c
pe-mcore.c
pe-mips.c
pe-ppc.c
pe-sh.c
ppcboot.c
reloc.c
reloc16.c
reloc.c
riscix.c
sco5-core.c
section.c
@ -212,8 +233,8 @@ sparclinux.c
sparclynx.c
sparcnetbsd.c
srec.c
stab-syms.c
stabs.c
stab-syms.c
sunos.c
syms.c
targets.c
@ -221,10 +242,11 @@ tekhex.c
trad-core.c
vaxnetbsd.c
versados.c
vms.c
vms-gsd.c
vms.h
vms-hdr.c
vms-misc.c
vms-tir.c
vms.c
vms.h
xcofflink.c
xcoff-target.h

945
bfd/po/bfd.pot
View file

File diff suppressed because it is too large Load diff

17
bfd/reloc.c
View file

@ -2881,6 +2881,23 @@ ENUMX
BFD_RELOC_IA64_LDXMOV
ENUMDOC
Intel IA64 Relocations.
ENUM
BFD_RELOC_M68HC11_HI8
ENUMDOC
Motorola 68HC11 reloc.
This is the 8 bits high part of an absolute address.
ENUM
BFD_RELOC_M68HC11_LO8
ENUMDOC
Motorola 68HC11 reloc.
This is the 8 bits low part of an absolute address.
ENUM
BFD_RELOC_M68HC11_3B
ENUMDOC
Motorola 68HC11 reloc.
This is the 3 bits of a value.
ENDSENUM
BFD_RELOC_UNUSED
CODE_FRAGMENT

12
bfd/section.c
View file

@ -552,25 +552,25 @@ static const asymbol global_syms[] =
const asymbol * const SYM = (asymbol *) &global_syms[IDX]; \
const asection SEC = \
/* name, index, next, flags, set_vma, reloc_done, linker_mark, gc_mark */ \
{ NAME, 0, 0, FLAGS, 0, 0, 0, 0, \
{ NAME, 0, NULL, FLAGS, 0, 0, 0, 0, \
\
/* vma, lma, _cooked_size, _raw_size, output_offset, output_section, */ \
0, 0, 0, 0, 0, (struct sec *) &SEC, \
\
/* alig..., reloc..., orel..., reloc_count, filepos, rel_..., line_... */ \
0, 0, 0, 0, 0, 0, 0, \
0, NULL, NULL, 0, 0, 0, 0, \
\
/* userdata, contents, lineno, lineno_count */ \
0, 0, 0, 0, \
NULL, NULL, NULL, 0, \
\
/* comdat_info, moving_line_filepos, target_index, used_by_bfd, */ \
NULL, 0, 0, 0, \
NULL, 0, 0, NULL, \
\
/* cons..., owner, symbol */ \
0, 0, (struct symbol_cache_entry *) &global_syms[IDX], \
NULL, NULL, (struct symbol_cache_entry *) &global_syms[IDX], \
\
/* symbol_ptr_ptr, link_order_head, ..._tail */ \
(struct symbol_cache_entry **) &SYM, 0, 0 \
(struct symbol_cache_entry **) &SYM, NULL, NULL \
}
STD_SECTION (bfd_com_section, SEC_IS_COMMON, bfd_com_symbol,

4
bfd/targets.c
View file

@ -533,6 +533,8 @@ extern const bfd_target bfd_elf32_little_generic_vec;
extern const bfd_target bfd_elf32_littlemips_vec;
extern const bfd_target bfd_elf64_littlemips_vec;
extern const bfd_target bfd_elf32_m32r_vec;
extern const bfd_target bfd_elf32_m68hc11_vec;
extern const bfd_target bfd_elf32_m68hc12_vec;
extern const bfd_target bfd_elf32_m68k_vec;
extern const bfd_target bfd_elf32_m88k_vec;
extern const bfd_target bfd_elf32_mn10200_vec;
@ -738,6 +740,8 @@ const bfd_target * const bfd_target_vector[] = {
&bfd_elf32_m32r_vec,
&bfd_elf32_mn10200_vec,
&bfd_elf32_mn10300_vec,
&bfd_elf32_m68hc11_vec,
&bfd_elf32_m68hc12_vec,
&bfd_elf32_m68k_vec,
&bfd_elf32_m88k_vec,
&bfd_elf32_sparc_vec,

2
binutils/po/POTFILES.in
View file

@ -14,8 +14,6 @@ debug.h
dlltool.c
dlltool.h
dllwrap.c
dyn-string.c
dyn-string.h
filemode.c
ieee.c
ieee.c

1750
binutils/po/binutils.pot
View file

File diff suppressed because it is too large Load diff

3
binutils/readelf.c
View file

@ -5934,6 +5934,9 @@ read_and_display_attr (attribute, form, data, cu_offset, pointer_size)
switch (form)
{
default:
break;
case DW_FORM_ref_addr:
case DW_FORM_addr:
uvalue = byte_get (data, pointer_size);

5
binutils/testsuite/ChangeLog
View file

@ -1,3 +1,8 @@
2000-06-18 Stephane Carrez <stcarrez@worldnet.fr>
* binutils-all/objdump.exp (cpus_expected): Recognize m68hc11 and
m68hc12.
2000-06-18 Nick Clifton <nickc@redhat.com>
* binutils-all/readelf.wi: Do not assume the compilation tag to be

13
binutils/testsuite/binutils-all/objdump.exp
View file

@ -33,7 +33,7 @@ send_user "Version [binutil_version $OBJDUMP]"
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected "(a29k|alliant|alpha|arc|arm|convex|d10v|d30v|fr30|h8|hppa|i386|i860|i960|m32r|m68k|m88k|MCore|mips|mn10200|mn10300|ns32k|pj|powerpc|pyramid|romp|rs6000|sh|sparc|tahoe|v850|vax|we32k|z8k|z8001|z8002)"
set cpus_expected "(a29k|alliant|alpha|arc|arm|convex|d10v|d30v|fr30|h8|hppa|i386|i860|i960|m32r|m68hc11|m68hc12|m68k|m88k|MCore|mips|mn10200|mn10300|ns32k|pj|powerpc|pyramid|romp|rs6000|sh|sparc|tahoe|v850|vax|we32k|z8k|z8001|z8002)"
# Make sure the target CPU shows up in the list.
if ![regexp $cpus_expected $target_cpu] {
@ -83,7 +83,14 @@ if ![regexp $want $got all text_name text_size data_name data_size] then {
} else {
verbose "text name is $text_name size is $text_size"
verbose "data name is $data_name size is $data_size"
if {[expr "0x$text_size"] < 8 || [expr "0x$data_size"] < 4} then {
set ets 8
set eds 4
# c54x section sizes are in bytes, not octets; adjust accordingly
if [istarget *c54x*-*-*] then {
set ets 4
set eds 2
}
if {[expr "0x$text_size"] < $ets || [expr "0x$data_size"] < $eds} then {
send_log "sizes too small\n"
fail "objdump -h"
} else {
@ -126,7 +133,7 @@ if [regexp $want $got] then {
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -s $testfile"]
set want "$testfile:\[ \]*file format.*Contents.*(text|TEXT|\\\$CODE\\\$)\[^0-9\]*\[ \]*\[0-9a-fA-F\]*\[ \]*(00000001|01000000).*Contents.*(data|DATA)\[^0-9\]*\[ \]*\[0-9a-fA-F\]*\[ \]*(00000002|02000000)"
set want "$testfile:\[ \]*file format.*Contents.*(text|TEXT|\\\$CODE\\\$)\[^0-9\]*\[ \]*\[0-9a-fA-F\]*\[ \]*(00000001|01000000|00000100).*Contents.*(data|DATA)\[^0-9\]*\[ \]*\[0-9a-fA-F\]*\[ \]*(00000002|02000000|00000200)"
if [regexp $want $got] then {
pass "objdump -s"

13
gas/ChangeLog
View file

@ -1,3 +1,16 @@
2000-06-18 Stephane Carrez <stcarrez@worldnet.fr>
* doc/Makefile.am (CPU_DOCS): Added 68hc11 file.
* doc/c-m68hc11.texi: Document 68HC11 and 68HC12 port.
* doc/as.texinfo: Likewise.
* configure, Makefile.in: Regenerate.
* configure.in (emulations): Recognize m6811 and m6812.
* Makefile.am (CPU_TYPES, TARGET_CPU_CFILES, TARGET_CPU_HFILES):
Added files for 68hc11 and 68hc12 assembler.
* config/tc-m68hc11.c: Assembler for 68hc11 and 68hc12.
* config/tc-m68hc11.h: Header definition for that assembler.
2000-06-18 Nick Clifton <nickc@redhat.com>
* symbols.c (resolve_symbol_value): Use bfd_octets_per_byte

11
gas/Makefile.am
View file

@ -54,6 +54,7 @@ CPU_TYPES = \
i860 \
i960 \
m32r \
m68hc11 \
m68k \
m88k \
mcore \
@ -225,6 +226,7 @@ TARGET_CPU_CFILES = \
config/tc-i860.c \
config/tc-i960.c \
config/tc-m32r.c \
config/tc-m68hc11.c \
config/tc-m68k.c \
config/tc-m88k.c \
config/tc-mcore.c \
@ -262,6 +264,7 @@ TARGET_CPU_HFILES = \
config/tc-i860.h \
config/tc-i960.h \
config/tc-m32r.h \
config/tc-m68hc11.h \
config/tc-m68k.h \
config/tc-m88k.h \
config/tc-mcore.h \
@ -1087,6 +1090,11 @@ DEPTC_m32r_elf = $(INCDIR)/bin-bugs.h $(INCDIR)/progress.h \
$(INCDIR)/symcat.h $(srcdir)/../opcodes/m32r-desc.h \
$(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32r-opc.h \
cgen.h
DEPTC_m68hc11_elf = $(INCDIR)/bin-bugs.h $(INCDIR)/progress.h \
$(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h $(INCDIR)/obstack.h \
subsegs.h $(INCDIR)/opcode/m68hc11.h
DEPTC_m68k_aout = $(INCDIR)/bin-bugs.h $(INCDIR)/progress.h \
$(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h emul.h $(INCDIR)/obstack.h \
@ -1814,6 +1822,9 @@ DEP_m32r_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32r.h \
DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h
DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h
DEP_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
DEP_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \

15
gas/Makefile.in
View file

@ -158,6 +158,7 @@ CPU_TYPES = \
i860 \
i960 \
m32r \
m68hc11 \
m68k \
m88k \
mcore \
@ -335,6 +336,7 @@ TARGET_CPU_CFILES = \
config/tc-i860.c \
config/tc-i960.c \
config/tc-m32r.c \
config/tc-m68hc11.c \
config/tc-m68k.c \
config/tc-m88k.c \
config/tc-mcore.c \
@ -373,6 +375,7 @@ TARGET_CPU_HFILES = \
config/tc-i860.h \
config/tc-i960.h \
config/tc-m32r.h \
config/tc-m68hc11.h \
config/tc-m68k.h \
config/tc-m88k.h \
config/tc-mcore.h \
@ -837,6 +840,12 @@ DEPTC_m32r_elf = $(INCDIR)/bin-bugs.h $(INCDIR)/progress.h \
$(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32r-opc.h \
cgen.h
DEPTC_m68hc11_elf = $(INCDIR)/bin-bugs.h $(INCDIR)/progress.h \
$(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h $(INCDIR)/obstack.h \
subsegs.h $(INCDIR)/opcode/m68hc11.h
DEPTC_m68k_aout = $(INCDIR)/bin-bugs.h $(INCDIR)/progress.h \
$(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h emul.h $(INCDIR)/obstack.h \
@ -1742,6 +1751,10 @@ DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h
DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h
DEP_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
$(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
@ -1958,7 +1971,7 @@ configure configure.in gdbinit.in itbl-lex.c itbl-parse.c
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
TAR = tar
TAR = gtar
GZIP_ENV = --best
SOURCES = $(itbl_test_SOURCES) $(as_new_SOURCES) $(EXTRA_as_new_SOURCES) $(gasp_new_SOURCES)
OBJECTS = $(itbl_test_OBJECTS) $(as_new_OBJECTS) $(gasp_new_OBJECTS)

2
gas/config/obj-elf.c
View file

@ -833,7 +833,7 @@ obj_elf_section (push)
char mri_type;
#ifdef md_flush_pending_output
md_flush_pending_output ();
md_flush_pending_output ();
#endif
previous_section = now_seg;

6
gas/config/tc-i386.c
View file

@ -145,7 +145,7 @@ const char extra_symbol_chars[] = "*%-(";
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful */
#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (TE_LINUX) && !defined(TE_FreeBSD))
#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
/* Putting '/' here makes it impossible to use the divide operator.
However, we need it for compatibility with SVR4 systems. */
const char comment_chars[] = "#/";
@ -163,7 +163,7 @@ const char comment_chars[] = "#";
#NO_APP at the beginning of its output. */
/* Also note that comments started like this one will always work if
'/' isn't otherwise defined. */
#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (TE_LINUX) && !defined(TE_FreeBSD))
#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
const char line_comment_chars[] = "";
#else
const char line_comment_chars[] = "/";
@ -1021,7 +1021,7 @@ reloc (size, pcrel, other)
*/
int
tc_i386_fix_adjustable (fixP)
fixS *fixP;
fixS * fixP;
{
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PE)
/* Prevent all adjustments to global symbols, or else dynamic

7
gas/config/tc-m32r.c
View file

@ -1882,6 +1882,9 @@ m32r_elf_section_change_hook ()
(void) m32r_fill_insn (0);
}
/* Return true if can adjust the reloc to be relative to its section
(such as .data) instead of relative to some symbol. */
boolean
m32r_fix_adjustable (fixP)
fixS *fixP;
@ -1901,13 +1904,13 @@ m32r_fix_adjustable (fixP)
if (fixP->fx_addsy == NULL)
return 1;
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERN (fixP->fx_addsy))
return 0;
if (S_IS_WEAK (fixP->fx_addsy))
return 0;
/* We need the symbol name for the VTABLE entries */
if (reloc_type == BFD_RELOC_VTABLE_INHERIT
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)

2831
gas/config/tc-m68hc11.c Normal file
View file

File diff suppressed because it is too large Load diff

109
gas/config/tc-m68hc11.h Normal file
View file

@ -0,0 +1,109 @@
/* tc-m68hc11.h -- Header file for tc-m68hc11.c.
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#define TC_M68HC11
#define TC_M68HC12
/* Define TC_M68K so that we can use the MRI mode. */
#define TC_M68K
#define TARGET_BYTES_BIG_ENDIAN 1
/* Motorola assembler specs does not require '.' before pseudo-ops. */
#define NO_PSEUDO_DOT 1
#if 0
/* Treat the single quote as a string delimiter.
??? This does not work at all. */
#define SINGLE_QUOTE_STRINGS 1
#endif
#ifndef BFD_ASSEMBLER
#error M68HC11 support requires BFD_ASSEMBLER
#endif
/* The target BFD architecture. */
#define TARGET_ARCH (m68hc11_arch ())
extern enum bfd_architecture m68hc11_arch PARAMS ((void));
#define TARGET_MACH (m68hc11_mach ())
extern int m68hc11_mach PARAMS ((void));
#define TARGET_FORMAT (m68hc11_arch_format ())
extern const char *m68hc11_arch_format PARAMS ((void));
/* Specific sections:
- The .page0 is a data section that is mapped in [0x0000..0x00FF].
Page0 accesses are faster on the M68HC11. Soft registers used by GCC-m6811
are located in .page0.
- The .vectors is the data section that represents the interrupt
vectors. */
#define ELF_TC_SPECIAL_SECTIONS \
{ ".page0", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, \
{ ".vectors", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
#define LISTING_WORD_SIZE 1 /* A word is 1 bytes */
#define LISTING_LHS_WIDTH 4 /* One word on the first line */
#define LISTING_LHS_WIDTH_SECOND 4 /* One word on the second line */
#define LISTING_LHS_CONT_LINES 4 /* And 4 lines max */
#define LISTING_HEADER "M68HC11 GAS "
/* call md_pcrel_from_section, not md_pcrel_from */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section(FIXP, SEC)
/* Permit temporary numeric labels. */
#define LOCAL_LABELS_FB 1
#define DIFF_EXPR_OK /* .-foo gets turned into PC relative relocs */
extern void m68hc11_init_after_args PARAMS ((void));
#define tc_init_after_args m68hc11_init_after_args
extern int m68hc11_parse_long_option PARAMS ((char *));
#define md_parse_long_option m68hc11_parse_long_option
extern void m68hc11_end_of_source PARAMS ((void));
#define md_end() m68hc11_end_of_source ()
#define DWARF2_LINE_MIN_INSN_LENGTH 1
/* We don't need to handle .word strangely. */
#define WORKING_DOT_WORD
#define md_number_to_chars number_to_chars_bigendian
/* Relax table to translate short relative branches (-128..127) into
absolute branches. */
extern struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table
extern int m68hc11_cleanup PARAMS ((void));
#define md_operand(x)
#define md_after_pass_hook() m68hc11_cleanup()
#define md_cleanup() m68hc11_cleanup()
#define md_do_align(a,b,c,d,e) m68hc11_cleanup()
#define tc_frob_label(sym) do {\
m68hc11_cleanup(); \
S_SET_VALUE (sym, (valueT) frag_now_fix ()); \
} while (0)
#define tc_print_statistics m68hc11_print_statistics
extern void m68hc11_print_statistics PARAMS ((FILE *));

335
gas/configure vendored
View file

File diff suppressed because it is too large Load diff

3
gas/configure.in
View file

@ -122,6 +122,7 @@ changequote([,])dnl
changequote(,)dnl
i[456]86) cpu_type=i386 ;;
ia64) cpu_type=ia64 ;;
m6811|m6812) cpu_type=m68hc11 ;;
m680[012346]0) cpu_type=m68k ;;
changequote([,])dnl
m68008) cpu_type=m68k ;;
@ -274,6 +275,8 @@ changequote([,])dnl
m32r-*-*) fmt=elf bfd_gas=yes ;;
m68hc11-*-*|m6811-*-*|m68hc12-*-*|m6812-*-*)fmt=elf bfd_gas=yes ;;
m68k-*-vxworks* | m68k-ericsson-ose | m68k-*-sunos*)
fmt=aout em=sun3 ;;
m68k-motorola-sysv*) fmt=coff em=delta ;;

1
gas/doc/Makefile.am
View file

@ -26,6 +26,7 @@ CPU_DOCS = \
c-i386.texi \
c-i960.texi \
c-m32r.texi \
c-m68hc11.texi \
c-m68k.texi \
c-mips.texi \
c-ns32k.texi \

3
gas/doc/Makefile.in
View file

@ -129,6 +129,7 @@ CPU_DOCS = \
c-i386.texi \
c-i960.texi \
c-m32r.texi \
c-m68hc11.texi \
c-m68k.texi \
c-mips.texi \
c-ns32k.texi \
@ -164,7 +165,7 @@ DIST_COMMON = Makefile.am Makefile.in
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
TAR = tar
TAR = gtar
GZIP_ENV = --best
all: all-redirect
.SUFFIXES:

1
gas/doc/all.texi
View file

@ -37,6 +37,7 @@
@set I80386
@set I960
@set M32R
@set M68HC11
@set M680X0
@set MCORE
@set MIPS

51
gas/doc/as.texinfo
View file

@ -267,6 +267,11 @@ Here is a brief summary of how to invoke @code{@value{AS}}. For details,
[ -jsri2bsr ] [ -sifilter ] [ -relax ]
[ -mcpu=[210|340] ]
@end ifset
@ifset M68HC11
[ -m68hc11 | -m68hc12 ]
[ --force-long-branchs ] [ --short-branchs ] [ --strict-direct-mode ]
[ --print-insn-syntax ] [ --print-opcodes ] [ --generate-example ]
@end ifset
@ifset MIPS
[ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
[ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ]
@ -558,6 +563,42 @@ Generate ``little endian'' format output.
@end table
@end ifset
@ifset M68HC11
The following options are available when @value{AS} is configured for the
Motorola 68HC11 or 68HC12 series.
@table @code
@item -m68hc11 | -m68hc12
Specify what processor is the target. The default is
defined by the configuration option when building the assembler.
@item --force-long-branchs
Relative branches are turned into absolute ones. This concerns
conditional branches, unconditional branches and branches to a
sub routine.
@item -S | --short-branchs
Do not turn relative branchs into absolute ones
when the offset is out of range.
@item --strict-direct-mode
Do not turn the direct addressing mode into extended addressing mode
when the instruction does not support direct addressing mode.
@item --print-insn-syntax
Print the syntax of instruction in case of error.
@item --print-opcodes
print the list of instructions with syntax and then exit.
@item --generate-example
print an example of instruction for each possible instruction and then exit.
This option is only useful for testing @code{@value{AS}}.
@end table
@end ifset
@ifset SPARC
The following options are available when @code{@value{AS}} is configured
for the SPARC architecture:
@ -1614,6 +1655,9 @@ is considered a comment and is ignored. The line comment character is
@ifset M680X0
@samp{|} on the 680x0;
@end ifset
@ifset M68HC11
@samp{#} on the 68HC11 and 68HC12;
@end ifset
@ifset VAX
@samp{#} on the Vax;
@end ifset
@ -4972,6 +5016,9 @@ subject, see the hardware manufacturer's manual.
@ifset M680X0
* M68K-Dependent:: M680x0 Dependent Features
@end ifset
@ifset M68HC11
* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features
@end ifset
@ifset MIPS
* MIPS-Dependent:: MIPS Dependent Features
@end ifset
@ -5150,6 +5197,10 @@ family.
@include c-m68k.texi
@end ifset
@ifset M68HC11
@include c-m68hc11.texi
@end ifset
@ifset MIPS
@include c-mips.texi
@end ifset

235
gas/doc/c-m68hc11.texi Normal file
View file

@ -0,0 +1,235 @@
@c Copyright (C) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node M68HC11-Dependent
@chapter M68HC11 and M68HC12 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter M68HC11 and M68HC12 Dependent Features
@end ifclear
@cindex M68HC11 and M68HC12 support
@menu
* M68HC11-Opts:: M68HC11 and M68HC12 Options
* M68HC11-Syntax:: Syntax
* M68HC11-Float:: Floating Point
* M68HC11-opcodes:: Opcodes
@end menu
@node M68HC11-Opts
@section M68HC11 and M68HC12 Options
@cindex options, M68HC11
@cindex M68HC11 options
The Motorola 68HC11 and 68HC12 version of @code{@value{AS}} has a few machine
dependent options.
@cindex @samp{-m68hc11}
This option switches the assembler in the M68HC11 mode. In this mode,
the assembler only accepts 68HC11 operands and mnemonics. It produces
code for the 68HC11.
@cindex @samp{-m68hc12}
This option switches the assembler in the M68HC12 mode. In this mode,
the assembler also accepts 68HC12 operands and mnemonics. It produces
code for the 68HC12. A fiew 68HC11 instructions are replaced by
some 68HC12 instructions as recommended by Motorola specifications.
@cindex @samp{--strict-direct-mode}
You can use the @samp{--strict-direct-mode} option to disable
the automatic translation of direct page mode addressing into
extended mode when the instruction does not support direct mode.
For example, the @samp{clr} instruction does not support direct page
mode addressing. When it is used with the direct page mode,
@code{@value{AS}} will ignore it and generate an absolute addressing.
This option prevents @code{@value{AS}} from doing this, and the wrong
usage of the direct page mode will raise an error.
@cindex @samp{--short-branchs}
The @samp{--short-branchs} option turns off the translation of
relative branches into absolute branches when the branch offset is
out of range. By default @code{@value{AS}} transforms the relative
branch (@samp{bsr}, @samp{bgt}, @samp{bge}, @samp{beq}, @samp{bne},
@samp{ble}, @samp{blt}, @samp{bhi}, @samp{bcc}, @samp{bls},
@samp{bcs}, @samp{bmi}, @samp{bvs}, @samp{bvs}, @samp{bra}) into
an absolute branch when the offset is out of the -128 .. 127 range.
In that case, the @samp{bsr} instruction is translated into a
@samp{jsr}, the @samp{bra} instruction is translated into a
@samp{jmp} and the conditional branchs instructions are inverted and
followed by a @samp{jmp}. This option disables these translations
and @code{@value{AS}} will generate an error if a relative branch
is out of range. This option does not affect the optimization
associated to the @samp{jbra}, @samp{jbsr} and @samp{jbXX} pseudo opcodes.
@cindex @samp{--force-long-branchs}
The @samp{--force-long-branchs} option forces the translation of
relative branches into absolute branches. This option does not affect
the optimization associated to the @samp{jbra}, @samp{jbsr} and
@samp{jbXX} pseudo opcodes.
@cindex @samp{--print-insn-syntax}
You can use the @samp{--print-insn-syntax} option to obtain the
syntax description of the instruction when an error is detected.
@cindex @samp{--print-opcodes}
The @samp{--print-opcodes} option prints the list of all the
instructions with their syntax. The first item of each line
represents the instruction name and the rest of the line indicates
the possible operands for that instruction. The list is printed
in alphabetical order. Once the list is printed @code{@value{AS}}
exits.
@cindex @samp{--generate-example}
The @samp{--generate-example} option is similar to @samp{--print-opcodes}
but it generates an example for each instruction instead.
@node M68HC11-Syntax
@section Syntax
@cindex M68HC11 syntax
@cindex syntax, M68HC11
In the M68HC11 syntax, the instruction name comes first and it may
be followed by one or several operands (up to three). Operands are
separated by comma (@samp{,}). In the normal mode,
@code{@value{AS}} will complain if too many operands are specified for
a given instruction. In the MRI mode (turned on with @samp{-M} option),
it will treat them as comments. Example:
@smallexample
inx
lda #23
bset 2,x #4
brclr *bot #8 foo
@end smallexample
@cindex M68HC11 addressing modes
@cindex addressing modes, M68HC11
The following addressing modes are understood:
@table @dfn
@item Immediate
@samp{#@var{number}}
@item Address Register
@samp{@var{number},X}, @samp{@var{number},Y}
The @var{number} may be omitted in which case 0 is assumed.
@item Direct Addressing mode
@samp{*@var{symbol}}, or @samp{*@var{digits}}
@item Absolute
@samp{@var{symbol}}, or @samp{@var{digits}}
@end table
@node M68HC11-Float
@section Floating Point
@cindex floating point, M68HC11
@cindex M68HC11 floating point
Packed decimal (P) format floating literals are not supported.
Feel free to add the code!
The floating point formats generated by directives are these.
@table @code
@cindex @code{float} directive, M68HC11
@item .float
@code{Single} precision floating point constants.
@cindex @code{double} directive, M68HC11
@item .double
@code{Double} precision floating point constants.
@cindex @code{extend} directive M68HC11
@cindex @code{ldouble} directive M68HC11
@item .extend
@itemx .ldouble
@code{Extended} precision (@code{long double}) floating point constants.
@end table
@need 2000
@node M68HC11-opcodes
@section Opcodes
@cindex M68HC11 opcodes
@cindex opcodes, M68HC11
@cindex instruction set, M68HC11
@menu
* M68HC11-Branch:: Branch Improvement
@end menu
@node M68HC11-Branch
@subsection Branch Improvement
@cindex pseudo-opcodes, M68HC11
@cindex M68HC11 pseudo-opcodes
@cindex branch improvement, M68HC11
@cindex M68HC11 branch improvement
Certain pseudo opcodes are permitted for branch instructions.
They expand to the shortest branch instruction that reach the
target. Generally these mnemonics are made by prepending @samp{j} to
the start of Motorola mnemonic. These pseudo opcodes are not affected
by the @samp{--short-branchs} or @samp{--force-long-branchs} options.
The following table summarizes the pseudo-operations.
@smallexample
Displacement Width
+-------------------------------------------------------------+
| Options |
| --short-branchs --force-long-branchs |
+--------------------------+----------------------------------+
Pseudo-Op |BYTE WORD | BYTE WORD |
+--------------------------+----------------------------------+
bsr | bsr <pc-rel> <error> | jsr <abs> |
bra | bra <pc-rel> <error> | jmp <abs> |
jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> |
jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> |
bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> |
| jmp <abs> | |
+--------------------------+----------------------------------+
XX: condition
NX: negative of condition XX
@end smallexample
@table @code
@item jbsr
@itemx jbra
These are the simplest jump pseudo-operations; they always map to one
particular machine instruction, depending on the displacement to the
branch target.
@item jb@var{XX}
Here, @samp{jb@var{XX}} stands for an entire family of pseudo-operations,
where @var{XX} is a conditional branch or condition-code test. The full
list of pseudo-ops in this family is:
@smallexample
jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo
jbcs jbne jblt jble jbls jbvc jbmi
@end smallexample
For the cases of non-PC relative displacements and long displacements,
@code{@value{AS}} issues a longer code fragment in terms of
@var{NX}, the opposite condition to @var{XX}. For example, for the
non-PC relative case:
@smallexample
jb@var{XX} foo
@end smallexample
gives
@smallexample
b@var{NX}s oof
jmp foo
oof:
@end smallexample
@end table

6
gas/expr.c
View file

@ -541,8 +541,8 @@ integer_constant (radix, expressionP)
}
}
if ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
&& suffix != NULL
if ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
&& suffix != NULL
&& input_line_pointer - 1 == suffix)
c = *input_line_pointer++;
@ -815,7 +815,7 @@ operand (expressionP)
case '9':
input_line_pointer--;
integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
? 0 : 10,
expressionP);
break;

16
gas/po/POTFILES.in
View file

@ -46,6 +46,8 @@ config/tc-arc.c
config/tc-arc.h
config/tc-arm.c
config/tc-arm.h
config/tc-avr.c
config/tc-avr.h
config/tc-d10v.c
config/tc-d10v.h
config/tc-d30v.c
@ -66,8 +68,12 @@ config/tc-i860.c
config/tc-i860.h
config/tc-i960.c
config/tc-i960.h
config/tc-ia64.c
config/tc-ia64.h
config/tc-m32r.c
config/tc-m32r.h
config/tc-m68hc11.c
config/tc-m68hc11.h
config/tc-m68k.c
config/tc-m68k.h
config/tc-m88k.c
@ -114,18 +120,18 @@ ecoff.c
ecoff.h
ehopt.c
ehopt.c
emul-target.h
emul.h
emul-target.h
expr.c
expr.c
expr.h
flonum-copy.c
flonum-copy.c
flonum-konst.c
flonum-konst.c
flonum-mult.c
flonum-mult.c
flonum.h
flonum-konst.c
flonum-konst.c
flonum-mult.c
flonum-mult.c
frags.c
frags.c
frags.h

2523
gas/po/gas.pot
View file

File diff suppressed because it is too large Load diff

9
gas/testsuite/ChangeLog
View file

@ -1,3 +1,12 @@
2000-06-18 Stephane Carrez <stcarrez@worldnet.fr>
* gas/m68k/all.exp: Don't execute tests if the target is m68hc11&12.
* gas/m68hc11/all.exp: Specific tests for m68hc11.
* gas/m68hc11/all_insns.[ds]: Check m68hc11 instructions.
* gas/m68hc11/insns[ds]: Another test.
* gas/m68hc11/lbranch.[ds]: Check branch optimization (gas relax).
* gas/m68hc11/opers12.[ds]: New files, check m68hc12 operands.
2000-06-17 Alan Modra <alan@linuxcare.com.au>
* gas/macros/strings.s: Don't start directives in first column

18
gas/testsuite/gas/m68hc11/all.exp Normal file
View file

@ -0,0 +1,18 @@
#
# Some generic m68HC11 tests
#
if ![istarget "m68hc11-*-*"] then {
if ![istarget "m6811-*-*"] then {
if ![istarget "m68hc12-*-*"] then {
if ![istarget "m6812-*-*"] then {
return
}
}
}
}
run_dump_test insns
run_dump_test lbranch
run_dump_test all_insns
# Some 68HC12 tests
run_dump_test opers12

352
gas/testsuite/gas/m68hc11/all_insns.d Normal file
View file

@ -0,0 +1,352 @@
#objdump: -d --prefix-addresses
#as: -m68hc11
#name: all_insns
# Test handling of basic instructions.
.*: +file format elf32\-m68hc11
Disassembly of section .text:
0+000 <L0> aba
0+001 <L1> abx
0+002 <L2> aby
0+004 <L3> adca #103
0+006 <L4> adca \*0+000 <L0>
0+008 <L5> adca 105,x
0+00a <L6> adca 0+000 <L0>
0+00d <L7> adca 81,x
0+00f <L8> adcb #255
0+011 <L9> adcb \*0+000 <L0>
0+013 <L10> adcb 236,x
0+015 <L11> adcb 0+000 <L0>
0+018 <L12> adcb 205,x
0+01a <L13> adda #186
0+01c <L14> adda \*0+000 <L0>
0+01e <L15> adda 242,x
0+020 <L16> adda 0+000 <L0>
0+023 <L17> adda 227,x
0+025 <L18> addb #70
0+027 <L19> addb \*0+000 <L0>
0+029 <L20> addb 194,x
0+02b <L21> addb 0+000 <L0>
0+02e <L22> addb 248,x
0+030 <L23> addd #0000231b <L330\+0x2034>
0+033 <L24> addd \*0+000 <L0>
0+035 <L25> addd 231,x
0+037 <L26> addd 0+000 <L0>
0+03a <L27> addd 118,x
0+03c <L28> anda #90
0+03e <L29> anda \*0+000 <L0>
0+040 <L30> anda 99,x
0+042 <L31> anda 0+000 <L0>
0+045 <L32> anda 159,x
0+047 <L33> andb #201
0+049 <L34> andb \*0+000 <L0>
0+04b <L35> andb 102,x
0+04d <L36> andb 0+000 <L0>
0+050 <L37> andb 13,x
0+052 <L38> asl 183,x
0+054 <L39> asl 0+000 <L0>
0+057 <L40> asl 88,x
0+059 <L41> asla
0+05a <L42> aslb
0+05b <L43> asld
0+05c <L44> asr 163,x
0+05e <L45> asr 0+000 <L0>
0+061 <L46> asr 37,x
0+063 <L47> asra
0+064 <L48> asrb
0+065 <L49> bcs 0+06a <L50>
0+067 <L49\+0x2> jmp 0+0f3 <L93>
0+06a <L50> bclr \*0+000 <L0> #\$00
0+06d <L51> bclr 88,x #\$00
0+070 <L52> bclr 94,x #\$00
0+073 <L53> bcc 0+078 <L54>
0+075 <L53\+0x2> jmp 0+1a8 <L171>
0+078 <L54> bne 0+07d <L55>
0+07a <L54\+0x2> jmp 0+1b6 <L178>
0+07d <L55> blt 0+082 <L56>
0+07f <L55\+0x2> jmp 0+1f5 <L205>
0+082 <L56> ble 0+087 <L57>
0+084 <L56\+0x2> jmp 0+1e4 <L198>
0+087 <L57> bls 0+08c <L58>
0+089 <L57\+0x2> jmp 0+18a <L155>
0+08c <L58> bcs 0+091 <L59>
0+08e <L58\+0x2> jmp 0+1bb <L180>
0+091 <L59> bita #84
0+093 <L60> bita \*0+000 <L0>
0+095 <L61> bita 14,x
0+097 <L62> bita 0+000 <L0>
0+09a <L63> bita 116,x
0+09c <L64> bitb #65
0+09e <L65> bitb \*0+000 <L0>
0+0a0 <L66> bitb 61,x
0+0a2 <L67> bitb 0+000 <L0>
0+0a5 <L68> bitb 135,x
0+0a7 <L69> ble 0+11d <L112>
0+0a9 <L70> bcc 0+0ae <L71>
0+0ab <L70\+0x2> jmp 0+22e <L233>
0+0ae <L71> bls 0+097 <L62>
0+0b0 <L72> bge 0+0b5 <L73>
0+0b2 <L72\+0x2> jmp 0+197 <L161>
0+0b5 <L73> bmi 0+09e <L65>
0+0b7 <L74> beq 0+0bc <L75>
0+0b9 <L74\+0x2> jmp 0+220 <L225>
0+0bc <L75> bmi 0+0c1 <L76>
0+0be <L75\+0x2> jmp 0+24e <L252>
0+0c1 <L76> bra 0+106 <L103>
0+0c3 <L77> brclr \*0+000 <L0> #\$00 0+145 <L125\+0x2>
0+0c7 <L78> brclr 151,x #\$00 0+127 <L115>
0+0cb <L79> brclr 107,x #\$00 0+0de <L84\+0x1>
0+0cf <L80> brn 0+082 <L56>
0+0d1 <L81> brset \*0+000 <L0> #\$00 0+141 <L124>
0+0d5 <L82> brset 176,x #\$00 0+154 <L132>
0+0d9 <L83> brset 50,x #\$00 0+119 <L110\+0x2>
0+0dd <L84> bset \*0+000 <L0> #\$00
0+0e0 <L85> bset 24,x #\$00
0+0e3 <L86> bset 92,x #\$00
0+0e6 <L87> jsr 0+037 <L26>
0+0e9 <L88> bvs 0+0ee <L89>
0+0eb <L88\+0x2> jmp 0+253 <L254>
0+0ee <L89> bvs 0+0a2 <L67>
0+0f0 <L90> cba
0+0f1 <L91> clc
0+0f2 <L92> cli
0+0f3 <L93> clr 251,x
0+0f5 <L94> clr 0+000 <L0>
0+0f8 <L95> clr 170,x
0+0fa <L96> clra
0+0fb <L97> clrb
0+0fc <L98> clv
0+0fd <L99> cmpa #58
0+0ff <L100> cmpa \*0+000 <L0>
0+101 <L101> cmpa 41,x
0+103 <L102> cmpa 0+000 <L0>
0+106 <L103> cmpa 230,x
0+108 <L104> cmpb #5
0+10a <L105> cmpb \*0+000 <L0>
0+10c <L106> cmpb 124,x
0+10e <L107> cmpb 0+000 <L0>
0+111 <L108> cmpb 117,x
0+113 <L109> cpd #0+fd8 <L330\+0xcf1>
0+117 <L110> cpd \*0+000 <L0>
0+11a <L111> cpd 97,x
0+11d <L112> cpd 0+000 <L0>
0+121 <L113> cpd 249,x
0+124 <L114> cpx #0000af5c <L330\+0xac75>
0+127 <L115> cpx \*0+000 <L0>
0+129 <L116> cpx 168,x
0+12b <L117> cpx 0+000 <L0>
0+12e <L118> cpx 15,x
0+130 <L119> cpy #00004095 <L330\+0x3dae>
0+134 <L120> cpy \*0+000 <L0>
0+137 <L121> cpy 235,x
0+13a <L122> cpy 0+000 <L0>
0+13e <L123> cpy 179,x
0+141 <L124> com 5,x
0+143 <L125> com 0+000 <L0>
0+146 <L126> com 247,x
0+148 <L127> coma
0+149 <L128> comb
0+14a <L129> cpd #0000bf00 <L330\+0xbc19>
0+14e <L130> cpd \*0+000 <L0>
0+151 <L131> cpd 161,x
0+154 <L132> cpd 0+000 <L0>
0+158 <L133> cpd 229,x
0+15b <L134> cpx #00008fca <L330\+0x8ce3>
0+15e <L135> cpx \*0+000 <L0>
0+160 <L136> cpx 203,x
0+162 <L137> cpx 0+000 <L0>
0+165 <L138> cpx 72,x
0+167 <L139> cpy #0+247 <L248>
0+16b <L140> cpy \*0+000 <L0>
0+16e <L141> cpy 189,x
0+171 <L142> cpy 0+000 <L0>
0+175 <L143> cpy 35,x
0+178 <L144> daa
0+179 <L145> dec 30,x
0+17b <L146> dec 0+000 <L0>
0+17e <L147> dec 28,x
0+180 <L148> deca
0+181 <L149> decb
0+182 <L150> des
0+183 <L151> dex
0+184 <L152> dey
0+186 <L153> eora #123
0+188 <L154> eora \*0+000 <L0>
0+18a <L155> eora 197,x
0+18c <L156> eora 0+000 <L0>
0+18f <L157> eora 115,x
0+191 <L158> eorb #90
0+193 <L159> eorb \*0+000 <L0>
0+195 <L160> eorb 94,x
0+197 <L161> eorb 0+000 <L0>
0+19a <L162> eorb 121,x
0+19c <L163> fdiv
0+19d <L164> idiv
0+19e <L165> inc 99,x
0+1a0 <L166> inc 0+000 <L0>
0+1a3 <L167> inc 112,x
0+1a5 <L168> inca
0+1a6 <L169> incb
0+1a7 <L170> ins
0+1a8 <L171> inx
0+1a9 <L172> iny
0+1ab <L173> jmp 100,x
0+1ad <L174> jmp 0+000 <L0>
0+1b0 <L175> jmp 17,x
0+1b2 <L176> jsr \*0+000 <L0>
0+1b4 <L177> jsr 9,x
0+1b6 <L178> jsr 0+000 <L0>
0+1b9 <L179> jsr 170,x
0+1bb <L180> ldaa #212
0+1bd <L181> ldaa \*0+000 <L0>
0+1bf <L182> ldaa 242,x
0+1c1 <L183> ldaa 0+000 <L0>
0+1c4 <L184> ldaa 16,x
0+1c6 <L185> ldab #175
0+1c8 <L186> ldab \*0+000 <L0>
0+1ca <L187> ldab 51,x
0+1cc <L188> ldab 0+000 <L0>
0+1cf <L189> ldab 227,x
0+1d1 <L190> ldd #0000c550 <L330\+0xc269>
0+1d4 <L191> ldd \*0+000 <L0>
0+1d6 <L192> ldd 71,x
0+1d8 <L193> ldd 0+000 <L0>
0+1db <L194> ldd 92,x
0+1dd <L195> lds #00004fbb <L330\+0x4cd4>
0+1e0 <L196> lds \*0+000 <L0>
0+1e2 <L197> lds 34,x
0+1e4 <L198> lds 0+000 <L0>
0+1e7 <L199> lds 186,x
0+1e9 <L200> ldx #0000579b <L330\+0x54b4>
0+1ec <L201> ldx \*0+000 <L0>
0+1ee <L202> ldx 245,x
0+1f0 <L203> ldx 0+000 <L0>
0+1f3 <L204> ldx 225,x
0+1f5 <L205> ldy #0000ac1a <L330\+0xa933>
0+1f9 <L206> ldy \*0+000 <L0>
0+1fc <L207> ldy 127,x
0+1ff <L208> ldy 0+000 <L0>
0+203 <L209> ldy 248,x
0+206 <L210> asl 41,x
0+208 <L211> asl 0+000 <L0>
0+20b <L212> asl 164,x
0+20d <L213> asla
0+20e <L214> aslb
0+20f <L215> asld
0+210 <L216> lsr 27,x
0+212 <L217> lsr 0+000 <L0>
0+215 <L218> lsr 181,x
0+217 <L219> lsra
0+218 <L220> lsrb
0+219 <L221> lsrd
0+21a <L222> mul
0+21b <L223> neg 202,x
0+21d <L224> neg 0+000 <L0>
0+220 <L225> neg 232,x
0+222 <L226> nega
0+223 <L227> negb
0+224 <L228> nop
0+225 <L229> oraa #152
0+227 <L230> oraa \*0+000 <L0>
0+229 <L231> oraa 56,x
0+22b <L232> oraa 0+000 <L0>
0+22e <L233> oraa 121,x
0+230 <L234> orab #77
0+232 <L235> orab \*0+000 <L0>
0+234 <L236> orab 52,x
0+236 <L237> orab 0+000 <L0>
0+239 <L238> orab 95,x
0+23b <L239> psha
0+23c <L240> pshb
0+23d <L241> pshx
0+23e <L242> pshy
0+240 <L243> pula
0+241 <L244> pulb
0+242 <L245> pulx
0+243 <L246> puly
0+245 <L247> rol 78,x
0+247 <L248> rol 0+000 <L0>
0+24a <L249> rol 250,x
0+24c <L250> rola
0+24d <L251> rolb
0+24e <L252> ror 203,x
0+250 <L253> ror 0+000 <L0>
0+253 <L254> ror 5,x
0+255 <L255> rora
0+256 <L256> rorb
0+257 <L257> rti
0+258 <L258> rts
0+259 <L259> sba
0+25a <L260> sbca #172
0+25c <L261> sbca \*0+000 <L0>
0+25e <L262> sbca 33,x
0+260 <L263> sbca 0+000 <L0>
0+263 <L264> sbca 170,x
0+265 <L265> sbcb #26
0+267 <L266> sbcb \*0+000 <L0>
0+269 <L267> sbcb 162,x
0+26b <L268> sbcb 0+000 <L0>
0+26e <L269> sbcb 112,x
0+270 <L270> sec
0+271 <L271> sei
0+272 <L272> sev
0+273 <L273> staa \*0+000 <L0>
0+275 <L274> staa 115,x
0+277 <L275> staa 0+000 <L0>
0+27a <L276> staa 4,x
0+27c <L277> stab \*0+000 <L0>
0+27e <L278> stab 211,x
0+280 <L279> stab 0+000 <L0>
0+283 <L280> stab 148,x
0+285 <L281> std \*0+000 <L0>
0+287 <L282> std 175,x
0+289 <L283> std 0+000 <L0>
0+28c <L284> std 240,x
0+28e <L285> stop
0+28f <L286> sts \*0+000 <L0>
0+291 <L287> sts 158,x
0+293 <L288> sts 0+000 <L0>
0+296 <L289> sts 50,x
0+298 <L290> stx \*0+000 <L0>
0+29a <L291> stx 73,x
0+29c <L292> stx 0+000 <L0>
0+29f <L293> stx 130,x
0+2a1 <L294> sty \*0+000 <L0>
0+2a4 <L295> sty 169,x
0+2a7 <L296> sty 0+000 <L0>
0+2ab <L297> sty 112,x
0+2ae <L298> suba #212
0+2b0 <L299> suba \*0+000 <L0>
0+2b2 <L300> suba 138,x
0+2b4 <L301> suba 0+000 <L0>
0+2b7 <L302> suba 84,x
0+2b9 <L303> subb #72
0+2bb <L304> subb \*0+000 <L0>
0+2bd <L305> subb 10,x
0+2bf <L306> subb 0+000 <L0>
0+2c2 <L307> subb 213,x
0+2c4 <L308> subd #0000f10e <L330\+0xee27>
0+2c7 <L309> subd \*0+000 <L0>
0+2c9 <L310> subd 168,x
0+2cb <L311> subd 0+000 <L0>
0+2ce <L312> subd 172,x
0+2d0 <L313> swi
0+2d1 <L314> tab
0+2d2 <L315> tap
0+2d3 <L316> tba
...
0+2d5 <L318> tpa
0+2d6 <L319> tst 91,x
0+2d8 <L320> tst 0+000 <L0>
0+2db <L321> tst 142,x
0+2dd <L322> tsta
0+2de <L323> tstb
0+2df <L324> tsx
0+2e0 <L325> tsy
0+2e2 <L326> txs
0+2e3 <L327> tys
0+2e5 <L328> wai
0+2e6 <L329> xgdx
0+2e7 <L330> xgdy

335
gas/testsuite/gas/m68hc11/all_insns.s Normal file
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@ -0,0 +1,335 @@
# Example of M68hc11 instructions
.sect .text
_start:
L0: aba
L1: abx
L2: aby
L3: adca #103
L4: adca *Z198
L5: adca 105,X
L6: adca symbol115
L7: adca 81,X
L8: adcb #255
L9: adcb *Z74
L10: adcb 236,X
L11: adcb symbol41
L12: adcb 205,X
L13: adda #186
L14: adda *Z171
L15: adda 242,X
L16: adda symbol251
L17: adda 227,X
L18: addb #70
L19: addb *Z124
L20: addb 194,X
L21: addb symbol84
L22: addb 248,X
L23: addd #8987
L24: addd *Z232
L25: addd 231,X
L26: addd symbol141
L27: addd 118,X
L28: anda #90
L29: anda *Z46
L30: anda 99,X
L31: anda symbol51
L32: anda 159,X
L33: andb #201
L34: andb *Z154
L35: andb 102,X
L36: andb symbol50
L37: andb 13,X
L38: asl 183,X
L39: asl symbol49
L40: asl 88,X
L41: asla
L42: aslb
L43: asld
L44: asr 163,X
L45: asr symbol90
L46: asr 37,X
L47: asra
L48: asrb
L49: bcc L93
L50: bclr *Z5 #$17
L51: bclr 88,X #$e9
L52: bclr 94,X #$d4
L53: bcs L171
L54: beq L178
L55: bge L205
L56: bgt L198
L57: bhi L155
L58: bhs L180
L59: bita #84
L60: bita *Z17
L61: bita 14,X
L62: bita symbol130
L63: bita 116,X
L64: bitb #65
L65: bitb *Z33
L66: bitb 61,X
L67: bitb symbol220
L68: bitb 135,X
L69: ble L112
L70: blo L233
L71: bls L62
L72: blt L161
L73: bmi L65
L74: bne L225
L75: bpl L252
L76: bra L103
L77: brclr *Z62 #$01 .+126
L78: brclr 151,X #$ea .+92
L79: brclr 107,X #$96 .+15
L80: brn L56
L81: brset *Z92 #$2a .+108
L82: brset 176,X #$3b .+123
L83: brset 50,X #$af .+60
L84: bset *Z84 #$ec
L85: bset 24,X #$db
L86: bset 92,X #$02
L87: bsr L26
L88: bvc L254
L89: bvs L67
L90: cba
L91: clc
L92: cli
L93: clr 251,X
L94: clr symbol250
L95: clr 170,X
L96: clra
L97: clrb
L98: clv
L99: cmpa #58
L100: cmpa *Z251
L101: cmpa 41,X
L102: cmpa symbol209
L103: cmpa 230,X
L104: cmpb #5
L105: cmpb *Z60
L106: cmpb 124,X
L107: cmpb symbol148
L108: cmpb 117,X
L109: cmpd #4056
L110: cmpd *Z190
L111: cmpd 97,X
L112: cmpd symbol137
L113: cmpd 249,X
L114: cmpx #44892
L115: cmpx *Z187
L116: cmpx 168,X
L117: cmpx symbol153
L118: cmpx 15,X
L119: cmpy #16533
L120: cmpy *Z177
L121: cmpy 235,X
L122: cmpy symbol241
L123: cmpy 179,X
L124: com 5,X
L125: com symbol239
L126: com 247,X
L127: coma
L128: comb
L129: cpd #48896
L130: cpd *Z233
L131: cpd 161,X
L132: cpd symbol58
L133: cpd 229,X
L134: cpx #36810
L135: cpx *Z11
L136: cpx 203,X
L137: cpx symbol208
L138: cpx 72,X
L139: cpy #583
L140: cpy *Z100
L141: cpy 189,X
L142: cpy symbol31
L143: cpy 35,X
L144: daa
L145: dec 30,X
L146: dec symbol168
L147: dec 28,X
L148: deca
L149: decb
L150: des
L151: dex
L152: dey
L153: eora #123
L154: eora *Z100
L155: eora 197,X
L156: eora symbol20
L157: eora 115,X
L158: eorb #90
L159: eorb *Z197
L160: eorb 94,X
L161: eorb symbol75
L162: eorb 121,X
L163: fdiv
L164: idiv
L165: inc 99,X
L166: inc symbol59
L167: inc 112,X
L168: inca
L169: incb
L170: ins
L171: inx
L172: iny
L173: jmp 100,X
L174: jmp symbol36
L175: jmp 17,X
L176: jsr *Z158
L177: jsr 9,X
L178: jsr symbol220
L179: jsr 170,X
L180: ldaa #212
L181: ldaa *Z172
L182: ldaa 242,X
L183: ldaa symbol27
L184: ldaa 16,X
L185: ldab #175
L186: ldab *Z59
L187: ldab 51,X
L188: ldab symbol205
L189: ldab 227,X
L190: ldd #50512
L191: ldd *Z72
L192: ldd 71,X
L193: ldd symbol21
L194: ldd 92,X
L195: lds #20411
L196: lds *Z111
L197: lds 34,X
L198: lds symbol25
L199: lds 186,X
L200: ldx #22427
L201: ldx *Z125
L202: ldx 245,X
L203: ldx symbol11
L204: ldx 225,X
L205: ldy #44058
L206: ldy *Z28
L207: ldy 127,X
L208: ldy symbol35
L209: ldy 248,X
L210: lsl 41,X
L211: lsl symbol248
L212: lsl 164,X
L213: lsla
L214: lslb
L215: lsld
L216: lsr 27,X
L217: lsr symbol19
L218: lsr 181,X
L219: lsra
L220: lsrb
L221: lsrd
L222: mul
L223: neg 202,X
L224: neg symbol78
L225: neg 232,X
L226: nega
L227: negb
L228: nop
L229: oraa #152
L230: oraa *Z50
L231: oraa 56,X
L232: oraa symbol224
L233: oraa 121,X
L234: orab #77
L235: orab *Z61
L236: orab 52,X
L237: orab symbol188
L238: orab 95,X
L239: psha
L240: pshb
L241: pshx
L242: pshy
L243: pula
L244: pulb
L245: pulx
L246: puly
L247: rol 78,X
L248: rol symbol119
L249: rol 250,X
L250: rola
L251: rolb
L252: ror 203,X
L253: ror symbol108
L254: ror 5,X
L255: rora
L256: rorb
L257: rti
L258: rts
L259: sba
L260: sbca #172
L261: sbca *Z134
L262: sbca 33,X
L263: sbca symbol43
L264: sbca 170,X
L265: sbcb #26
L266: sbcb *Z85
L267: sbcb 162,X
L268: sbcb symbol190
L269: sbcb 112,X
L270: sec
L271: sei
L272: sev
L273: staa *Z181
L274: staa 115,X
L275: staa symbol59
L276: staa 4,X
L277: stab *Z92
L278: stab 211,X
L279: stab symbol54
L280: stab 148,X
L281: std *Z179
L282: std 175,X
L283: std symbol226
L284: std 240,X
L285: stop
L286: sts *Z228
L287: sts 158,X
L288: sts symbol79
L289: sts 50,X
L290: stx *Z21
L291: stx 73,X
L292: stx symbol253
L293: stx 130,X
L294: sty *Z78
L295: sty 169,X
L296: sty symbol8
L297: sty 112,X
L298: suba #212
L299: suba *Z178
L300: suba 138,X
L301: suba symbol41
L302: suba 84,X
L303: subb #72
L304: subb *Z154
L305: subb 10,X
L306: subb symbol188
L307: subb 213,X
L308: subd #61710
L309: subd *Z24
L310: subd 168,X
L311: subd symbol68
L312: subd 172,X
L313: swi
L314: tab
L315: tap
L316: tba
L317: test
L318: tpa
L319: tst 91,X
L320: tst symbol243
L321: tst 142,X
L322: tsta
L323: tstb
L324: tsx
L325: tsy
L326: txs
L327: tys
L328: wai
L329: xgdx
L330: xgdy

44
gas/testsuite/gas/m68hc11/insns.d Normal file
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@ -0,0 +1,44 @@
#objdump: -d --prefix-addresses
#as: -m68hc11
#name: insns
# Test handling of basic instructions.
.*: +file format elf32\-m68hc11
Disassembly of section .text:
0+000 <_start> lds #0+0400 <L1\+0x3a9>
0+003 <_start\+0x3> ldx #0+0001 <_start\+0x1>
0+006 <Loop> jsr 0+0010 <test>
0+009 <Loop\+0x3> dex
0+00a <Loop\+0x4> bne 0+0006 <Loop>
0+00c <Stop> .byte 0xcd, 0x03
0+00e <Stop\+0x2> bra 0+0000 <_start>
0+010 <test> ldd #0+0002 <_start\+0x2>
0+013 <test\+0x3> jsr 0+0017 <test2>
0+016 <test\+0x6> rts
0+017 <test2> ldx 23,y
0+01a <test2\+0x3> std 23,x
0+01c <test2\+0x5> ldd 0,x
0+01e <test2\+0x7> sty 0,y
0+021 <test2\+0xa> stx 0,y
0+024 <test2\+0xd> brclr 6,x #\$04 00000017 <test2>
0+028 <test2\+0x11> brclr 12,x #\$08 00000017 <test2>
0+02c <test2\+0x15> ldd \*0+0 <_start>
0+02e <test2\+0x17> ldx \*0+2 <_start\+0x2>
0+030 <test2\+0x19> clr 0+0 <_start>
0+033 <test2\+0x1c> clr 0+1 <_start\+0x1>
0+036 <test2\+0x1f> bne 0+34 <test2\+0x1d>
0+038 <test2\+0x21> beq 0+3c <test2\+0x25>
0+03a <test2\+0x23> bclr \*0+1 <_start\+0x1> #\$20
0+03d <test2\+0x26> brclr \*0+2 <_start\+0x2> #\$28 0+017 <test2>
0+041 <test2\+0x2a> ldy #0+ffec <L1\+0xff95>
0+045 <test2\+0x2e> ldd 12,y
0+048 <test2\+0x31> addd 44,y
0+04b <test2\+0x34> addd 50,y
0+04e <test2\+0x37> subd 0+02c <test2\+0x15>
0+051 <test2\+0x3a> subd #0+02c <test2\+0x15>
0+054 <test2\+0x3d> jmp 0000000c <Stop>
0+057 <L1> anda #23
0+059 <L1\+0x2> andb #0
0+05b <L1\+0x4> rts

60
gas/testsuite/gas/m68hc11/insns.s Normal file
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@ -0,0 +1,60 @@
# Test for correct generation of 68HC11 insns.
.globl _start
.sect .text
_start:
lds #stack+1024
ldx #1
Loop:
jsr test
dex
bne Loop
Stop:
.byte 0xcd
.byte 3
bra _start
test:
ldd #2
jsr test2
rts
B_low = 12
A_low = 44
D_low = 50
value = 23
.globl test2
test2:
ldx value,y
std value,x
ldd ,x
sty ,y
stx ,y
brclr 6,x,#4,test2
brclr 12,x #8 test2
ldd *ZD1
ldx *ZD1+2
clr *ZD2
clr *ZD2+1
bne .-4
beq .+2
bclr *ZD1+1, #32
brclr *ZD2+2, #40, test2
ldy #24+_start-44
ldd B_low,y
addd A_low,y
addd D_low,y
subd A_low
subd #A_low
jmp Stop
L1:
anda #%lo(test2)
andb #%hi(test2)
rts
.sect .data
.comm stack, 1024

47
gas/testsuite/gas/m68hc11/lbranch.d Normal file
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@ -0,0 +1,47 @@
#objdump: -d --prefix-addresses
#as: -m68hc11
#name: lbranch
# Test handling of basic instructions.
.*: +file format elf32\-m68hc11
Disassembly of section .text:
0+0000 <_rcall> ldaa #16
0+0002 <_rcall\+0x2> jmp 0+010b <Lend>
0+0005 <_rcall\+0x5> jsr 0+011b <toto>
0+0008 <_rcall\+0x8> beq 0+000d <_rcall\+0xd>
0+000a <_rcall\+0xa> jmp 0+011b <toto>
0+000d <_rcall\+0xd> bne 0+0012 <_rcall\+0x12>
0+000f <_rcall\+0xf> jmp 0+011b <toto>
0+0012 <_rcall\+0x12> bcc 0+0017 <_rcall\+0x17>
0+0014 <_rcall\+0x14> jmp 0+011b <toto>
0+0017 <_rcall\+0x17> bcs 0+001c <_rcall\+0x1c>
0+0019 <_rcall\+0x19> jmp 0+011b <toto>
0+001c <_rcall\+0x1c> xgdx
0+001d <_rcall\+0x1d> xgdx
0+001e <_rcall\+0x1e> bne 0+0023 <_rcall\+0x23>
0+0020 <_rcall\+0x20> jmp 0+0180 <bidule>
0+0023 <_rcall\+0x23> bcc 0+0028 <_rcall\+0x28>
0+0025 <_rcall\+0x25> jmp 0+0180 <bidule>
0+0028 <_rcall\+0x28> bcs 0+002d <_rcall\+0x2d>
0+002a <_rcall\+0x2a> jmp 0+0180 <bidule>
0+002d <_rcall\+0x2d> xgdx
0+002e <_rcall\+0x2e> jmp 0+00c8 <_rcall\+0xc8>
0+0031 <_rcall\+0x31> jsr 0+0783 <bidule\+0x603>
0+0034 <_rcall\+0x34> beq 0+0039 <_rcall\+0x39>
0+0036 <_rcall\+0x36> jmp 0+010b <Lend>
0+0039 <_rcall\+0x39> jsr 0+011b <toto>
0+003c <_rcall\+0x3c> bne 0+0041 <_rcall\+0x41>
0+003e <_rcall\+0x3e> jmp 0+011b <toto>
[ ]*\.\.\.
0+0109 <_rcall\+0x109> ldaa \*0+0000 <_rcall>
0+010b <Lend> bls 0+0110 <Lend\+0x5>
0+010d <Lend\+0x2> jmp 0+0000 <_rcall>
0+0110 <Lend\+0x5> bhi 0+0115 <Lend\+0xa>
0+0112 <Lend\+0x7> jmp 0+0000 <_rcall>
0+0115 <Lend\+0xa> jsr 0+0000 <_rcall>
0+0118 <Lend\+0xd> ldx #0+000c <_rcall\+0xc>
0+011b <toto> rts
[ ]*\.\.\.
0+0180 <bidule> rts

41
gas/testsuite/gas/m68hc11/lbranch.s Normal file
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@ -0,0 +1,41 @@
# Test for the 68HC11 long branch switch
.text
.globl _rcall
.globl _start
_start:
_rcall:
ldaa #0x10 ;86 10
jbra Lend ; Must be switched to a jmp
jbsr toto ; -> to a jsr
jbne toto ; -> to a beq+jmp
jbeq toto ; -> to a bne+jmp
jbcs toto ; -> to a bcc+jmp
jbcc toto ; -> to a bcs+jmp
xgdx
xgdx
beq bidule ; -> to a bne+jmp
bcs bidule ; -> to a bcc+jmp
bcc bidule ; -> to a bcs+jmp
xgdx
jbra 200
jbsr 1923
bne Lend ; -> to a beq+jmp
jbsr toto
jbeq toto
.skip 200
ldaa *dir ;96 33
Lend:
bhi external_op
bls external_op
bsr out
ldx #12
toto:
rts
.skip 100
bidule:
rts
.sect ".page0"
dir:
.long 0
; END

70
gas/testsuite/gas/m68hc11/opers12.d Normal file
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@ -0,0 +1,70 @@
#objdump: -d --prefix-addresses
#as: -m68hc12
#name: opers
.*: +file format elf32\-m68hc12
Disassembly of section .text:
0+000 <start> anda \[12,X\]
0+004 <start\+0x4> ldaa #10
0+006 <start\+0x6> ldx 0+009 <L1>
0+009 <L1> ldy 0,X
0+00b <L1\+0x2> addd 1,Y
0+00d <L1\+0x4> subd -1,Y
0+00f <L1\+0x6> eora 15,Y
0+011 <L1\+0x8> eora -16,Y
0+013 <L1\+0xa> eorb 16,Y
0+016 <L1\+0xd> eorb -17,Y
0+019 <L1\+0x10> oraa 128,SP
0+01c <L1\+0x13> orab -128,SP
0+01f <L1\+0x16> orab 255,X
0+022 <L1\+0x19> orab -256,X
0+025 <L1\+0x1c> anda 256,X
0+029 <L1\+0x20> andb -257,X
0+02d <L1\+0x24> anda \[12,X\]
0+031 <L1\+0x28> ldaa \[257,Y\]
0+035 <L1\+0x2c> ldab \[32767,SP\]
0+039 <L1\+0x30> ldd \[32768,PC\]
0+03d <L1\+0x34> ldd 0,PC
0+040 <L1\+0x37> std A,X
0+042 <L1\+0x39> ldx B,X
0+044 <L1\+0x3b> stx D,Y
0+046 <L1\+0x3d> addd 1,\+X
0+048 <L1\+0x3f> addd 2,\+X
0+04a <L1\+0x41> addd 8,\+X
0+04c <L1\+0x43> addd 1,SP\+
0+04e <L1\+0x45> addd 2,SP\+
0+050 <L1\+0x47> addd 8,SP\+
0+052 <L1\+0x49> subd 1,\-Y
0+054 <L1\+0x4b> subd 2,\-Y
0+056 <L1\+0x4d> subd 8,\-Y
0+058 <L1\+0x4f> addd 1,Y\-
0+05a <L1\+0x51> addd 2,Y\-
0+05c <L1\+0x53> addd 8,Y\-
0+05e <L1\+0x55> std \[D,X\]
0+060 <L1\+0x57> std \[D,Y\]
0+062 <L1\+0x59> std \[D,SP\]
0+064 <L1\+0x5b> std \[D,PC\]
0+066 <L1\+0x5d> beq 0+009 <L1>
0+068 <L1\+0x5f> lbeq 0+000 <start>
0+06c <L1\+0x63> lbcc 0+0bc <L2>
0+070 <L1\+0x67> movb 0+000 <start>, 1,X
0+075 <L1\+0x6c> movw 1,X, 0+000 <start>
0+07a <L1\+0x71> movb 0+000 <start>, 1,\+X
0+07f <L1\+0x76> movb 0+000 <start>, 1,\-X
0+084 <L1\+0x7b> movb #23, 1,\-SP
0+088 <L1\+0x7f> movb 0+009 <L1>, 0+0bc <L2>
0+08e <L1\+0x85> movb 0+009 <L1>, A,X
0+093 <L1\+0x8a> movw 0+009 <L1>, B,X
0+098 <L1\+0x8f> movw 0+009 <L1>, D,X
0+09d <L1\+0x94> movw D,X, A,X
0+0a1 <L1\+0x98> movw B,SP, D,PC
0+0a5 <L1\+0x9c> movw B,SP, 0+009 <L1>
0+0aa <L1\+0xa1> movw B,SP, 1,X
0+0ae <L1\+0xa5> movw D,X, A,Y
0+0b2 <L1\+0xa9> trap #48
0+0b4 <L1\+0xab> trap #57
0+0b6 <L1\+0xad> trap #64
0+0b8 <L1\+0xaf> trap #128
0+0ba <L1\+0xb1> trap #255
0+0bc <L2> rts

72
gas/testsuite/gas/m68hc11/opers12.s Normal file
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@ -0,0 +1,72 @@
#
# Try to verify all operand modes for 68HC12
#
sect .text
globl start
start:
anda [12,x]
ldaa #10
ldx L1
L1: ldy ,x
addd 1,y
subd -1,y
eora 15,y
eora -16,y
eorb 16,y
eorb -17,y
oraa 128,sp
orab -128,sp
orab 255,x
orab -256,x
anda 256,x
andb -257,x
anda [12,x]
ldaa [257,y]
ldab [32767,sp]
ldd [32768,pc]
ldd L1,pc
std a,x
ldx b,x
stx d,y
addd 1,+x
addd 2,+x
addd 8,+x
addd 1,sp+
addd 2,sp+
addd 8,sp+
subd 1,-y
subd 2,-y
subd 8,-y
addd 1,y-
addd 2,y-
addd 8,y-
std [d,x]
std [d,y]
std [d,sp]
std [d,pc]
beq L1
lbeq start
lbcc L2
movb start, 1,x
movw 1,x, start
movb start, 1,+x
movb start, 1,-x
movb #23, 1,-sp
movb L1, L2
movb L1, a,x
movw L1, b,x
movw L1, d,x
movw d,x, a,x
movw b,sp, d,pc
movw b,sp, L1
movw b,sp, 1,x
movw d,x, a,y
trap #0x30
trap #0x39
trap #0x40
trap #0x80
trap #255
L2:
rts

14
gas/testsuite/gas/m68k/all.exp
View file

@ -1,6 +1,18 @@
#
# Some generic m68k tests
#
if [istarget "m68hc11-*-*"] then {
return
}
if [istarget "m68hc12-*-*"] then {
return
}
if [istarget "m6811-*-*"] then {
return
}
if [istarget "m6812-*-*"] then {
return
}
if [istarget m68*-*-*] then {
gas_test "t2.s" "" "" "cross-section branch"
if [istarget m68*-motorola-sysv] then {
@ -36,4 +48,4 @@ if [istarget m68*-*-*] then {
}
if [info exists errorInfo] then {
unset errorInfo
}
}

2
gprof/Makefile.in
View file

@ -178,7 +178,7 @@ aclocal.m4 configure configure.in gconfig.in
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
TAR = tar
TAR = gtar
GZIP_ENV = --best
SOURCES = $(gprof_SOURCES)
OBJECTS = $(gprof_OBJECTS)

40
gprof/po/gprof.pot
View file

@ -6,7 +6,7 @@
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"POT-Creation-Date: 2000-04-04 23:21+0930\n"
"POT-Creation-Date: 2000-06-18 16:58-0700\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
@ -250,81 +250,75 @@ msgstr ""
msgid "%s: bfd_vma has unexpected size of %ld bytes\n"
msgstr ""
#: gmon_io.c:87 gmon_io.c:182
#: gmon_io.c:90 gmon_io.c:185
#, c-format
msgid "%s: file too short to be a gmon file\n"
msgstr ""
#: gmon_io.c:97 gmon_io.c:215
#: gmon_io.c:100 gmon_io.c:218
#, c-format
msgid "%s: file `%s' has bad magic cookie\n"
msgstr ""
#: gmon_io.c:108
#: gmon_io.c:111
#, c-format
msgid "%s: file `%s' has unsupported version %d\n"
msgstr ""
#: gmon_io.c:138
#: gmon_io.c:141
#, c-format
msgid "%s: %s: found bad tag %d (file corrupted?)\n"
msgstr ""
#: gmon_io.c:203
#: gmon_io.c:206
#, c-format
msgid "%s: profiling rate incompatible with first gmon file\n"
msgstr ""
#: gmon_io.c:232
#: gmon_io.c:235
#, c-format
msgid "%s: incompatible with first gmon file\n"
msgstr ""
#: gmon_io.c:258
#: gmon_io.c:261
#, c-format
msgid "%s: file '%s' does not appear to be in gmon.out format\n"
msgstr ""
#: gmon_io.c:280
#: gmon_io.c:283
#, c-format
msgid "%s: unexpected EOF after reading %d/%d bins\n"
msgstr ""
#: gmon_io.c:315
#: gmon_io.c:318
msgid "time is in ticks, not seconds\n"
msgstr ""
#: gmon_io.c:321 gmon_io.c:461
#: gmon_io.c:324 gmon_io.c:464
#, c-format
msgid "%s: don't know how to deal with file format %d\n"
msgstr ""
#: gmon_io.c:328
#: gmon_io.c:331
#, c-format
msgid "File `%s' (version %d) contains:\n"
msgstr ""
#: gmon_io.c:330
#: gmon_io.c:333
#, c-format
msgid "\t%d histogram record%s\n"
msgstr ""
#: gmon_io.c:332
#: gmon_io.c:335
#, c-format
msgid "\t%d call-graph record%s\n"
msgstr ""
#: gmon_io.c:334
#: gmon_io.c:337
#, c-format
msgid "\t%d basic-block count record%s\n"
msgstr ""
#: gprof.c:59
msgid ""
"@(#) Copyright (c) 1983 Regents of the University of California.\n"
" All rights reserved.\n"
msgstr ""
#: gprof.c:144
#, c-format
msgid ""
@ -461,12 +455,12 @@ msgstr ""
msgid "Flat profile:\n"
msgstr ""
#: source.c:140
#: source.c:155
#, c-format
msgid "%s: could not locate `%s'\n"
msgstr ""
#: source.c:200
#: source.c:242
#, c-format
msgid "*** File %s:\n"
msgstr ""

5
include/ChangeLog
View file

@ -1,3 +1,8 @@
2000-06-18 Stephane Carrez <stcarrez@worldnet.fr>
* dis-asm.h (print_insn_m68hc12): Define.
(print_insn_m68hc11): Likewise.
2000-06-18 Nick Clifton <nickc@redhat.com>
* os9k.h: Change values of MODSYNC and CRCCON due to bug report

2
include/dis-asm.h
View file

@ -159,6 +159,8 @@ extern int print_insn_i386_att PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i386_intel PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_ia64 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i370 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_m68hc11 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_m68hc12 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*));

24
include/elf/ChangeLog
View file

@ -1,3 +1,7 @@
2000-06-18 Stephane Carrez <stcarrez@worldnet.fr>
* m68hc11.h: New file, definitions for the Motorola 68hc11.
2000-06-06 Alan Modra <alan@linuxcare.com.au>
* reloc-macros.h (START_RELOC_NUMBERS): Don't define initial dummy
@ -120,6 +124,12 @@ Thu Feb 17 00:18:33 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
(EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise.
(EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise.
2000-03-10 Geoffrey Keating <geoffk@cygnus.com>
* mips.h: Add R_MIPS_GNU_REL_HI16, R_MIPS_GNU_REL_LO16,
R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation
numbers.
2000-02-03 H.J. Lu <hjl@gnu.org>
* arm-oabi.h: Duplicate changes made to arm.h on Jan. 27,
@ -245,6 +255,20 @@ Mon Oct 4 17:42:38 1999 Doug Evans <devans@canuck.cygnus.com>
* pj.h: New file.
* common.h (EM_PJ): Define.
Wed Dec 1 03:02:15 1999 Jeffrey A Law (law@cygnus.com)
* mn10300.h (E_MN10300_MACH_AM33): Define.
Mon Oct 11 22:42:37 1999 Jeffrey A Law (law@cygnus.com)
* hppa.h (PF_HP_PAGE_SIZE): Define.
(PF_HP_FAR_SHARED, PF_HP_NEAR_SHARED, PF_HP_CODE): Likewise.
(PF_HP_MODIFY, PF_HP_LAZYSWAP, PF_HP_SBP): Likewise.
1999-09-15 Ulrich Drepper <drepper@cygnus.com>
* hppa.h: Add DT_HP_GST_SIZE, DT_HP_GST_VERSION, and DT_HP_GST_HASHVAL.
1999-09-02 Ulrich Drepper <drepper@cygnus.com>
* hppa.h: Add HPUX specific symbol type definitions.

42
include/elf/m68hc11.h Normal file
View file

@ -0,0 +1,42 @@
/* m68hc11 & m68hc12 ELF support for BFD.
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _ELF_M68HC11_H
#define _ELF_M68HC11_H
#include "elf/reloc-macros.h"
/* Relocation types. */
START_RELOC_NUMBERS (elf_m68hc11_reloc_type)
RELOC_NUMBER (R_M68HC11_NONE, 0)
RELOC_NUMBER (R_M68HC11_8, 1)
RELOC_NUMBER (R_M68HC11_HI8, 2)
RELOC_NUMBER (R_M68HC11_LO8, 3)
RELOC_NUMBER (R_M68HC11_PCREL_8, 4)
RELOC_NUMBER (R_M68HC11_16, 5)
RELOC_NUMBER (R_M68HC11_32, 6)
RELOC_NUMBER (R_M68HC11_3B, 7)
RELOC_NUMBER (R_M68HC11_PCREL_16, 8)
/* These are GNU extensions to enable C++ vtable garbage collection. */
RELOC_NUMBER (R_M68HC11_GNU_VTINHERIT, 9)
RELOC_NUMBER (R_M68HC11_GNU_VTENTRY, 10)
END_RELOC_NUMBERS (R_M68HC11_max)
#endif

4
include/opcode/ChangeLog
View file

@ -1,3 +1,7 @@
2000-06-18 Stephane Carrez <stcarrez@worldnet.fr>
* m68hc11.h: New file for support of Motorola 68hc11.
Fri Jun 9 21:51:50 2000 Denis Chertykov <denisc@overta.ru>
* avr.h: clr,lsl,rol, ... moved after add,adc, ...

2
include/opcode/cgen.h
View file

@ -736,7 +736,7 @@ typedef struct
the data is recorded in the parse/insert/extract/print switch statements. */
/* This should be at least as large as necessary for any target. */
#define CGEN_MAX_SYNTAX_BYTES 32
#define CGEN_MAX_SYNTAX_BYTES 40
/* A target may know its own precise maximum. Assert that it falls below
the above limit. */

418
include/opcode/m68hc11.h Normal file
View file

@ -0,0 +1,418 @@
/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table
Copyright 1999, 2000 Free Software Foundation, Inc.
Written by Stephane Carrez (stcarrez@worldnet.fr)
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _OPCODE_M68HC11_H
#define _OPCODE_M68HC11_H
/* Flags for the definition of the 68HC11 & 68HC12 CCR. */
#define M6811_S_BIT 0x80 /* Stop disable */
#define M6811_X_BIT 0x40 /* X-interrupt mask */
#define M6811_H_BIT 0x20 /* Half carry flag */
#define M6811_I_BIT 0x10 /* I-interrupt mask */
#define M6811_N_BIT 0x08 /* Negative */
#define M6811_Z_BIT 0x04 /* Zero */
#define M6811_V_BIT 0x02 /* Overflow */
#define M6811_C_BIT 0x01 /* Carry */
/* 68HC11 register address offsets (range 0..0x3F or 0..64).
The absolute address of the I/O register depends on the setting
of the M6811_INIT register. At init time, the I/O registers are
mapped at 0x1000. Address of registers is then:
0x1000 + M6811_xxx
*/
#define M6811_PORTA 0x00 /* Port A register */
#define M6811__RES1 0x01 /* Unused/Reserved */
#define M6811_PIOC 0x02 /* Parallel I/O Control register */
#define M6811_PORTC 0x03 /* Port C register */
#define M6811_PORTB 0x04 /* Port B register */
#define M6811_PORTCL 0x05 /* Alternate latched port C */
#define M6811__RES6 0x06 /* Unused/Reserved */
#define M6811_DDRC 0x07 /* Data direction register for port C */
#define M6811_PORTD 0x08 /* Port D register */
#define M6811_DDRD 0x09 /* Data direction register for port D */
#define M6811_PORTE 0x0A /* Port E input register */
#define M6811_CFORC 0x0B /* Compare Force Register */
#define M6811_OC1M 0x0C /* OC1 Action Mask register */
#define M6811_OC1D 0x0D /* OC1 Action Data register */
#define M6811_TCTN 0x0E /* Timer Counter Register */
#define M6811_TCTN_H 0x0E /* " " " High part */
#define M6811_TCTN_L 0x0F /* " " " Low part */
#define M6811_TIC1 0x10 /* Input capture 1 register */
#define M6811_TIC1_H 0x10 /* " " " High part */
#define M6811_TIC1_L 0x11 /* " " " Low part */
#define M6811_TIC2 0x12 /* Input capture 2 register */
#define M6811_TIC2_H 0x12 /* " " " High part */
#define M6811_TIC2_L 0x13 /* " " " Low part */
#define M6811_TIC3 0x14 /* Input capture 3 register */
#define M6811_TIC3_H 0x14 /* " " " High part */
#define M6811_TIC3_L 0x15 /* " " " Low part */
#define M6811_TOC1 0x16 /* Output Compare 1 register */
#define M6811_TOC1_H 0x16 /* " " " High part */
#define M6811_TOC1_L 0x17 /* " " " Low part */
#define M6811_TOC2 0x18 /* Output Compare 2 register */
#define M6811_TOC2_H 0x18 /* " " " High part */
#define M6811_TOC2_L 0x19 /* " " " Low part */
#define M6811_TOC3 0x1A /* Output Compare 3 register */
#define M6811_TOC3_H 0x1A /* " " " High part */
#define M6811_TOC3_L 0x1B /* " " " Low part */
#define M6811_TOC4 0x1C /* Output Compare 4 register */
#define M6811_TOC4_H 0x1C /* " " " High part */
#define M6811_TOC4_L 0x1D /* " " " Low part */
#define M6811_TOC5 0x1E /* Output Compare 5 register */
#define M6811_TOC5_H 0x1E /* " " " High part */
#define M6811_TOC5_L 0x1F /* " " " Low part */
#define M6811_TCTL1 0x20 /* Timer Control register 1 */
#define M6811_TCTL2 0x21 /* Timer Control register 2 */
#define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */
#define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */
#define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */
#define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */
#define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */
#define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */
#define M6811_SPCR 0x28 /* SPI Control register */
#define M6811_SPSR 0x29 /* SPI Status register */
#define M6811_SPDR 0x2A /* SPI Data register */
#define M6811_BAUD 0x2B /* SCI Baud register */
#define M6811_SCCR1 0x2C /* SCI Control register 1 */
#define M6811_SCCR2 0x2D /* SCI Control register 2 */
#define M6811_SCSR 0x2E /* SCI Status register */
#define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */
#define M6811_ADCTL 0x30 /* A/D Control register */
#define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */
#define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */
#define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */
#define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */
#define M6811__RES35 0x35
#define M6811__RES36 0x36
#define M6811__RES37 0x37
#define M6811__RES38 0x38
#define M6811_OPTION 0x39 /* System Configuration Options */
#define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */
#define M6811_PPROG 0x3B /* EEPROM Programming Control Register */
#define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */
#define M6811_INIT 0x3D /* Ram and I/O mapping register */
#define M6811_TEST1 0x3E /* Factory test control register */
#define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */
/* Flags of the CONFIG register (in EEPROM). */
#define M6811_NOSEC 0x08 /* Security mode disable */
#define M6811_NOCOP 0x04 /* COP system disable */
#define M6811_ROMON 0x02 /* Enable on-chip rom */
#define M6811_EEON 0x01 /* Enable on-chip eeprom */
/* Flags of the PPROG register. */
#define M6811_BYTE 0x10 /* Byte mode */
#define M6811_ROW 0x08 /* Row mode */
#define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */
#define M6811_EELAT 0x02 /* EEPROM Latch Control */
#define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */
/* Flags of the PIOC register. */
#define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */
#define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */
#define M6811_CWOM 0x20 /* Port C Wire OR mode */
#define M6811_HNDS 0x10 /* Handshake mode */
#define M6811_OIN 0x08 /* Output or Input handshaking */
#define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */
#define M6811_EGA 0x02 /* Active Edge for Strobe A */
#define M6811_INVB 0x01 /* Invert Strobe B */
/* Flags of the SCCR1 register. */
#define M6811_R8 0x80 /* Receive Data bit 8 */
#define M6811_T8 0x40 /* Transmit data bit 8 */
#define M6811__SCCR1_5 0x20 /* Unused */
#define M6811_M 0x10 /* SCI Character length */
#define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */
/* Flags of the SCCR2 register. */
#define M6811_TIE 0x80 /* Transmit Interrupt enable */
#define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */
#define M6811_RIE 0x20 /* Receive Interrupt Enable */
#define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */
#define M6811_TE 0x08 /* Transmit Enable */
#define M6811_RE 0x04 /* Receive Enable */
#define M6811_RWU 0x02 /* Receiver Wake Up */
#define M6811_SBK 0x01 /* Send Break */
/* Flags of the SCSR register. */
#define M6811_TDRE 0x80 /* Transmit Data Register Empty */
#define M6811_TC 0x40 /* Transmit Complete */
#define M6811_RDRF 0x20 /* Receive Data Register Full */
#define M6811_IDLE 0x10 /* Idle Line Detect */
#define M6811_OR 0x08 /* Overrun Error */
#define M6811_NF 0x04 /* Noise Flag */
#define M6811_FE 0x02 /* Framing Error */
#define M6811__SCSR_0 0x01 /* Unused */
/* Flags of the BAUD register. */
#define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */
#define M6811__BAUD_6 0x40 /* Not used */
#define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */
#define M6811_SCP0 0x10
#define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */
#define M6811_SCR2 0x04 /* SCI Baud rate select */
#define M6811_SCR1 0x02
#define M6811_SCR0 0x01
#define M6811_BAUD_DIV_1 (0)
#define M6811_BAUD_DIV_3 (M6811_SCP0)
#define M6811_BAUD_DIV_4 (M6811_SCP1)
#define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0)
/* Flags of the SPCR register. */
#define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */
#define M6811_SPE 0x40 /* Serial Peripheral System Enable */
#define M6811_DWOM 0x20 /* Port D Wire-OR mode option */
#define M6811_MSTR 0x10 /* Master Mode Select */
#define M6811_CPOL 0x08 /* Clock Polarity */
#define M6811_CPHA 0x04 /* Clock Phase */
#define M6811_SPR1 0x02 /* SPI Clock Rate Select */
#define M6811_SPR0 0x01
/* Flags of the SPSR register. */
#define M6811_SPIF 0x80 /* SPI Transfer Complete flag */
#define M6811_WCOL 0x40 /* Write Collision */
#define M6811_MODF 0x20 /* Mode Fault */
/* Flags of the ADCTL register. */
#define M6811_CCF 0x80 /* Conversions Complete Flag */
#define M6811_SCAN 0x20 /* Continuous Scan Control */
#define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */
#define M6811_CD 0x08 /* Channel Select D */
#define M6811_CC 0x04 /* C */
#define M6811_CB 0x02 /* B */
#define M6811_CA 0x01 /* A */
/* Flags of the CFORC register. */
#define M6811_FOC1 0x80 /* Force Output Compare 1 */
#define M6811_FOC2 0x40 /* 2 */
#define M6811_FOC3 0x20 /* 3 */
#define M6811_FOC4 0x10 /* 4 */
#define M6811_FOC5 0x08 /* 5 */
/* Flags of the OC1M register. */
#define M6811_OC1M7 0x80 /* Output Compare 7 */
#define M6811_OC1M6 0x40 /* 6 */
#define M6811_OC1M5 0x40 /* 5 */
#define M6811_OC1M4 0x40 /* 4 */
#define M6811_OC1M3 0x08 /* 3 */
/* Flags of the OC1D register. */
#define M6811_OC1D7 0x80
#define M6811_OC1D6 0x40
#define M6811_OC1D5 0x20
#define M6811_OC1D4 0x10
#define M6811_OC1D3 0x08
/* Flags of the TCTL1 register. */
#define M6811_OM2 0x80 /* Output Mode 2 */
#define M6811_OL2 0x40 /* Output Level 2 */
#define M6811_OM3 0x20
#define M6811_OL3 0x10
#define M6811_OM4 0x08
#define M6811_OL4 0x04
#define M6811_OM5 0x02
#define M6811_OL5 0x01
/* Flags of the TCTL2 register. */
#define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */
#define M6811_EDG1A 0x10
#define M6811_EDG2B 0x08 /* Input 2 */
#define M6811_EDG2A 0x04
#define M6811_EDG3B 0x02 /* Input 3 */
#define M6811_EDG3A 0x01
/* Flags of the TMSK1 register. */
#define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */
#define M6811_OC2I 0x40 /* 2 */
#define M6811_OC3I 0x20 /* 3 */
#define M6811_OC4I 0x10 /* 4 */
#define M6811_OC5I 0x08 /* 5 */
#define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */
#define M6811_IC2I 0x02 /* 2 */
#define M6811_IC3I 0x01 /* 3 */
/* Flags of the TFLG1 register. */
#define M6811_OC1F 0x80 /* Output Compare 1 Flag */
#define M6811_OC2F 0x40 /* 2 */
#define M6811_OC3F 0x20 /* 3 */
#define M6811_OC4F 0x10 /* 4 */
#define M6811_OC5F 0x08 /* 5 */
#define M6811_IC1F 0x04 /* Input Capture 1 Flag */
#define M6811_IC2F 0x02 /* 2 */
#define M6811_IC3F 0x01 /* 3 */
/* Flags of Timer Interrupt Mask Register 2 (TMSK2). */
#define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */
#define M6811_RTII 0x40 /* RTI Interrupt Enable */
#define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */
#define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */
#define M6811_PR1 0x02 /* Timer prescaler */
#define M6811_PR0 0x01 /* Timer prescaler */
#define M6811_TPR_1 0x00 /* " " prescale div 1 */
#define M6811_TPR_4 0x01 /* " " prescale div 4 */
#define M6811_TPR_8 0x02 /* " " prescale div 8 */
#define M6811_TPR_16 0x03 /* " " prescale div 16 */
/* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */
#define M6811_TOF 0x80 /* Timer overflow bit */
#define M6811_RTIF 0x40 /* Read time interrupt flag */
#define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */
#define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */
/* Flags of Pulse Accumulator Control Register (PACTL). */
#define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */
#define M6811_PAEN 0x40 /* Pulse accumulator system enable */
#define M6811_PAMOD 0x20 /* Pulse accumulator mode */
#define M6811_PEDGE 0x10 /* Pulse accumulator edge control */
#define M6811_RTR1 0x02 /* RTI Interrupt rates select */
#define M6811_RTR0 0x01 /* " " " " */
/* Flags of the Options register. */
#define M6811_ADPU 0x80 /* A/D Powerup */
#define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */
#define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */
#define M6811_DLY 0x10 /* Stop exit turn on delay */
#define M6811_CME 0x08 /* Clock Monitor enable */
#define M6811_CR1 0x02 /* COP timer rate select */
#define M6811_CR0 0x01 /* COP timer rate select */
/* Flags of the HPRIO register. */
#define M6811_RBOOT 0x80 /* Read Bootstrap ROM */
#define M6811_SMOD 0x40 /* Special Mode */
#define M6811_MDA 0x20 /* Mode Select A */
#define M6811_IRV 0x10 /* Internal Read Visibility */
#define M6811_PSEL3 0x08 /* Priority Select */
#define M6811_PSEL2 0x04
#define M6811_PSEL1 0x02
#define M6811_PSEL0 0x01
/* Some insns used by gas to turn relative branches into absolute ones. */
#define M6811_BRA 0x20
#define M6811_JMP 0x7e
#define M6811_BSR 0x8d
#define M6811_JSR 0xbd
#define M6812_JMP 0x06
#define M6812_BSR 0x07
#define M6812_JSR 0x16
/* Instruction code pages. Code page 1 is the default. */
/*#define M6811_OPCODE_PAGE1 0x00*/
#define M6811_OPCODE_PAGE2 0x18
#define M6811_OPCODE_PAGE3 0x1A
#define M6811_OPCODE_PAGE4 0xCD
/* 68HC11 operands formats as stored in the m6811_opcode table. These
flags do not correspond to anything in the 68HC11 or 68HC12.
They are only used by GAS to recognize operands. */
#define M6811_OP_NONE 0 /* No operand */
#define M6811_OP_DIRECT 0x0001 /* Page 0 addressing: *<val-8bits> */
#define M6811_OP_IMM8 0x0002 /* 8 bits immediat: #<val-8bits> */
#define M6811_OP_IMM16 0x0004 /* 16 bits immediat: #<val-16bits> */
#define M6811_OP_IND16 0x0008 /* Indirect abs: <val-16> */
#define M6812_OP_IND16_P2 0x0010 /* Second parameter indirect abs. */
#define M6812_OP_REG 0x0020 /* Register operand 1 */
#define M6812_OP_REG_2 0x0040 /* Register operand 2 */
#define M6811_OP_IX 0x0080 /* Indirect IX: <val-8>,x */
#define M6811_OP_IY 0x0100 /* Indirect IY: <val-8>,y */
#define M6812_OP_IDX 0x0200 /* Indirect: N,r N,[+-]r[+-] N:5-bits */
#define M6812_OP_IDX_1 0x0400 /* N,r N:9-bits */
#define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */
#define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */
#define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */
#define M6811_OP_MASK 0x0FFFF
#define M6811_OP_BITMASK 0x00010000 /* Bitmask: #<val-8> */
#define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: <val-8> */
#define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: <val-16> */
#define M6811_OP_PAGE1 0x0000
#define M6811_OP_PAGE2 0x00080000 /* Need a page2 opcode before */
#define M6811_OP_PAGE3 0x00100000 /* Need a page3 opcode before */
#define M6811_OP_PAGE4 0x00200000 /* Need a page4 opcode before */
#define M6811_MAX_OPERANDS 3 /* Max operands: brset <dst> <mask> <b> */
#define M6812_ACC_OFFSET 0x00400000 /* A,r B,r D,r */
#define M6812_ACC_IND 0x00800000 /* [D,r] */
#define M6812_PRE_INC 0x01000000 /* n,+r n = -8..8 */
#define M6812_PRE_DEC 0x02000000 /* n,-r */
#define M6812_POST_INC 0x04000000 /* n,r+ */
#define M6812_POST_DEC 0x08000000 /* n,r- */
#define M6812_INDEXED_IND 0x10000000 /* [n,r] n = 16-bits */
#define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */
#define M6812_OP_IDX_P2 0x40000000
/* Markers to identify some instructions. */
#define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */
#define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */
#define M6812_OP_SEX_MARKER 0x04000000 /* sex r1,r2 */
#define M6812_OP_EQ_MARKER 0x80000000 /* dbeq/ibeq/tbeq */
#define M6812_OP_DBCC_MARKER 0x04000000 /* dbeq/dbne */
#define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */
#define M6812_OP_TBCC_MARKER 0x01000000
#define M6812_OP_TRAP_ID 0x80000000 /* trap #N */
#define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */
#define M6811_OP_LOW_ADDR 0x02000000
/* CPU identification. */
#define cpu6811 0x01
#define cpu6812 0x02
/* The opcode table is an array of struct m68hc11_opcode. */
struct m68hc11_opcode {
const char* name; /* Op-code name */
long format;
unsigned char size;
unsigned char opcode;
unsigned char cycles_low;
unsigned char cycles_high;
unsigned char set_flags_mask;
unsigned char clr_flags_mask;
unsigned char chg_flags_mask;
unsigned char arch;
};
/* Alias definition for 68HC12. */
struct m68hc12_opcode_alias
{
const char* name;
const char* translation;
unsigned char size;
unsigned char code1;
unsigned char code2;
};
/* The opcode table. The table contains all the opcodes (all pages).
You can't rely on the order. */
extern const struct m68hc11_opcode m68hc11_opcodes[];
extern const int m68hc11_num_opcodes;
/* Alias table for 68HC12. It translates some 68HC11 insn which are not
implemented in 68HC12 but have equivalent translations. */
extern const struct m68hc12_opcode_alias m68hc12_alias[];
extern const int m68hc12_num_alias;
#endif /* _OPCODE_M68HC11_H */

14
ld/ChangeLog
View file

@ -1,3 +1,17 @@
2000-06-18 Stephane Carrez <stcarrez@worldnet.fr>
* Makefile.am (ALL_EMULATIONS): Added new emulation for m68hc12
and m68hc11 (elf).
* Makefile.in: Rebuild.
* configure.tgt: Recognize m68hc12 and m68hc11.
* scripttempl/elfm68hc12.sc: New file.
* emulparams/m68hc12elfb: New emulation.
* emulparams/m68hc12elf: New emulation.
* emulparams/m68hc11elfb.sh: New file. User configurable emulation
(includes a memory.x script to define the ROM and RAM banks).
* scripttempl/elfm68hc11.sc, emulparams/m68hc11elf.sh:
New configuration files for support of Motorola 68hc11
2000-06-15 Alan Modra <alan@linuxcare.com.au>
* ldmain.c (main): Only change SEC_READONLY for final link.

16
ld/Makefile.am
View file

@ -175,6 +175,10 @@ ALL_EMULATIONS = \
ei386pe.o \
ei386pe_posix.o \
elnk960.o \
em68hc11elf.o \
em68hc11elfb.o \
em68hc12elf.o \
em68hc12elfb.o \
em68k4knbsd.o \
em68kaout.o \
em68kaux.o \
@ -557,6 +561,18 @@ ei386pe_posix.c: $(srcdir)/emulparams/i386pe_posix.sh \
elnk960.c: $(srcdir)/emulparams/lnk960.sh \
$(srcdir)/emultempl/lnk960.em $(srcdir)/scripttempl/i960.sc ${GEN_DEPENDS}
${GENSCRIPTS} lnk960 "$(tdir_lnk960)"
em68hc11elf.c: $(srcdir)/emulparams/m68hc11elf.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elfm68hc11.sc ${GEN_DEPENDS}
${GENSCRIPTS} m68hc11elf "$(tdir_m68hc11)"
em68hc11elfb.c: $(srcdir)/emulparams/m68hc11elfb.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elfm68hc11.sc ${GEN_DEPENDS}
${GENSCRIPTS} m68hc11elfb "$(tdir_m68hc11b)"
em68hc12elf.c: $(srcdir)/emulparams/m68hc12elf.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elfm68hc12.sc ${GEN_DEPENDS}
${GENSCRIPTS} m68hc12elf "$(tdir_m68hc12)"
em68hc12elfb.c: $(srcdir)/emulparams/m68hc12elfb.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elfm68hc12.sc ${GEN_DEPENDS}
${GENSCRIPTS} m68hc12elfb "$(tdir_m68hc12b)"
em68k4knbsd.c: $(srcdir)/emulparams/m68k4knbsd.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} m68k4knbsd "$(tdir_m68k4knbsd)"

18
ld/Makefile.in
View file

@ -278,6 +278,10 @@ ALL_EMULATIONS = \
ei386pe.o \
ei386pe_posix.o \
elnk960.o \
em68hc11elf.o \
em68hc11elfb.o \
em68hc12elf.o \
em68hc12elfb.o \
em68k4knbsd.o \
em68kaout.o \
em68kaux.o \
@ -436,7 +440,7 @@ ldgram.c ldlex.c
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
TAR = tar
TAR = gtar
GZIP_ENV = --best
SOURCES = $(ld_new_SOURCES)
OBJECTS = $(ld_new_OBJECTS)
@ -1256,6 +1260,18 @@ ei386pe_posix.c: $(srcdir)/emulparams/i386pe_posix.sh \
elnk960.c: $(srcdir)/emulparams/lnk960.sh \
$(srcdir)/emultempl/lnk960.em $(srcdir)/scripttempl/i960.sc ${GEN_DEPENDS}
${GENSCRIPTS} lnk960 "$(tdir_lnk960)"
em68hc11elf.c: $(srcdir)/emulparams/m68hc11elf.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elfm68hc11.sc ${GEN_DEPENDS}
${GENSCRIPTS} m68hc11elf "$(tdir_m68hc11)"
em68hc11elfb.c: $(srcdir)/emulparams/m68hc11elfb.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elfm68hc11.sc ${GEN_DEPENDS}
${GENSCRIPTS} m68hc11elfb "$(tdir_m68hc11b)"
em68hc12elf.c: $(srcdir)/emulparams/m68hc12elf.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elfm68hc12.sc ${GEN_DEPENDS}
${GENSCRIPTS} m68hc12elf "$(tdir_m68hc12)"
em68hc12elfb.c: $(srcdir)/emulparams/m68hc12elfb.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/elfm68hc12.sc ${GEN_DEPENDS}
${GENSCRIPTS} m68hc12elfb "$(tdir_m68hc12b)"
em68k4knbsd.c: $(srcdir)/emulparams/m68k4knbsd.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} m68k4knbsd "$(tdir_m68k4knbsd)"

6
ld/configure.tgt
View file

@ -84,6 +84,10 @@ i960-*-elf*) targ_emul=elf32_i960 ;;
ia64-*-elf*) targ_emul=elf64_ia64 ;;
ia64-*-linux*) targ_emul=elf64_ia64 ;;
m32r-*-*) targ_emul=m32relf ;;
m68hc11-*-*|m6811-*-*) targ_emul=m68hc11elf
targ_extra_emuls="m68hc11elfb m68hc12elf m68hc12elfb" ;;
m68hc12-*-*|m6812-*-*) targ_emul=m68hc12elf
targ_extra_emuls="m68hc12elfb m68hc11elf m68hc11elfb" ;;
m68*-sun-sunos[34]*) targ_emul=sun3 ;;
m68*-wrs-vxworks*) targ_emul=sun3 ;;
m68*-ericsson-ose) targ_emul=sun3 ;;
@ -257,7 +261,7 @@ alpha*-*-netbsd*) targ_emul=elf64alpha ;;
z8k-*-coff) targ_emul=z8002; targ_extra_emuls=z8001 ;;
ns32k-pc532-mach* | ns32k-pc532-ux*) targ_emul=pc532macha ;;
ns32k-pc532-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd ;;
powerpc-*-linux-gnu*) targ_emul=elf32ppclinux;
powerpc-*-linux-gnu*) targ_emul=elf32ppclinux;
targ_extra_emuls="elf32ppc elf32ppcsim";
targ_extra_libpath=elf32ppc ;;
pjl*-*-*) targ_emul=pjlelf ; targ_extra_emuls="elf_i386" ;;

13
ld/emulparams/m68hc11elf.sh Normal file
View file

@ -0,0 +1,13 @@
MACHINE=
SCRIPT_NAME=elfm68hc11
OUTPUT_FORMAT="elf32-m68hc11"
ROM_START_ADDR=0x08000
ROM_SIZE=0x8000
RAM_START_ADDR=0x01100
RAM_SIZE=0x6F00
TEXT_MEMORY=text
DATA_MEMORY=data
ARCH=m68hc11
MAXPAGESIZE=32
EMBEDDED=yes
GENERIC_BOARD=no

9
ld/emulparams/m68hc11elfb.sh Normal file
View file

@ -0,0 +1,9 @@
MACHINE=
SCRIPT_NAME=elfm68hc11
OUTPUT_FORMAT="elf32-m68hc11"
TEXT_MEMORY=text
DATA_MEMORY=data
ARCH=m68hc11
MAXPAGESIZE=32
GENERIC_BOARD=yes

13
ld/emulparams/m68hc12elf.sh Normal file
View file

@ -0,0 +1,13 @@
MACHINE=
SCRIPT_NAME=elfm68hc12
OUTPUT_FORMAT="elf32-m68hc12"
ROM_START_ADDR=0x08000
ROM_SIZE=0x8000
RAM_START_ADDR=0x01100
RAM_SIZE=0x6F00
TEXT_MEMORY=text
DATA_MEMORY=data
ARCH=m68hc12
MAXPAGESIZE=32
EMBEDDED=yes
GENERIC_BOARD=no

9
ld/emulparams/m68hc12elfb.sh Normal file
View file

@ -0,0 +1,9 @@
MACHINE=
SCRIPT_NAME=elfm68hc12
OUTPUT_FORMAT="elf32-m68hc12"
TEXT_MEMORY=text
DATA_MEMORY=data
ARCH=m68hc12
MAXPAGESIZE=32
GENERIC_BOARD=yes

3
ld/emulparams/shpe.sh
View file

@ -4,3 +4,6 @@ OUTPUT_FORMAT="pei-shl"
TEMPLATE_NAME=pe
SUBSYSTEM=PE_DEF_SUBSYSTEM
INITIAL_SYMBOL_CHAR=\"_\"
ENTRY="_mainCRTStartup"
SUBSYSTEM=PE_DEF_SUBSYSTEM
INITIAL_SYMBOL_CHAR=\"_\"

8
ld/emultempl/elf32.em
View file

@ -423,7 +423,7 @@ gld${EMULATION_NAME}_search_needed (path, name, force)
path = s + 1;
}
return false;
return false;
}
/* This function is called for each possible name for a dynamic object
@ -1125,7 +1125,7 @@ then
sc="-f stringify.sed"
cat >>e${EMULATION_NAME}.c <<EOF
{
{
*isfile = 0;
if (link_info.relocateable == true && config.build_constructors == true)
@ -1152,7 +1152,7 @@ else
# Scripts read from the filesystem.
cat >>e${EMULATION_NAME}.c <<EOF
{
{
*isfile = 1;
if (link_info.relocateable == true && config.build_constructors == true)
@ -1190,7 +1190,7 @@ fi
cat >>e${EMULATION_NAME}.c <<EOF
struct ld_emulation_xfer_struct ld_${EMULATION_NAME}_emulation =
struct ld_emulation_xfer_struct ld_${EMULATION_NAME}_emulation =
{
gld${EMULATION_NAME}_before_parse,
syslib_default,

2
ld/po/POTFILES.in
View file

@ -1,7 +1,6 @@
deffile.h
emultempl/armcoff.em
emultempl/pe.em
ld.h
ldcref.c
ldctor.c
ldctor.h
@ -11,6 +10,7 @@ ldexp.c
ldexp.h
ldfile.c
ldfile.h
ld.h
ldlang.c
ldlang.h
ldlex.h

446
ld/po/ld.pot
View file

File diff suppressed because it is too large Load diff

359
ld/scripttempl/elfm68hc11.sc Normal file
View file

@ -0,0 +1,359 @@
#
# Unusual variables checked by this code:
# NOP - two byte opcode for no-op (defaults to 0)
# DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
# OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
# (e.g., .PARISC.global)
# OTHER_SECTIONS - at the end
# EXECUTABLE_SYMBOLS - symbols that must be defined for an
# executable (e.g., _DYNAMIC_LINK)
# TEXT_START_SYMBOLS - symbols that appear at the start of the
# .text section.
# DATA_START_SYMBOLS - symbols that appear at the start of the
# .data section.
# OTHER_BSS_SYMBOLS - symbols that appear at the start of the
# .bss section besides __bss_start.
# EMBEDDED - whether this is for an embedded system.
#
# When adding sections, do note that the names of some sections are used
# when specifying the start address of the next.
#
test -z "$ENTRY" && ENTRY=_start
test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
test "$LD_FLAG" = "N" && DATA_ADDR=.
CTOR=".ctors ${CONSTRUCTING-0} :
{
${CONSTRUCTING+ __CTOR_LIST__ = .; }
${CONSTRUCTING+${CTOR_START}}
*(.ctors)
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors)) */
${CONSTRUCTING+${CTOR_END}}
${CONSTRUCTING+ __CTOR_END__ = .; }
} ${RELOCATING+ > ${DATA_MEMORY}}"
DTOR=" .dtors ${CONSTRUCTING-0} :
{
${CONSTRUCTING+ __DTOR_LIST__ = .; }
*(.dtors)
/*
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors)) */
${CONSTRUCTING+ __DTOR_END__ = .; }
} ${RELOCATING+ > ${DATA_MEMORY}}"
VECTORS="
/* If the 'vectors_addr' symbol is defined, it indicates the start address
of interrupt vectors. This depends on the 68HC11 operating mode:
Addr
Single chip 0xffc0
Extended mode 0xffc0
Bootstrap 0x00c0
Test 0xbfc0
In general, the vectors address is 0xffc0. This can be overriden
with the '-defsym vectors_addr=0xbfc0' ld option.
Note: for the bootstrap mode, the interrupt vectors are at 0xbfc0 but
they are redirected to 0x00c0 by the internal PROM. Application's vectors
must also consist of jump instructions (see Motorola's manual). */
PROVIDE (_vectors_addr = DEFINED (vectors_addr) ? vectors_addr : 0xffc0);
.vectors DEFINED (vectors_addr) ? vectors_addr : 0xffc0 :
{
*(.vectors)
}"
#
# We provide two emulations: a fixed on that defines some memory banks
# and a configurable one that includes a user provided memory definition.
#
case $GENERIC_BOARD in
yes|1|YES)
MEMORY_DEF="
/* Get memory banks definition from some user configuration file.
This file must be located in some linker directory (search path
with -L<dir>). See fixed memory banks emulation script. */
INCLUDE memory.x;
"
;;
*)
MEMORY_DEF="
/* Fixed definition of the available memory banks.
See generic emulation script for a user defined configuration. */
MEMORY
{
page0 (rwx) : ORIGIN = 0x0, LENGTH = 256
text (rx) : ORIGIN = ${ROM_START_ADDR}, LENGTH = ${ROM_SIZE}
data : ORIGIN = ${RAM_START_ADDR}, LENGTH = ${RAM_SIZE}
}
/* Setup the stack on the top of the data memory bank. */
PROVIDE (_stack = ${RAM_START_ADDR} + ${RAM_SIZE} - 1);
"
;;
esac
STARTUP_CODE="
/* Startup code. */
*(.install0) /* Section should setup the stack pointer. */
*(.install1) /* Place holder for applications. */
*(.install2) /* Optional installation of data sections in RAM. */
*(.install3) /* Place holder for applications. */
*(.install4) /* Section that calls the main. */
"
PRE_COMPUTE_DATA_SIZE="
/* SCz: this does not work yet... This is supposed to force the loading
of _map_data.o (from libgcc.a) when the .data section is not empty.
By doing so, this should bring the code that copies the .data section
from ROM to RAM at init time.
___pre_comp_data_size = SIZEOF(.data);
__install_data_sections = ___pre_comp_data_size > 0 ?
__map_data_sections : 0;
*/
"
INSTALL_RELOC="
.install0 0 : { *(.install0) }
.install1 0 : { *(.install1) }
.install2 0 : { *(.install2) }
.install3 0 : { *(.install3) }
.install4 0 : { *(.install4) }
"
BSS_DATA_RELOC="
.data1 0 : { *(.data1) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata 0 : { *(.sdata) }
.sbss 0 : { *(.sbss) }
.scommon 0 : { *(.scommon) }
"
cat <<EOF
${RELOCATING+/* Linker script for 68HC11 executable (PROM). */}
${RELOCATING-/* Linker script for 68HC11 object file (ld -r). */}
OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
"${LITTLE_OUTPUT_FORMAT}")
OUTPUT_ARCH(${OUTPUT_ARCH})
ENTRY(${ENTRY})
${RELOCATING+${LIB_SEARCH_DIRS}}
${RELOCATING+${EXECUTABLE_SYMBOLS}}
${RELOCATING+${MEMORY_DEF}}
SECTIONS
{
.hash ${RELOCATING-0} : { *(.hash) }
.dynsym ${RELOCATING-0} : { *(.dynsym) }
.dynstr ${RELOCATING-0} : { *(.dynstr) }
.gnu.version ${RELOCATING-0} : { *(.gnu.version) }
.gnu.version_d ${RELOCATING-0} : { *(.gnu.version_d) }
.gnu.version_r ${RELOCATING-0} : { *(.gnu.version_r) }
.rela.text ${RELOCATING-0} : { *(.rela.text) *(.rela.gnu.linkonce.t*) }
.rela.data ${RELOCATING-0} : { *(.rela.data) *(.rela.gnu.linkonce.d*) }
.rela.rodata ${RELOCATING-0} : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
.rela.stext ${RELOCATING-0} : { *(.rela.stest) }
.rela.etext ${RELOCATING-0} : { *(.rela.etest) }
.rela.sdata ${RELOCATING-0} : { *(.rela.sdata) }
.rela.edata ${RELOCATING-0} : { *(.rela.edata) }
.rela.eit_v ${RELOCATING-0} : { *(.rela.eit_v) }
.rela.sbss ${RELOCATING-0} : { *(.rela.sbss) }
.rela.ebss ${RELOCATING-0} : { *(.rela.ebss) }
.rela.srodata ${RELOCATING-0} : { *(.rela.srodata) }
.rela.erodata ${RELOCATING-0} : { *(.rela.erodata) }
.rela.got ${RELOCATING-0} : { *(.rela.got) }
.rela.ctors ${RELOCATING-0} : { *(.rela.ctors) }
.rela.dtors ${RELOCATING-0} : { *(.rela.dtors) }
.rela.init ${RELOCATING-0} : { *(.rela.init) }
.rela.fini ${RELOCATING-0} : { *(.rela.fini) }
.rela.bss ${RELOCATING-0} : { *(.rela.bss) }
.rela.plt ${RELOCATING-0} : { *(.rela.plt) }
.rel.data ${RELOCATING-0} : { *(.rel.data) *(.rel.gnu.linkonce.d*) }
.rel.rodata ${RELOCATING-0} : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
.rel.stext ${RELOCATING-0} : { *(.rel.stest) }
.rel.etext ${RELOCATING-0} : { *(.rel.etest) }
.rel.sdata ${RELOCATING-0} : { *(.rel.sdata) }
.rel.edata ${RELOCATING-0} : { *(.rel.edata) }
.rel.sbss ${RELOCATING-0} : { *(.rel.sbss) }
.rel.ebss ${RELOCATING-0} : { *(.rel.ebss) }
.rel.eit_v ${RELOCATING-0} : { *(.rel.eit_v) }
.rel.srodata ${RELOCATING-0} : { *(.rel.srodata) }
.rel.erodata ${RELOCATING-0} : { *(.rel.erodata) }
.rel.got ${RELOCATING-0} : { *(.rel.got) }
.rel.ctors ${RELOCATING-0} : { *(.rel.ctors) }
.rel.dtors ${RELOCATING-0} : { *(.rel.dtors) }
.rel.init ${RELOCATING-0} : { *(.rel.init) }
.rel.fini ${RELOCATING-0} : { *(.rel.fini) }
.rel.bss ${RELOCATING-0} : { *(.rel.bss) }
.rel.plt ${RELOCATING-0} : { *(.rel.plt) }
/* Concatenate .page0 sections. Put them in the page0 memory bank
unless we are creating a relocatable file. */
.page0 :
{
*(.page0)
} ${RELOCATING+ > page0}
/* Start of text section. */
.stext ${RELOCATING-0} :
{
*(.stext)
} ${RELOCATING+ > ${TEXT_MEMORY}}
.init ${RELOCATING-0} :
{
*(.init)
} ${RELOCATING+=${NOP-0}}
${RELOCATING-${INSTALL_RELOC}}
.text ${RELOCATING-0}:
{
/* Put startup code at beginning so that _start keeps same address. */
${RELOCATING+${STARTUP_CODE}}
${RELOCATING+*(.init)}
*(.text)
*(.fini)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
${RELOCATING+_etext = .;}
${RELOCATING+PROVIDE (etext = .);}
} ${RELOCATING+ > ${TEXT_MEMORY}}
.eh_frame ${RELOCATING-0} :
{
*(.eh_frame)
} ${RELOCATING+ > ${TEXT_MEMORY}}
.rodata ${RELOCATING-0} :
{
*(.rodata)
*(.gnu.linkonce.r*)
} ${RELOCATING+ > ${TEXT_MEMORY}}
.rodata1 ${RELOCATING-0} :
{
*(.rodata1)
} ${RELOCATING+ > ${TEXT_MEMORY}}
/* Start of the data section image in ROM. */
${RELOCATING+__data_image = .;}
${RELOCATING+PROVIDE (__data_image = .);}
/* All read-only sections that normally go in PROM must be above.
We construct the DATA image section in PROM at end of all these
read-only sections. The data image must be copied at init time.
Refer to GNU ld, Section 3.6.8.2 Output Section LMA. */
.data ${RELOCATING-0} : ${RELOCATING+AT (__data_image)}
{
${RELOCATING+__data_section_start = .;}
${RELOCATING+PROVIDE (__data_section_start = .);}
${RELOCATING+${DATA_START_SYMBOLS}}
${RELOCATING+*(.sdata)}
*(.data)
${RELOCATING+*(.data1)}
*(.gnu.linkonce.d*)
${CONSTRUCTING+CONSTRUCTORS}
${RELOCATING+_edata = .;}
${RELOCATING+PROVIDE (edata = .);}
} ${RELOCATING+ > ${DATA_MEMORY}}
${RELOCATING+__data_section_size = SIZEOF(.data);}
${RELOCATING+PROVIDE (__data_section_size = SIZEOF(.data));}
${RELOCATING+__data_image_end = __data_image + __data_section_size;}
${RELOCATING+${PRE_COMPUTE_DATA_SIZE}}
/* .install ${RELOCATING-0}:
{
. = _data_image_end;
} ${RELOCATING+ > ${TEXT_MEMORY}} */
/* Relocation for some bss and data sections. */
${RELOCATING-${BSS_DATA_RELOC}}
.bss ${RELOCATING-0} :
{
${RELOCATING+__bss_start = .;}
${RELOCATING+*(.sbss)}
${RELOCATING+*(.scommon)}
*(.dynbss)
*(.bss)
*(COMMON)
${RELOCATING+PROVIDE (_end = .);}
} ${RELOCATING+ > ${DATA_MEMORY}}
${RELOCATING+${CTOR}}
${RELOCATING+${DTOR}}
${RELOCATING+${VECTORS}}
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0.
Treatment of DWARF debug section must be at end of the linker
script to avoid problems when there are undefined symbols. It's necessary
to avoid that the DWARF section is relocated before such undefined
symbols are found. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
}
EOF

359
ld/scripttempl/elfm68hc12.sc Normal file
View file

@ -0,0 +1,359 @@
#
# Unusual variables checked by this code:
# NOP - two byte opcode for no-op (defaults to 0)
# DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
# OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
# (e.g., .PARISC.global)
# OTHER_SECTIONS - at the end
# EXECUTABLE_SYMBOLS - symbols that must be defined for an
# executable (e.g., _DYNAMIC_LINK)
# TEXT_START_SYMBOLS - symbols that appear at the start of the
# .text section.
# DATA_START_SYMBOLS - symbols that appear at the start of the
# .data section.
# OTHER_BSS_SYMBOLS - symbols that appear at the start of the
# .bss section besides __bss_start.
# EMBEDDED - whether this is for an embedded system.
#
# When adding sections, do note that the names of some sections are used
# when specifying the start address of the next.
#
test -z "$ENTRY" && ENTRY=_start
test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
test "$LD_FLAG" = "N" && DATA_ADDR=.
CTOR=".ctors ${CONSTRUCTING-0} :
{
${CONSTRUCTING+ __CTOR_LIST__ = .; }
${CONSTRUCTING+${CTOR_START}}
*(.ctors)
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors)) */
${CONSTRUCTING+${CTOR_END}}
${CONSTRUCTING+ __CTOR_END__ = .; }
} ${RELOCATING+ > ${DATA_MEMORY}}"
DTOR=" .dtors ${CONSTRUCTING-0} :
{
${CONSTRUCTING+ __DTOR_LIST__ = .; }
*(.dtors)
/*
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors)) */
${CONSTRUCTING+ __DTOR_END__ = .; }
} ${RELOCATING+ > ${DATA_MEMORY}}"
VECTORS="
/* If the 'vectors_addr' symbol is defined, it indicates the start address
of interrupt vectors. This depends on the 68HC11 operating mode:
Addr
Single chip 0xffc0
Extended mode 0xffc0
Bootstrap 0x00c0
Test 0xbfc0
In general, the vectors address is 0xffc0. This can be overriden
with the '-defsym vectors_addr=0xbfc0' ld option.
Note: for the bootstrap mode, the interrupt vectors are at 0xbfc0 but
they are redirected to 0x00c0 by the internal PROM. Application's vectors
must also consist of jump instructions (see Motorola's manual). */
PROVIDE (_vectors_addr = DEFINED (vectors_addr) ? vectors_addr : 0xffc0);
.vectors DEFINED (vectors_addr) ? vectors_addr : 0xffc0 :
{
*(.vectors)
}"
#
# We provide two emulations: a fixed on that defines some memory banks
# and a configurable one that includes a user provided memory definition.
#
case $GENERIC_BOARD in
yes|1|YES)
MEMORY_DEF="
/* Get memory banks definition from some user configuration file.
This file must be located in some linker directory (search path
with -L<dir>). See fixed memory banks emulation script. */
INCLUDE memory.x;
"
;;
*)
MEMORY_DEF="
/* Fixed definition of the available memory banks.
See generic emulation script for a user defined configuration. */
MEMORY
{
page0 (rwx) : ORIGIN = 0x0, LENGTH = 256
text (rx) : ORIGIN = ${ROM_START_ADDR}, LENGTH = ${ROM_SIZE}
data : ORIGIN = ${RAM_START_ADDR}, LENGTH = ${RAM_SIZE}
}
/* Setup the stack on the top of the data memory bank. */
PROVIDE (_stack = ${RAM_START_ADDR} + ${RAM_SIZE} - 1);
"
;;
esac
STARTUP_CODE="
/* Startup code. */
*(.install0) /* Section should setup the stack pointer. */
*(.install1) /* Place holder for applications. */
*(.install2) /* Optional installation of data sections in RAM. */
*(.install3) /* Place holder for applications. */
*(.install4) /* Section that calls the main. */
"
PRE_COMPUTE_DATA_SIZE="
/* SCz: this does not work yet... This is supposed to force the loading
of _map_data.o (from libgcc.a) when the .data section is not empty.
By doing so, this should bring the code that copies the .data section
from ROM to RAM at init time.
___pre_comp_data_size = SIZEOF(.data);
__install_data_sections = ___pre_comp_data_size > 0 ?
__map_data_sections : 0;
*/
"
INSTALL_RELOC="
.install0 0 : { *(.install0) }
.install1 0 : { *(.install1) }
.install2 0 : { *(.install2) }
.install3 0 : { *(.install3) }
.install4 0 : { *(.install4) }
"
BSS_DATA_RELOC="
.data1 0 : { *(.data1) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata 0 : { *(.sdata) }
.sbss 0 : { *(.sbss) }
.scommon 0 : { *(.scommon) }
"
cat <<EOF
${RELOCATING+/* Linker script for 68HC12 executable (PROM). */}
${RELOCATING-/* Linker script for 68HC12 object file (ld -r). */}
OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
"${LITTLE_OUTPUT_FORMAT}")
OUTPUT_ARCH(${OUTPUT_ARCH})
ENTRY(${ENTRY})
${RELOCATING+${LIB_SEARCH_DIRS}}
${RELOCATING+${EXECUTABLE_SYMBOLS}}
${RELOCATING+${MEMORY_DEF}}
SECTIONS
{
.hash ${RELOCATING-0} : { *(.hash) }
.dynsym ${RELOCATING-0} : { *(.dynsym) }
.dynstr ${RELOCATING-0} : { *(.dynstr) }
.gnu.version ${RELOCATING-0} : { *(.gnu.version) }
.gnu.version_d ${RELOCATING-0} : { *(.gnu.version_d) }
.gnu.version_r ${RELOCATING-0} : { *(.gnu.version_r) }
.rela.text ${RELOCATING-0} : { *(.rela.text) *(.rela.gnu.linkonce.t*) }
.rela.data ${RELOCATING-0} : { *(.rela.data) *(.rela.gnu.linkonce.d*) }
.rela.rodata ${RELOCATING-0} : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
.rela.stext ${RELOCATING-0} : { *(.rela.stest) }
.rela.etext ${RELOCATING-0} : { *(.rela.etest) }
.rela.sdata ${RELOCATING-0} : { *(.rela.sdata) }
.rela.edata ${RELOCATING-0} : { *(.rela.edata) }
.rela.eit_v ${RELOCATING-0} : { *(.rela.eit_v) }
.rela.sbss ${RELOCATING-0} : { *(.rela.sbss) }
.rela.ebss ${RELOCATING-0} : { *(.rela.ebss) }
.rela.srodata ${RELOCATING-0} : { *(.rela.srodata) }
.rela.erodata ${RELOCATING-0} : { *(.rela.erodata) }
.rela.got ${RELOCATING-0} : { *(.rela.got) }
.rela.ctors ${RELOCATING-0} : { *(.rela.ctors) }
.rela.dtors ${RELOCATING-0} : { *(.rela.dtors) }
.rela.init ${RELOCATING-0} : { *(.rela.init) }
.rela.fini ${RELOCATING-0} : { *(.rela.fini) }
.rela.bss ${RELOCATING-0} : { *(.rela.bss) }
.rela.plt ${RELOCATING-0} : { *(.rela.plt) }
.rel.data ${RELOCATING-0} : { *(.rel.data) *(.rel.gnu.linkonce.d*) }
.rel.rodata ${RELOCATING-0} : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
.rel.stext ${RELOCATING-0} : { *(.rel.stest) }
.rel.etext ${RELOCATING-0} : { *(.rel.etest) }
.rel.sdata ${RELOCATING-0} : { *(.rel.sdata) }
.rel.edata ${RELOCATING-0} : { *(.rel.edata) }
.rel.sbss ${RELOCATING-0} : { *(.rel.sbss) }
.rel.ebss ${RELOCATING-0} : { *(.rel.ebss) }
.rel.eit_v ${RELOCATING-0} : { *(.rel.eit_v) }
.rel.srodata ${RELOCATING-0} : { *(.rel.srodata) }
.rel.erodata ${RELOCATING-0} : { *(.rel.erodata) }
.rel.got ${RELOCATING-0} : { *(.rel.got) }
.rel.ctors ${RELOCATING-0} : { *(.rel.ctors) }
.rel.dtors ${RELOCATING-0} : { *(.rel.dtors) }
.rel.init ${RELOCATING-0} : { *(.rel.init) }
.rel.fini ${RELOCATING-0} : { *(.rel.fini) }
.rel.bss ${RELOCATING-0} : { *(.rel.bss) }
.rel.plt ${RELOCATING-0} : { *(.rel.plt) }
/* Concatenate .page0 sections. Put them in the page0 memory bank
unless we are creating a relocatable file. */
.page0 :
{
*(.page0)
} ${RELOCATING+ > page0}
/* Start of text section. */
.stext ${RELOCATING-0} :
{
*(.stext)
} ${RELOCATING+ > ${TEXT_MEMORY}}
.init ${RELOCATING-0} :
{
*(.init)
} ${RELOCATING+=${NOP-0}}
${RELOCATING-${INSTALL_RELOC}}
.text ${RELOCATING-0}:
{
/* Put startup code at beginning so that _start keeps same address. */
${RELOCATING+${STARTUP_CODE}}
${RELOCATING+*(.init)}
*(.text)
*(.fini)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
${RELOCATING+_etext = .;}
${RELOCATING+PROVIDE (etext = .);}
} ${RELOCATING+ > ${TEXT_MEMORY}}
.eh_frame ${RELOCATING-0} :
{
*(.eh_frame)
} ${RELOCATING+ > ${TEXT_MEMORY}}
.rodata ${RELOCATING-0} :
{
*(.rodata)
*(.gnu.linkonce.r*)
} ${RELOCATING+ > ${TEXT_MEMORY}}
.rodata1 ${RELOCATING-0} :
{
*(.rodata1)
} ${RELOCATING+ > ${TEXT_MEMORY}}
/* Start of the data section image in ROM. */
${RELOCATING+__data_image = .;}
${RELOCATING+PROVIDE (__data_image = .);}
/* All read-only sections that normally go in PROM must be above.
We construct the DATA image section in PROM at end of all these
read-only sections. The data image must be copied at init time.
Refer to GNU ld, Section 3.6.8.2 Output Section LMA. */
.data ${RELOCATING-0} : ${RELOCATING+AT (__data_image)}
{
${RELOCATING+__data_section_start = .;}
${RELOCATING+PROVIDE (__data_section_start = .);}
${RELOCATING+${DATA_START_SYMBOLS}}
${RELOCATING+*(.sdata)}
*(.data)
${RELOCATING+*(.data1)}
*(.gnu.linkonce.d*)
${CONSTRUCTING+CONSTRUCTORS}
${RELOCATING+_edata = .;}
${RELOCATING+PROVIDE (edata = .);}
} ${RELOCATING+ > ${DATA_MEMORY}}
${RELOCATING+__data_section_size = SIZEOF(.data);}
${RELOCATING+PROVIDE (__data_section_size = SIZEOF(.data));}
${RELOCATING+__data_image_end = __data_image + __data_section_size;}
${RELOCATING+${PRE_COMPUTE_DATA_SIZE}}
/* .install ${RELOCATING-0}:
{
. = _data_image_end;
} ${RELOCATING+ > ${TEXT_MEMORY}} */
/* Relocation for some bss and data sections. */
${RELOCATING-${BSS_DATA_RELOC}}
.bss ${RELOCATING-0} :
{
${RELOCATING+__bss_start = .;}
${RELOCATING+*(.sbss)}
${RELOCATING+*(.scommon)}
*(.dynbss)
*(.bss)
*(COMMON)
${RELOCATING+PROVIDE (_end = .);}
} ${RELOCATING+ > ${DATA_MEMORY}}
${RELOCATING+${CTOR}}
${RELOCATING+${DTOR}}
${RELOCATING+${VECTORS}}
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0.
Treatment of DWARF debug section must be at end of the linker
script to avoid problems when there are undefined symbols. It's necessary
to avoid that the DWARF section is relocated before such undefined
symbols are found. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
}
EOF

2
ltconfig
View file

@ -1183,7 +1183,7 @@ EOF
$DLLTOOL --as=$AS --dllname $soname --exclude-symbols DllMain@12,_cygwin_dll_entry@12,_cygwin_noncygwin_dll_entry@12 --def $objdir/$soname-def --base-file $objdir/$soname-base --output-exp $objdir/$soname-exp~
$CC $objdir/$soname-exp -Wl,--dll -nostartfiles -Wl,-e,__cygwin_dll_entry@12 -o $lib $objdir/$soname-ltdll.$objext $libobjs $deplibs $linkopts'
old_archive_from_new_cmds='$DLLTOOL --as=$AS --dllname $soname --def $objdir/$soname-def --output-lib $objdir/$libname.a'
old_archive_from_new_cmds='$DLLTOOL --as=$AS --dllname $soname --def $objdir/$soname-def --output-lib $objdir/$libname.a'
;;
netbsd*)

8
opcodes/Makefile.am
View file

@ -79,6 +79,8 @@ CFILES = \
m32r-ibld.c \
m32r-opc.c \
m32r-opinst.c \
m68hc11-dis.c \
m68hc11-opc.c \
m68k-dis.c \
m68k-opc.c \
m88k-dis.c \
@ -145,6 +147,8 @@ ALL_MACHINES = \
m32r-ibld.lo \
m32r-opc.lo \
m32r-opinst.lo \
m68hc11-dis.lo \
m68hc11-opc.lo \
m68k-dis.lo \
m68k-opc.lo \
m88k-dis.lo \
@ -387,6 +391,10 @@ m32r-opc.lo: m32r-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
m32r-opc.h
m68hc11-dis.lo: m68hc11-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
$(INCDIR)/ansidecl.h $(INCDIR)/floatformat.h \
$(INCDIR)/opcode/m68hc11.h
m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/m68hc11.h
m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/floatformat.h \
opintl.h $(INCDIR)/opcode/m68k.h

10
opcodes/Makefile.in
View file

@ -183,6 +183,8 @@ CFILES = \
m32r-ibld.c \
m32r-opc.c \
m32r-opinst.c \
m68hc11-dis.c \
m68hc11-opc.c \
m68k-dis.c \
m68k-opc.c \
m88k-dis.c \
@ -250,6 +252,8 @@ ALL_MACHINES = \
m32r-ibld.lo \
m32r-opc.lo \
m32r-opinst.lo \
m68hc11-dis.lo \
m68hc11-opc.lo \
m68k-dis.lo \
m68k-opc.lo \
m88k-dis.lo \
@ -330,7 +334,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
TAR = tar
TAR = gtar
GZIP_ENV = --best
SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES)
OBJECTS = libopcodes.a.o $(libopcodes_la_OBJECTS)
@ -885,6 +889,10 @@ m32r-opc.lo: m32r-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
m32r-opc.h
m68hc11-dis.lo: m68hc11-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
$(INCDIR)/ansidecl.h $(INCDIR)/floatformat.h \
$(INCDIR)/opcode/m68hc11.h
m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/m68hc11.h
m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/floatformat.h \
opintl.h $(INCDIR)/opcode/m68k.h

2
opcodes/configure vendored
View file

@ -3957,6 +3957,8 @@ if test x${all_targets} = xfalse ; then
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;

2
opcodes/configure.in
View file

@ -168,6 +168,8 @@ if test x${all_targets} = xfalse ; then
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;

10
opcodes/disassemble.c
View file

@ -37,6 +37,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define ARCH_fr30
#define ARCH_m32r
#define ARCH_m68k
#define ARCH_m68hc11
#define ARCH_m68hc12
#define ARCH_m88k
#define ARCH_mcore
#define ARCH_mips
@ -164,6 +166,14 @@ disassembler (abfd)
disassemble = print_insn_m32r;
break;
#endif
#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12)
case bfd_arch_m68hc11:
disassemble = print_insn_m68hc11;
break;
case bfd_arch_m68hc12:
disassemble = print_insn_m68hc12;
break;
#endif
#ifdef ARCH_m68k
case bfd_arch_m68k:
disassemble = print_insn_m68k;

608
opcodes/m68hc11-dis.c Normal file
View file

@ -0,0 +1,608 @@
/* m68hc11-dis.c -- Motorola 68HC11 & 68HC12 disassembly
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
Written by Stephane Carrez (stcarrez@worldnet.fr)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdio.h>
#include "ansidecl.h"
#include "opcode/m68hc11.h"
#include "dis-asm.h"
static const char *const reg_name[] = {
"X", "Y", "SP", "PC"
};
static const char *const reg_src_table[] = {
"A", "B", "CCR", "TMP3", "D", "X", "Y", "SP"
};
static const char *const reg_dst_table[] = {
"A", "B", "CCR", "TMP2", "D", "X", "Y", "SP"
};
#define OP_PAGE_MASK (M6811_OP_PAGE2|M6811_OP_PAGE3|M6811_OP_PAGE4)
static int
read_memory (memaddr, buffer, size, info)
bfd_vma memaddr;
bfd_byte *buffer;
int size;
struct disassemble_info *info;
{
int status;
/* Get first byte. Only one at a time because we don't know the
size of the insn. */
status = (*info->read_memory_func) (memaddr, buffer, size, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
return 0;
}
/* Read the 68HC12 indexed operand byte and print the corresponding mode.
Returns the number of bytes read or -1 if failure. */
static int
print_indexed_operand (memaddr, info, mov_insn)
bfd_vma memaddr;
struct disassemble_info *info;
int mov_insn;
{
bfd_byte buffer[4];
int reg;
int status;
short sval;
int pos = 1;
status = read_memory (memaddr, &buffer[0], 1, info);
if (status != 0)
{
return status;
}
/* n,r with 5-bits signed constant. */
if ((buffer[0] & 0x20) == 0)
{
reg = (buffer[0] >> 6) & 3;
sval = (buffer[0] & 0x1f);
if (sval & 0x10)
sval |= 0xfff0;
(*info->fprintf_func) (info->stream, "%d,%s",
(int) sval, reg_name[reg]);
}
/* Auto pre/post increment/decrement. */
else if ((buffer[0] & 0xc0) != 0xc0)
{
const char *mode;
reg = (buffer[0] >> 6) & 3;
sval = (buffer[0] & 0x0f);
if (sval & 0x8)
{
sval |= 0xfff0;
sval = -sval;
mode = "-";
}
else
{
sval = sval + 1;
mode = "+";
}
(*info->fprintf_func) (info->stream, "%d,%s%s%s",
(int) sval,
(buffer[0] & 0x10 ? "" : mode),
reg_name[reg], (buffer[0] & 0x10 ? mode : ""));
}
/* [n,r] 16-bits offset indexed indirect. */
else if ((buffer[0] & 0x07) == 3)
{
if (mov_insn)
{
(*info->fprintf_func) (info->stream, "<invalid op: 0x%x>",
buffer[0] & 0x0ff);
return 0;
}
reg = (buffer[0] >> 3) & 0x03;
status = read_memory (memaddr + pos, &buffer[0], 2, info);
if (status != 0)
{
return status;
}
pos += 2;
sval = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
(*info->fprintf_func) (info->stream, "[%u,%s]",
sval & 0x0ffff, reg_name[reg]);
}
else if ((buffer[0] & 0x4) == 0)
{
if (mov_insn)
{
(*info->fprintf_func) (info->stream, "<invalid op: 0x%x>",
buffer[0] & 0x0ff);
return 0;
}
reg = (buffer[0] >> 3) & 0x03;
status = read_memory (memaddr + pos,
&buffer[1], (buffer[0] & 0x2 ? 2 : 1), info);
if (status != 0)
{
return status;
}
if (buffer[0] & 2)
{
sval = ((buffer[1] << 8) | (buffer[2] & 0x0FF));
sval &= 0x0FFFF;
pos += 2;
}
else
{
sval = buffer[1] & 0x00ff;
if (buffer[0] & 0x01)
sval |= 0xff00;
pos++;
}
(*info->fprintf_func) (info->stream, "%d,%s",
(int) sval, reg_name[reg]);
}
else
{
reg = (buffer[0] >> 3) & 0x03;
switch (buffer[0] & 3)
{
case 0:
(*info->fprintf_func) (info->stream, "A,%s", reg_name[reg]);
break;
case 1:
(*info->fprintf_func) (info->stream, "B,%s", reg_name[reg]);
break;
case 2:
(*info->fprintf_func) (info->stream, "D,%s", reg_name[reg]);
break;
case 3:
default:
(*info->fprintf_func) (info->stream, "[D,%s]", reg_name[reg]);
break;
}
}
return pos;
}
/* Disassemble one instruction at address 'memaddr'. Returns the number
of bytes used by that instruction. */
static int
print_insn (memaddr, info, arch)
bfd_vma memaddr;
struct disassemble_info *info;
int arch;
{
int status;
bfd_byte buffer[4];
unsigned char code;
long format, pos, i;
short sval;
const struct m68hc11_opcode *opcode;
/* Get first byte. Only one at a time because we don't know the
size of the insn. */
status = read_memory (memaddr, buffer, 1, info);
if (status != 0)
{
return status;
}
format = 0;
code = buffer[0];
pos = 0;
/* Look for page2,3,4 opcodes. */
if (code == M6811_OPCODE_PAGE2)
{
pos++;
format = M6811_OP_PAGE2;
}
else if (code == M6811_OPCODE_PAGE3 && arch == cpu6811)
{
pos++;
format = M6811_OP_PAGE3;
}
else if (code == M6811_OPCODE_PAGE4 && arch == cpu6811)
{
pos++;
format = M6811_OP_PAGE4;
}
/* We are in page2,3,4; get the real opcode. */
if (pos == 1)
{
status = read_memory (memaddr + pos, &buffer[1], 1, info);
if (status != 0)
{
return status;
}
code = buffer[1];
}
/* Look first for a 68HC12 alias. All of them are 2-bytes long and
in page 1. There is no operand to print. We read the second byte
only when we have a possible match. */
if ((arch & cpu6812) && format == 0)
{
int must_read = 1;
/* Walk the alias table to find a code1+code2 match. */
for (i = 0; i < m68hc12_num_alias; i++)
{
if (m68hc12_alias[i].code1 == code)
{
if (must_read)
{
status = read_memory (memaddr + pos + 1,
&buffer[1], 1, info);
if (status != 0)
break;
must_read = 1;
}
if (m68hc12_alias[i].code2 == (unsigned char) buffer[1])
{
(*info->fprintf_func) (info->stream, "%s",
m68hc12_alias[i].name);
return 2;
}
}
}
}
pos++;
/* Scan the opcode table until we find the opcode
with the corresponding page. */
opcode = m68hc11_opcodes;
for (i = 0; i < m68hc11_num_opcodes; i++, opcode++)
{
int offset;
if ((opcode->arch & arch) == 0)
continue;
if (opcode->opcode != code)
continue;
if ((opcode->format & OP_PAGE_MASK) != format)
continue;
if (opcode->format & M6812_OP_REG)
{
int j;
int is_jump;
if (opcode->format & M6811_OP_JUMP_REL)
is_jump = 1;
else
is_jump = 0;
status = read_memory (memaddr + pos, &buffer[0], 1, info);
if (status != 0)
{
return status;
}
for (j = 0; i + j < m68hc11_num_opcodes; j++)
{
if ((opcode[j].arch & arch) == 0)
continue;
if (opcode[j].opcode != code)
continue;
if (is_jump)
{
if (!(opcode[j].format & M6811_OP_JUMP_REL))
continue;
if ((opcode[j].format & M6812_OP_IBCC_MARKER)
&& (buffer[0] & 0xc0) != 0x80)
continue;
if ((opcode[j].format & M6812_OP_TBCC_MARKER)
&& (buffer[0] & 0xc0) != 0x40)
continue;
if ((opcode[j].format & M6812_OP_DBCC_MARKER)
&& (buffer[0] & 0xc0) != 0)
continue;
if ((opcode[j].format & M6812_OP_EQ_MARKER)
&& (buffer[0] & 0x20) == 0)
break;
if (!(opcode[j].format & M6812_OP_EQ_MARKER)
&& (buffer[0] & 0x20) != 0)
break;
continue;
}
if (opcode[j].format & M6812_OP_EXG_MARKER && buffer[0] & 0x80)
break;
if ((opcode[j].format & M6812_OP_SEX_MARKER)
&& (((buffer[0] & 0x07) >= 3 && (buffer[0] & 7) <= 7))
&& ((buffer[0] & 0x0f0) <= 0x20))
break;
if (opcode[j].format & M6812_OP_TFR_MARKER
&& !(buffer[0] & 0x80))
break;
}
if (i + j < m68hc11_num_opcodes)
opcode = &opcode[j];
}
/* We have found the opcode. Extract the operand and print it. */
(*info->fprintf_func) (info->stream, "%s", opcode->name);
format = opcode->format;
if (format & (M6811_OP_MASK | M6811_OP_BITMASK
| M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
{
(*info->fprintf_func) (info->stream, "\t");
}
/* The movb and movw must be handled in a special way... */
offset = 0;
if (format & (M6812_OP_IDX_P2 | M6812_OP_IND16_P2))
{
if ((format & M6812_OP_IDX_P2)
&& (format & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_IND16)))
offset = 1;
}
/* Operand with one more byte: - immediate, offset,
direct-low address. */
if (format &
(M6811_OP_IMM8 | M6811_OP_IX | M6811_OP_IY | M6811_OP_DIRECT))
{
status = read_memory (memaddr + pos + offset, &buffer[0], 1, info);
if (status != 0)
{
return status;
}
pos++;
offset = -1;
if (format & M6811_OP_IMM8)
{
(*info->fprintf_func) (info->stream, "#%d", (int) buffer[0]);
format &= ~M6811_OP_IMM8;
}
else if (format & M6811_OP_IX)
{
/* Offsets are in range 0..255, print them unsigned. */
(*info->fprintf_func) (info->stream, "%u,x", buffer[0] & 0x0FF);
format &= ~M6811_OP_IX;
}
else if (format & M6811_OP_IY)
{
(*info->fprintf_func) (info->stream, "%u,y", buffer[0] & 0x0FF);
format &= ~M6811_OP_IY;
}
else if (format & M6811_OP_DIRECT)
{
(*info->fprintf_func) (info->stream, "*");
(*info->print_address_func) (buffer[0] & 0x0FF, info);
format &= ~M6811_OP_DIRECT;
}
}
#define M6812_INDEXED_FLAGS (M6812_OP_IDX|M6812_OP_IDX_1|M6812_OP_IDX_2)
/* Analyze the 68HC12 indexed byte. */
if (format & M6812_INDEXED_FLAGS)
{
status = print_indexed_operand (memaddr + pos, info, 0);
if (status < 0)
{
return status;
}
pos += status;
}
/* 68HC12 dbcc/ibcc/tbcc operands. */
if ((format & M6812_OP_REG) && (format & M6811_OP_JUMP_REL))
{
status = read_memory (memaddr + pos, &buffer[0], 2, info);
if (status != 0)
{
return status;
}
(*info->fprintf_func) (info->stream, "%s,",
reg_src_table[buffer[0] & 0x07]);
sval = buffer[1] & 0x0ff;
if (buffer[0] & 0x10)
sval |= 0xff00;
pos += 2;
(*info->print_address_func) (memaddr + pos + sval, info);
format &= ~(M6812_OP_REG | M6811_OP_JUMP_REL);
}
else if (format & (M6812_OP_REG | M6812_OP_REG_2))
{
status = read_memory (memaddr + pos, &buffer[0], 1, info);
if (status != 0)
{
return status;
}
pos++;
(*info->fprintf_func) (info->stream, "%s,%s",
reg_src_table[(buffer[0] >> 4) & 7],
reg_dst_table[(buffer[0] & 7)]);
}
/* M6811_OP_BITMASK and M6811_OP_JUMP_REL must be treated separately
and in that order. The brset/brclr insn have a bitmask and then
a relative branch offset. */
if (format & M6811_OP_BITMASK)
{
status = read_memory (memaddr + pos, &buffer[0], 1, info);
if (status != 0)
{
return status;
}
pos++;
(*info->fprintf_func) (info->stream, " #$%02x%s",
buffer[0] & 0x0FF,
(format & M6811_OP_JUMP_REL ? " " : ""));
format &= ~M6811_OP_BITMASK;
}
if (format & M6811_OP_JUMP_REL)
{
int val;
status = read_memory (memaddr + pos, &buffer[0], 1, info);
if (status != 0)
{
return status;
}
pos++;
val = (buffer[0] & 0x80) ? buffer[0] | 0xFFFFFF00 : buffer[0];
(*info->print_address_func) (memaddr + pos + val, info);
format &= ~M6811_OP_JUMP_REL;
}
else if (format & M6812_OP_JUMP_REL16)
{
int val;
status = read_memory (memaddr + pos, &buffer[0], 2, info);
if (status != 0)
{
return status;
}
pos += 2;
val = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
if (val & 0x8000)
val |= 0xffff0000;
(*info->print_address_func) (memaddr + pos + val, info);
format &= ~M6812_OP_JUMP_REL16;
}
if (format & (M6811_OP_IMM16 | M6811_OP_IND16))
{
int val;
status = read_memory (memaddr + pos + offset, &buffer[0], 2, info);
if (status != 0)
{
return status;
}
if (format & M6812_OP_IDX_P2)
offset = -2;
else
offset = 0;
pos += 2;
val = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
val &= 0x0FFFF;
if (format & M6811_OP_IMM16)
{
format &= ~M6811_OP_IMM16;
(*info->fprintf_func) (info->stream, "#");
}
else
format &= ~M6811_OP_IND16;
(*info->print_address_func) (val, info);
}
if (format & M6812_OP_IDX_P2)
{
(*info->fprintf_func) (info->stream, ", ");
status = print_indexed_operand (memaddr + pos + offset, info, 1);
if (status < 0)
return status;
pos += status;
}
if (format & M6812_OP_IND16_P2)
{
int val;
(*info->fprintf_func) (info->stream, ", ");
status = read_memory (memaddr + pos + offset, &buffer[0], 2, info);
if (status != 0)
{
return status;
}
pos += 2;
val = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
val &= 0x0FFFF;
(*info->print_address_func) (val, info);
}
#ifdef DEBUG
/* Consistency check. 'format' must be 0, so that we have handled
all formats; and the computed size of the insn must match the
opcode table content. */
if (format & ~(M6811_OP_PAGE4 | M6811_OP_PAGE3 | M6811_OP_PAGE2))
{
(*info->fprintf_func) (info->stream, "; Error, format: %x", format);
}
if (pos != opcode->size)
{
(*info->fprintf_func) (info->stream, "; Error, size: %d expect %d",
pos, opcode->size);
}
#endif
return pos;
}
/* Opcode not recognized. */
if (format == M6811_OP_PAGE2 && arch & cpu6812
&& ((code >= 0x30 && code <= 0x39) || (code >= 0x40 && code <= 0xff)))
(*info->fprintf_func) (info->stream, "trap\t#%d", code & 0x0ff);
else if (format == M6811_OP_PAGE2)
(*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x",
M6811_OPCODE_PAGE2, code);
else if (format == M6811_OP_PAGE3)
(*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x",
M6811_OPCODE_PAGE3, code);
else if (format == M6811_OP_PAGE4)
(*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x",
M6811_OPCODE_PAGE4, code);
else
(*info->fprintf_func) (info->stream, ".byte\t0x%02x", code);
return pos;
}
/* Disassemble one instruction at address 'memaddr'. Returns the number
of bytes used by that instruction. */
int
print_insn_m68hc11 (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
return print_insn (memaddr, info, cpu6811);
}
int
print_insn_m68hc12 (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
return print_insn (memaddr, info, cpu6812);
}

1074
opcodes/m68hc11-opc.c Normal file
View file

File diff suppressed because it is too large Load diff

2
opcodes/po/POTFILES.in
View file

@ -54,6 +54,8 @@ m32r-ibld.c
m32r-opc.c
m32r-opc.h
m32r-opinst.c
m68hc11-dis.c
m68hc11-opc.c
m68k-dis.c
m68k-opc.c
m88k-dis.c

19
opcodes/po/opcodes.pot
View file

@ -6,7 +6,7 @@
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"POT-Creation-Date: 2000-05-30 11:33-0700\n"
"POT-Creation-Date: 2000-06-18 17:38-0700\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
@ -69,6 +69,19 @@ msgid ""
"the -M switch:\n"
msgstr ""
#: avr-dis.c:106
msgid " unknown register "
msgstr ""
#: avr-dis.c:168
msgid "Internal disassembler error"
msgstr ""
#: avr-dis.c:208
#, c-format
msgid "unknown constraint `%c'"
msgstr ""
#: cgen-asm.c:224
msgid "unrecognized keyword/register name"
msgstr ""
@ -171,12 +184,12 @@ msgstr ""
msgid "Unrecognized field %d while setting vma operand.\n"
msgstr ""
#: h8300-dis.c:405
#: h8300-dis.c:382
#, c-format
msgid "Hmmmm %x"
msgstr ""
#: h8300-dis.c:417
#: h8300-dis.c:393
#, c-format
msgid "Don't understand %x \n"
msgstr ""