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Add support for MIPS R1[02]000 performance counter opcodes.

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Thiemo Seufer 2001-08-16 19:24:33 +00:00
parent 2cd8959083
commit 99c14723f3
8 changed files with 50 additions and 5 deletions
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6
gas/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
* gas/mips/mips.exp: Added performance counter test.
* gas/mips/perfcount.s: New File. Test of performance counter opcodes.
* gas/mips/perfcount.d: Likewise.
2001-08-12 Nick Clifton <nickc@cambridge.redhat.com>
* gas/sparc/unalign.s: Extend test to check .uaword with multiple

1
gas/testsuite/gas/mips/mips.exp
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@ -111,6 +111,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mips4010"
run_dump_test "mips4650"
run_dump_test "mips4100"
run_dump_test "perfcount"
# Linux uses ELF stabs, which doesn't support line number.
setup_xfail "mips*-*-*linux*"
run_dump_test "lineno"

11
gas/testsuite/gas/mips/perfcount.d Normal file
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@ -0,0 +1,11 @@
#objdump: -dr --prefix-addresses -mmips:10000
#name: MIPS R1[20]000 performance counters
#as: -mips4 -march=r10000
.*: +file format .*mips.*
Disassembly of section .text:
0+0000 <[^>]*> mtps a0,0
0+0004 <[^>]*> mfps a0,1
0+0008 <[^>]*> mtpc a0,1
0+000c <[^>]*> mfpc a0,0

7
gas/testsuite/gas/mips/perfcount.s Normal file
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@ -0,0 +1,7 @@
# source file to test assembly of R1[20]000 performance counter instructions.
foo:
mtps $4, 0
mfps $4, 1
mtpc $4, 1
mfpc $4, 0

5
include/opcode/ChangeLog
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@ -1,3 +1,8 @@
2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
* mips.h (INSN_10000): Define.
(OPCODE_IS_MEMBER): Check for INSN_10000.
2001-08-10 Alan Modra <amodra@one.net.au>
* ppc.h: Revert 2001-08-08.

6
include/opcode/mips.h
View file

@ -326,6 +326,8 @@ struct mips_opcode
#define INSN_4100 0x00040000
/* Toshiba R3900 instruction. */
#define INSN_3900 0x00080000
/* MIPS R10000 instruction. */
#define INSN_10000 0x00100000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@ -375,7 +377,9 @@ struct mips_opcode
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
&& ((insn)->membership & INSN_4100) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
&& ((insn)->membership & INSN_10000) != 0))
/* This is a list of macro expanded instructions.

6
opcodes/ChangeLog
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@ -1,3 +1,9 @@
2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
* mips-opc.c (M1): Define. Reformatted Code.
(mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps,
mtps, mtps. Typo.
2001-08-16 Jonathan Larmour <jlarmour@redhat.com>
* mips-opc.c: R3900s can support all branch likely INSN_MACROs where

13
opcodes/mips-opc.c
View file

@ -86,15 +86,16 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
#define L1 INSN_4010
#define V1 INSN_4100
#define T3 INSN_3900
#define M1 INSN_10000
#define G1 (T3 \
)
#define G2 (T3 \
#define G2 (T3 \
)
#define G3 (I4 \
)
#define G3 (I4 \
)
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
@ -557,6 +558,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, V1 },
{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
@ -594,6 +597,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32 },
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32 },
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1 },
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1 },
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
@ -836,7 +841,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
disasembler recognizes more specific versions first. */
disassembler recognizes more specific versions first. */
{"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
{"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },