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175 commits

Author SHA1 Message Date
Andrew Cagney
37379a256b IGEN - Replace IMEM (IMEM_IMMED) macro with IMEM<insn-size> macro, 
update v850, tic80 and mips simulators.
IGEN - Prepend prefix to more generated symbols and macros
(idecode_issue, instruction_word).
IGEN - Add -Wnowith option to supress warnings about word size
inflicts in input files.
MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so
that a mips16 simulator built using IGEN can be compiled.
 1998-02-03 05:39:15 +00:00
Andrew Cagney
4634263c4c Make IGEN the generator for all but mips16 simulators. 
Clean up botched merge in interp.c:sim_open().
 1998-02-02 14:14:17 +00:00
Andrew Cagney
a97f304b04 Add support for configuring the size of the floating point unit (fp_word). 
For mips, move fp_registers into a separate array of type fp_word[].
 1998-02-02 14:06:52 +00:00
Andrew Cagney
2acd126a47 Rewrite the mipsI/II/III pending-slot code. 1998-02-02 13:49:17 +00:00
Andrew Cagney
192ae475f9 Always compile FP code (test for FP at run-time). 
Remove dependance of interp.c on gencode.c's output.
 1998-02-02 08:25:33 +00:00
Andrew Cagney
01737f42d8 mips: Add multi-processor support for r5900. Others might work. 
common, igen: Fix MP related bugs.
 1998-02-01 03:29:48 +00:00
Andrew Cagney
412c4e940e Add config support for the size of the target address and OF cell. 1998-01-31 14:07:23 +00:00
Andrew Cagney
c4db5b04f8 mips - for r5900 generate igen simulator. 
igen - stop crash when simulator isn't multi-sim'ed
 1998-01-31 06:56:13 +00:00
Andrew Cagney
9ec6741b17 igen: Fix SMP simulator generator support. 
Use the bfd-processor name in the sim-engine switch.
	Add nr_cpus argument to sim_engine_run.
tic80, v850, d30v, mips, common:
	Update
mips:	Fill in bfd-processor field of model records so that
	they match ../bfd/archures.
 1998-01-31 06:23:41 +00:00
Andrew Cagney
2d44e12a27 Use macro GPR_SET(N,VAL) to clear zero registers. 1998-01-21 22:08:37 +00:00
Doug Evans
462cfbc4eb * aclocal.m4: Recognize --enable-maintainer-mode. 
*/configure: Regenerated.
 1998-01-20 06:37:00 +00:00
Andrew Cagney
13151a934d Document existence of old (gencode) and new (igen) MIPS ISA simulators. 1998-01-16 01:09:15 +00:00
Mark Alexander
e0e0fc765e * interp.c (sim_monitor): Handle Densan monitor outbyte 
and inbyte functions.
 1998-01-05 23:43:30 +00:00
Felix Lee
76ef416550 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). 1997-12-29 16:03:23 +00:00
Andrew Cagney
9c8ec16d78 In nrun.c, look for sigaction & SA_RESTART. When both present, 
install cntrl-c (SIGINT) handler with no SA_RESTART bit set.
 1997-12-15 12:33:59 +00:00
Andrew Cagney
b17d2d1474 For MADD et.al. instructions sign extend 32 bit result assigned to a 
register.
 1997-12-13 04:23:31 +00:00
Jeff Law
255cbbf190 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or 
vr5400 with the vr5000 as the default.
 1997-12-12 19:24:34 +00:00
Jeff Law
23850e9219 * mips.igen (MSUB): Fix to work like MADD. 
* gencode.c (MSUB): Similarly.
 1997-12-11 00:11:04 +00:00
Andrew Cagney
c02ed6a8a3 For bfd, add vr5400 and vr5000 mips machine variants to list of machines. 
For sim/mips, enable multi-sim support when mips64vr5400-elf is target.
For sim/igen, allow specification of a default machine (will need
more work later).
 1997-12-09 04:01:06 +00:00
Doug Evans
6e51f990a2 Regenerate configure files. 1997-12-04 17:26:06 +00:00
Andrew Cagney
0931ce5aa7 Missing change log entry. 1997-12-03 22:54:44 +00:00
Andrew Cagney
0d5d0d102d Fix typo in format argument to sim_io_eprintf. 1997-11-26 12:07:27 +00:00
Andrew Cagney
35c246c9d7 Move MDMX instructions which are public knowledge from vr5400.igen 
into mdmx.igen (MDMX is MMX on steroids).  Keep the file secret.
 1997-11-26 11:47:36 +00:00
Andrew Cagney
8c31916d92 sanitize-r5900 not v5900 1997-11-25 22:02:59 +00:00
Andrew Cagney
58fb5d0a4f vr5400 sanitize cleanups 1997-11-25 21:47:16 +00:00
Andrew Cagney
9dcdd9ad73 Sanitization 1997-11-24 13:34:52 +00:00
Andrew Cagney
232156dee9 o Add SIM_SIGFPE to sim-signals 
o Start SIM_SIG* at 64 so that the use of host signal numbers can be
  detected and reported.
o Update MIPS simulator to use sim-signal.
 1997-11-20 09:50:36 +00:00
Andrew Cagney
a09a30d298 Allow reads/writes to C0_CONFIG register. 1997-11-20 09:17:06 +00:00
Doug Evans
486740ce01 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). 1997-11-18 23:40:40 +00:00
Andrew Cagney
f23e93dab0 * mips.igen: Tag vr5000 instructions. 
(ANDI): Was missing mipsIV model, fix assembler syntax.
        (do_c_cond_fmt): New function.
        (C.cond.fmt): Handle mips I-III which do not support CC field
        separatly.
        (bc1): Handle mips IV which do not have a delaed FCC separatly.
        (SDR): Mask paddr when BigEndianMem, not the converse as specified
        in IV3.2 spec.
        (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
        vr5000 which saves LO in a GPR separatly.
        * configure.in (enable-sim-igen): For vr5000, select vr5000
        specific instructions.
        * configure: Re-generate.
 1997-11-14 08:27:38 +00:00
Andrew Cagney
a94c5493a7 Make the signess of compares between GPR's explicit using a cast to 
signed_word.
 1997-11-11 12:31:24 +00:00
Andrew Cagney
030843d7f8 Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, 
SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI,
MFHI instructions.
Trace nullified instruction.
 1997-11-11 07:50:13 +00:00
Andrew Cagney
95469cebdd Replace global IPC with function argument cia or current instruction 
address.
Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
 1997-11-06 14:24:57 +00:00
Andrew Cagney
7ce8b9178c IGEN likes to cache the current instruction address (CIA). Change the 
MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
 1997-11-06 09:16:16 +00:00
Andrew Cagney
44b8585a3d Add option --enable-sim-igen to mips configuration. Allows user to 
attempt a build of an older MIPS simulator using igen.
 1997-11-05 09:43:34 +00:00
Andrew Cagney
63be8febf7 Rewrite the MIPS simulator's memory model so that it uses the generic 
common/sim-core.

Add support for 3, 5, 6, 7 byte transfers to sim core.
 1997-11-05 08:17:26 +00:00
Andrew Cagney
22de994d0e Delete -l and -n options, didn't do anything. 
Rename option trace to dinero-trace & dinero-file - -t clashed with
common options.
Enable common trace options.
 1997-11-05 01:08:12 +00:00
Andrew Cagney
525d929e49 Rewrite sim_monitor (implements read, write, open, et.al. system 
calls) and sim_open so that they uses the virtual memory data transfer
functions sim_read & sim_write.  This eliminates all code (other than
in load_memory & store_memory) that makes assumptions about the
implementation of the underlying memory model.
 1997-11-05 00:08:14 +00:00
Gavin Romig-Koch
0425cfb3af Correct r5900 sanitization. 1997-11-04 05:50:22 +00:00
Gavin Romig-Koch
6205f37913 * gencode.c: Add tx49 configury and insns. 
* configure.in: Add tx49 configury.
	* configure: Update.
 1997-10-29 19:42:49 +00:00
Andrew Cagney
01b9cd49ca common/sim-bits.h: Document ROTn macro. 
igen/{igen.c,ld-insns.h}: Document mnemonic string formats.
mips/Makefile.in: Add dependencies for files included by mips.igen
mips/vr5400.igen: checkpoint vr5400 instructions.
 1997-10-29 04:02:30 +00:00
Andrew Cagney
89d0973831 Add support for 16 byte quantities to sim-endian macro H2T. 
Add model-filter field to option, include, model anf function igen records
 1997-10-28 07:10:36 +00:00
Andrew Cagney
16bd5d6e52 Separate r5900 specifoc and mips16 instructions. 
Add support for this to configure (vr5400 target only)
 1997-10-27 07:55:24 +00:00
Andrew Cagney
90ad43b2de Add mips64vr5400 to configuration list 
Mark mipsIV instructions as being implemented by the vr5400.
Sanitize.
 1997-10-27 06:42:13 +00:00
Gavin Romig-Koch
635ae9cb7c * sim/mips/gencode.c (build_instruction): Follow sim_write's lead in using 
BigEndianMem instead of !ByteSwapMem.
 1997-10-25 20:53:46 +00:00
Andrew Cagney
122edc03de Add basic igen configuration to autoconf. Disable. 1997-10-24 07:54:21 +00:00
Andrew Cagney
dad6f1f326 Add function to fetch 32bit instructions 
When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
 1997-10-24 06:43:51 +00:00
Andrew Cagney
49a7683337 Checkpoint IGEN version of mips sim 1997-10-24 06:38:44 +00:00
Andrew Cagney
92ad193bb0 Use SIM*_OVERFLOW_RESULT defined in sim-alu.h 1997-10-21 07:57:33 +00:00
Andrew Cagney
aa324b9b1e Output pc profile statistics once gathered. 1997-10-21 07:40:00 +00:00