old-cross-binutils/sim/mips
Andrew Cagney 525d929e49 Rewrite sim_monitor (implements read, write, open, et.al. system
calls) and sim_open so that they uses the virtual memory data transfer
functions sim_read & sim_write.  This eliminates all code (other than
in load_memory & store_memory) that makes assumptions about the
implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
..
.Sanitize * gencode.c: Add tx49 configury and insns. 1997-10-29 19:42:49 +00:00
ChangeLog Rewrite sim_monitor (implements read, write, open, et.al. system 1997-11-05 00:08:14 +00:00
config.in Get configure to define RETSIGTYPE 1997-04-07 05:58:59 +00:00
configure * gencode.c: Add tx49 configury and insns. 1997-10-29 19:42:49 +00:00
configure.in * gencode.c: Add tx49 configury and insns. 1997-10-29 19:42:49 +00:00
gencode.c * gencode.c: Add tx49 configury and insns. 1997-10-29 19:42:49 +00:00
interp.c Rewrite sim_monitor (implements read, write, open, et.al. system 1997-11-05 00:08:14 +00:00
m16.igen Separate r5900 specifoc and mips16 instructions. 1997-10-27 07:55:24 +00:00
Makefile.in common/sim-bits.h: Document ROTn macro. 1997-10-29 04:02:30 +00:00
mips.dc MIPS/IGEN checkpoint - doesn't build. 1997-10-08 04:16:01 +00:00
mips.igen common/sim-bits.h: Document ROTn macro. 1997-10-29 04:02:30 +00:00
README.Cygnus Initial check-in of the MIPS simulator. Work still needs to be done on 1995-11-08 15:44:38 +00:00
sim-main.h Rewrite sim_monitor (implements read, write, open, et.al. system 1997-11-05 00:08:14 +00:00
tconfig.in * Makefile.in: Delete stuff moved to ../common/Make-common.in. 1996-11-20 10:00:42 +00:00
vr5400.igen common/sim-bits.h: Document ROTn macro. 1997-10-29 04:02:30 +00:00

> README.Cygnus
-------------------------------------------------------------------------------

The following are the main reasons for constructing the simulator as a
generator:

1) Avoid large fixed decode source file, with lots of #ifs controlling
   the compilation. i.e. keep the source cleaner, smaller and easier
   to parse.

2) Allow optimum code to be created, without run-time checks on
   instruction types. Ensure that the simulator engine only includes
   code for the architecture being targetted. e.g. This avoids
   run-time checks on ISA conformance, aswell as increasing
   throughput.

3) Allow updates to the instruction sets to be added quickly. Having a
   table means that the information is together, and is easier to
   manipulate. Having the table generate the engine, rather than the
   run-time parse the table gives higher performance at simulation
   time.

4) Keep all the similar simulation code together. i.e. have a single
   place where, for example, the addition code is held. This ensures that
   updates to the simulation are not spread over a large flat source
   file maintained by the developer.

-------------------------------------------------------------------------------

To keep the simulator simple (and to avoid the slight chance of
mis-matched files) the manifests describing an engine, and the
simulator engine itself, are held in the same source file.

This means that the engine must be included twice, with the first pass
controlled by the SIM_MANIFESTS definition.

-------------------------------------------------------------------------------
> EOF README.Cygnus