This patch enables x32 for x86_64-*-elf* for embedded target and disables
rex tests since it uses '/' as prefix separator which is `\' for
x86_64-*-elf*.
bfd/
* config.bfd (targ_selvecs): Add bfd_elf32_x86_64_vec for
x86_64-*-elf*.
gas/testsuite/
* gas/i386/rex.d: Skip x86_64-*-elf*.
* gas/i386/ilp32/rex.d: Likewise.
ld/
* configure.tgt (targ_extra_emuls): Adds elf32_x86_64 for
x86_64-*-elf*.
(targ_extra_libpath): Likewise.
(tdir_elf_i386): Replace x86_64 with i386 for x86_64-*-elf*.
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base
register being PC when is_t or writeback, and use distinct
diagnostic for the latter case.
gas/testsuite/
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/testsuite/gas/arm/ldst-pc.s: Add index, non-writeback
forms of various loads and stores with PC as base.
* gas/testsuite/gas/arm/ldst-pc.d: Update accordingly.
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (parse_operands): Re-write
po_barrier_or_imm().
(do_barrier): Remove bogus constraint().
(do_t_barrier): Remove.
gas/testsuite/
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/arm/barrier-bad.d: Change title.
* gas/arm/barrier-bad.s: Add immediate form of ISB and DSB as
well as one symbolic form of DSB.
* gas/arm/barrier-bad.l: Update accordingly.
* gas/arm/barrier-bad-thumb.d: Adjust title. Use barrier-bad.s as
source. Pass -mthumb to gas.
* gas/arm/barrier-bad-thumb.l: Remove.
* gas/arm/barrier-bad-thumb.s: Remove.
* gas/arm/barrier-thumb.d: Adjust title. Use barrier.s as source.
Pass -mthumb to gas.
* gas/arm/barrier-thumb.s: Remove.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_vmrs): Accept all control registers.
Use local variable Rt in more places.
(do_vmsr): Accept all control registers.
gas/testsuite/
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/vfp1xD.s: Add VMRS/VMSR tests with FPINST, FPINST2,
and C15.
* gas/arm/vfp1xD.d: Update accordingly.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
if there was none specified for moves between scalar and core
register.
gas/testsuite/
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-omit.s: Add tests for suffix less VMOV.
* gas/arm/neon-omit.d: Update accordingly.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the
NEON_ALL_LANES case.
gas/testsuite/
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-addressing-bad.s: Add test for further invalid VST
operands.
* gas/arm/neon-addressing-bad.l: Update accordingly.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
* gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add
and xor.
* gas/tic6x/insns16-lsd-unit.d: Update expected output.
2013-03-26 Douglas B Rupp <rupp@gnat.com>
* config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment
after fixup.
gas/testsuite/
2013-03-26 Douglas B Rupp <rupp@adacore.com
* gas/ia64/ia64.exp: Add new test reloc-mlx
* gas/ia64/reloc-mlx.[sd]: New test for X-unit reloc.
* gas/ia64/pcrel.d: Fix output for X-unit reloc.
2013-03-21 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all
pc-relative str instructions in Thumb mode.
gas/testsuite/ChangeLog:
2013-03-21 Will Newton <will.newton@linaro.org>
* gas/arm/thumb2_relax.d: Strip out invalid pc-relative strs.
* gas/arm/thumb2_relax.s: Likewise.
* gas/arm/thumb32.d: Likewise.
* gas/arm/thumb32.l: Likewise.
* gas/arm/thumb32.s: Likewise.
* gas/arm/thumb2_str-bad.d: New file.
* gas/arm/thumb2_str-bad.l: Likewise.
* gas/arm/thumb2_str-bad.s: Likewise.
* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
tic6x_operand_xregpair operand coding type.
Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
opcode field, usu ORXREGD1324 for the src2 operand and remove the
TIC6X_FLAG_NO_CROSS.
* gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with
cross-path.
* gas/tic6x/insns-bad-1.l: Update expected output.
* gas/tic6x/insns-c674x.s: Add a test-case for mpydp with
cross-path.
* gas/tic6x/insns-c674x.d: Update expected output.
order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.
* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types
and use it to encode register pair numbers when required.
* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.
* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.
* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.
2013-03-12 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_neon_ldr_str): Fix error check for PC register
in vstr in Thumb mode for pre-ARMv7 cores.
gas/testsuite/ChangeLog:
2013-03-12 Will Newton <will.newton@linaro.org>
* gas/arm/vstr-thumb-bad.d: Assemble with -mcpu=arm1156t2f-s.
opcodes/
* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
gas/testsuite/
* gas/nios2/nios2.exp: Run registers.
* gas/nios2/registers.d: New file.
* gas/nios2/registers.s: Likewise.
* config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
for system registers.
gas/testsuite/
* gas/aarch64/illegal.l: Delete the error message for
msr S3_1_C13_C15_1,x7.
* gas/aarch64/sysreg.s: Add new tests.
* gas/aarch64/sysreg.d: Update.
which also makes the disassembler output be in little
endian like it should be.
* metag/labelarithmetic.d: Fix the expected disassembler
output to be in little endian format
* metag/metacore12.d: likewise
* metag/metacore21.d: likewise
* metag/metacore21ext.d: likewise
* metag/metadsp21.d: likewise
* metag/metadsp21ext.d: likewise
* metag/metafpu.d: likewise
* metag/metafpuext.d: likewise
* metag/tls.d: likewise
* ld-metag/pcrel.d: Fix the expected disassembler
output to be in little endian format
* ld-metag/shared.d: likewise
* ld-metag/stub.d: likewise
* ld-metag/stub_pic_app.d: likewise
* ld-metag/stub_pic_shared.d: likewise
* ld-metag/stub_shared.d: likewise
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
(macro): Use it. Assert that trunc.w.s is not used for r5900.
opcodes/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
single-float. Disable ll, lld, sc and scd for EE. Disable the
trunc.w.s macro for EE.
gas/testsuite/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/24k-triple-stores-2.d, gas/mips/24k-triple-stores-2.s,
gas/mips/micromips@24k-triple-stores-2.d: Move "sc" tests to...
* gas/mips/24k-triple-stores-2-llsc.d,
gas/mips/24k-triple-stores-2-llsc.s,
gas/mips/micromips@24k-triple-stores-2-llsc.d: ...these new tests.
* gas/mips/r5900-full.d, gas/mips/r5900-full.s: Verify that the
MIPS ISA level can be upgraded to support ll, sc, lld and scd.
* gas/mips/l_d-single.d, gas/mips/s_d-single.d,
gas/mips/r5900-nollsc.l, gas/mips/r5900-nollsc.s: New tests.
* gas/mips/mips.exp: Update accordingly. Add "nollsc" to r5900
properties.
* tic6x-opcode-table.h: Fix encoding of BNOP instruction.
* gas/tic6x/insns-c674x-pcrel.s: Add test of BNOP instruction
within header based fetch packet.
* gas/tic6x/insns-c674x-pcrel.d: Update expected disassembly.
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
opcodes/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): For
AARCH64_MOD_LSL, move the range check on the shift amount before the
alignment check; change to call set_sft_amount_out_of_range_error
instead of set_imm_out_of_range_error.
* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
SIMD_IMM_SFT.
gas/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (output_operand_error_record): Change to output
the out-of-range error message as value-expected message if there is
only one single value in the expected range.
(programmer_friendly_fixup): Remove the handling of 8-bit MOVI with
LSL #0 as a programmer-friendly feature.
gas/testsuite/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/movi.s: Add tests.
* gas/aarch64/movi.d: Update.
* gas/aarch64/programmer-friendly.s: Add comment.
