* config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
* config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
"elf/bfin.h".
(GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
(any_gotrel): New rule.
(got): Use it, and create Expr_Node_GOT_Reloc nodes.
* config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
"elf/bfin.h".
(DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
(bfin_pic_ptr): New function.
(md_pseudo_table): Add it for ".picptr".
(OPTION_FDPIC): New macro.
(md_longopts): Add -mfdpic.
(md_parse_option): Handle it.
(md_begin): Set BFD flags.
(md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
(bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
us for GOT relocs.
* Makefile.am (bfin-parse.o): Update dependencies.
(DEPTC_bfin_elf): Likewise.
* Makefile.in: Regenerate.
* cpu-m68k.c (bfd_m68k_compatible): Treat ISA A+ and ISA B code as
incompatible. Likewise MAC and EMAC code.
* elf32-m68k.c (elf32_m68k_merge_private_bfd_data): Use
bfd_get_compatible to set the new bfd architecture. Rely on it
to detect incompatibilities.
gas/
* config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
mcfemac instead of mcfmac.
ld/testsuite/
* ld-m68k/merge-error-1a.s, ld-m68k/merge-error-1b.s,
* ld-m68k/merge-error-1a.d, ld-m68k/merge-error-1b.d,
* ld-m68k/merge-error-1c.d, ld-m68k/merge-error-1d.d,
* ld-m68k/merge-error-1e.d, ld-m68k/merge-ok-1a.d,
* ld-m68k/merge-ok-1b.d: New tests.
* ld-m68k/m68k.exp: Run them.
Daniel Jacobowitz <dan@codesourcery.com>
Phil Edwards <phil@codesourcery.com>
Zack Weinberg <zack@codesourcery.com>
Mark Mitchell <mark@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
bfd/
* bfd-in2.h: Regenerate.
* config.bfd (mips*-*-vxworks*, mips*el-*-vxworks*): New stanzas.
* configure.in (bfd_elf32_bigmips_vxworks_vec): New stanza.
(bfd_elf32_littlemips_vxworks_vec): Likewise.
(bfd_elf32_bigmips_vec): Add elf-vxworks.lo.
(bfd_elf32_littlemips_vec): Likewise.
(bfd_elf32_nbigmips_vec): Likewise.
(bfd_elf32_nlittlemips_vec): Likewise.
(bfd_elf32_ntradbigmips_vec): Likewise.
(bfd_elf32_ntradlittlemips_vec): Likewise.
(bfd_elf32_tradbigmips_vec): Likewise.
(bfd_elf32_tradlittlemips_vec): Likewise.
(bfd_elf64_bigmips_vec): Likewise.
(bfd_elf64_littlemips_vec): Likewise.
(bfd_elf64_tradbigmips_vec): Likewise.
(bfd_elf64_tradlittlemips_vec): Likewise.
* elf32-mips.c: Include elf-vxworks.h.
(mips_info_to_howto_rel): Use elf_backend_mips_rtype_to_howto
instead of calling mips_elf32_rtype_to_howto directly.
(mips_vxworks_copy_howto_rela): New reloc howto.
(mips_vxworks_jump_slot_howto_rela): Likewise.
(mips_vxworks_bfd_reloc_type_lookup): New function.
(mips_vxworks_rtype_to_howto): Likewise.
(mips_vxworks_final_write_processing): Likewise.
(TARGET_LITTLE_SYM, TARGET_LITTLE_NAME): Override for VxWorks.
(TARGET_BIG_SYM, TARGET_BIG_NAME, elf_bed, ELF_MAXPAGESIZE): Likewise.
(elf_backend_want_got_plt): Likewise.
(elf_backend_want_plt_sym): Likewise.
(elf_backend_got_symbol_offset): Likewise.
(elf_backend_want_dynbss): Likewise.
(elf_backend_may_use_rel_p): Likewise.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_got_header_size: Likewise.
(elf_backend_plt_readonly): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Likewise.
(elf_backend_mips_rtype_to_howto): Likewise.
(elf_backend_adjust_dynamic_symbol): Likewise.
(elf_backend_finish_dynamic_symbol): Likewise.
(bfd_elf32_bfd_link_hash_table_create): Likewise.
(elf_backend_add_symbol_hook): Likewise.
(elf_backend_link_output_symbol_hook): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_final_write_processing: Likewise.
(elf_backend_additional_program_headers): Likewise.
(elf_backend_modify_segment_map): Likewise.
(elf_backend_symbol_processing): Likewise.
* elfxx-mips.c: Include elf-vxworks.h.
(mips_elf_link_hash_entry): Add is_relocation_target and
is_branch_target fields.
(mips_elf_link_hash_table): Add is_vxworks, srelbss, sdynbss, srelplt,
srelplt2, sgotplt, splt, plt_header_size and plt_entry_size fields.
(MIPS_ELF_RELA_SIZE, MIPS_ELF_REL_DYN_NAME): New macros.
(MIPS_RESERVED_GOTNO): Take a mips_elf_link_hash_table argument.
Return 3 for VxWorks.
(ELF_MIPS_GP_OFFSET): Change the argument from a bfd to a
mips_elf_link_hash_table. Return 0 for VxWorks.
(MIPS_ELF_GOT_MAX_SIZE): Change the argument from a bfd to a
mips_elf_link_hash_table. Update the call to ELF_MIPS_GP_OFFSET.
(mips_vxworks_exec_plt0_entry): New variable.
(mips_vxworks_exec_plt_entry): Likewise.
(mips_vxworks_shared_plt0_entry): Likewise.
(mips_vxworks_shared_plt_entry): Likewise.
(mips_elf_link_hash_newfunc): Initialize the new hash_entry fields.
(mips_elf_rel_dyn_section): Change the bfd argument to a
mips_elf_link_hash_table. Use MIPS_ELF_REL_DYN_NAME to get
the name of the section.
(mips_elf_initialize_tls_slots): Update the call to
mips_elf_rel_dyn_section.
(mips_elf_gotplt_index): New function.
(mips_elf_local_got_index): Add an input_section argument.
Update the call to mips_elf_create_local_got_entry.
(mips_elf_got_page): Likewise.
(mips_elf_got16_entry): Likewise.
(mips_elf_create_local_got_entry): Add bfd_link_info and input_section
arguments. Create dynamic relocations for each entry on VxWorks.
(mips_elf_merge_gots): Update the use of MIPS_ELF_GOT_MAX_SIZE.
(mips_elf_multi_got): Update the uses of MIPS_ELF_GOT_MAX_SIZE
and MIPS_RESERVED_GOTNO.
(mips_elf_create_got_section): Update the uses of
MIPS_ELF_GOT_MAX_SIZE. Create .got.plt on VxWorks.
(is_gott_symbol): New function.
(mips_elf_calculate_relocation): Use a dynobj local variable.
Update the calls to mips_elf_local_got_index, mips_elf_got16_entry and
mips_elf_got_page_entry. Set G to the .got.plt entry when calculating
VxWorks R_MIPS_CALL* relocations. Calculate and use G for all GOT
relocations on VxWorks. Add dynamic relocations for references
to the VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols. Don't
create dynamic relocations for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64
in VxWorks executables.
(mips_elf_allocate_dynamic_relocations): Add a bfd_link_info argument.
Use MIPS_ELF_RELA_SIZE to calculate the size of a VxWorks entry.
Don't allocate a null entry on VxWorks.
(mips_elf_create_dynamic_relocation): Update the call to
mips_elf_rel_dyn_section. Use absolute rather than relative
relocations for VxWorks, and make them RELA rather than REL.
(_bfd_mips_elf_create_dynamic_sections): Don't make .dynamic
read-only on VxWorks. Update the call to mips_elf_rel_dyn_section.
Create the .plt, .rela.plt, .dynbss and .rela.bss sections on
VxWorks. Likewise create the _PROCEDURE_LINKAGE_TABLE symbol.
Call elf_vxworks_create_dynamic_sections for VxWorks and
initialize the plt_header_size and plt_entry_size fields.
(_bfd_mips_elf_check_relocs): Don't allow GOT relocations to be
used in VxWorks executables. Don't allocate dynamic relocations
for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 in VxWorks executables.
Set is_relocation_target for each symbol referenced by a relocation.
Allocate .rela.dyn entries for relocations against the special
VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols. Create GOT
entries for all VxWorks R_MIPS_GOT16 relocations. Don't allocate
a global GOT entry for symbols mentioned in VxWorks R_MIPS_CALL*,
R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 relocations. Update the calls
to mips_elf_rel_dyn_section and mips_elf_allocate_dynamic_relocations.
Set is_branch_target for symbols mentioned in R_MIPS_PC16 or R_MIPS_26
relocations. Don't set no_fn_stub on VxWorks.
(_bfd_mips_elf_adjust_dynamic_symbol): Update the call to
mips_elf_allocate_dynamic_relocations.
(_bfd_mips_vxworks_adjust_dynamic_symbol): New function.
(_bfd_mips_elf_always_size_sections): Do not allocate GOT page
entries for VxWorks, and do not create multiple GOTs.
(_bfd_mips_elf_size_dynamic_sections): Use MIPS_ELF_REL_DYN_NAME.
Handle .got specially for VxWorks. Update the uses of
MIPS_RESERVED_GOTNO and mips_elf_allocate_dynamic_relocations.
Check for sgotplt and splt. Allocate the .rel(a).dyn contents last,
once its final size is known. Set DF_TEXTREL for VxWorks. Add
DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL, DT_PLTRELSZ and DT_JMPREL
tags on VxWorks. Do not add the MIPS-specific tags for VxWorks.
(_bfd_mips_vxworks_finish_dynamic_symbol): New function.
(mips_vxworks_finish_exec_plt): Likewise.
(mips_vxworks_finish_shared_plt): Likewise.
(_bfd_mips_elf_finish_dynamic_sections): Remove an unncessary call
to mips_elf_rel_dyn_section. Use a VxWorks-specific value of
DT_PLTGOT. Handle DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL,
DT_PLTRELSZ and DT_JMPREL. Update the uses of MIPS_RESERVED_GOTNO
and mips_elf_rel_dyn_section. Use a different GOT header for
VxWorks. Don't sort .rela.dyn on VxWorks. Finish the PLT on VxWorks.
(_bfd_mips_elf_link_hash_table_create): Initialize the new
mips_elf_link_hash_table fields.
(_bfd_mips_vxworks_link_hash_table_create): New function.
(_bfd_mips_elf_final_link): Set the GP value to _GLOBAL_OFFSET_TABLE_
on VxWorks. Update the call to ELF_MIPS_GP_OFFSET.
* elfxx-mips.h (_bfd_mips_vxworks_adjust_dynamic_symbol): Declare.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_vxworks_link_hash_table_create): Likewise.
* libbfd.h: Regenerate.
* Makefile.am (elfxx-mips.lo): Depend on elf-vxworks.h.
(elf32-mips.lo): Likewise.
* Makefile.in: Regenerate.
* reloc.c (BFD_RELOC_MIPS_COPY, BFD_RELOC_MIPS_JUMP_SLOT): Declare.
* targets.c (bfd_elf32_bigmips_vxworks_vec): Declare.
(bfd_elf32_littlemips_vxworks_vec): Likewise.
(_bfd_target_vector): Add entries for them.
gas/
* config/tc-mips.c (mips_target_format): Handle vxworks targets.
(md_begin): Complain about -G being used for PIC. Don't change
the text, data and bss alignments on VxWorks.
(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
generating VxWorks PIC.
(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
(macro): Likewise, but do not treat la $25 specially for
VxWorks PIC, and do not handle jal.
(OPTION_MVXWORKS_PIC): New macro.
(md_longopts): Add -mvxworks-pic.
(md_parse_option): Don't complain about using PIC and -G together here.
Handle OPTION_MVXWORKS_PIC.
(md_estimate_size_before_relax): Always use the first relaxation
sequence on VxWorks.
* config/tc-mips.h (VXWORKS_PIC): New.
gas/testsuite/
* gas/mips/vxworks1.s, gas/mips/vxworks1.d,
* gas/mips/vxworks1-xgot.d: New tests.
* gas/mips/mips.exp: Run them. Do not run other tests on VxWorks.
include/elf/
* mips.h (R_MIPS_COPY, R_MIPS_JUMP_SLOT): New relocs.
ld/
* configure.tgt (mips*el-*-vxworks*, mips*-*-vxworks*): Use
separate VxWorks emulations.
* emulparams/elf32ebmipvxworks.sh: New file.
* emulparams/elf32elmipvxworks.sh: New file.
* Makefile.am (ALL_EMULATIONS): Add eelf32ebmipvxworks.o and
eelf32elmipvxworks.o.
(eelf32ebmipvxworks.c, eelf32elmipvxworks.c): New rules.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-mips/vxworks1.dd, ld-mips/vxworks1.ld, ld-mips/vxworks1-lib.dd,
* ld-mips/vxworks1-lib.nd, ld-mips/vxworks1-lib.rd,
* ld-mips/vxworks1-lib.s, ld-mips/vxworks1.rd, ld-mips/vxworks1.s,
* ld-mips/vxworks1-static.d, ld-mips/vxworks2.s, ld-mips/vxworks2.sd,
* ld-mips/vxworks2-static.sd: New tests.
* ld-mips/mips-elf.exp: Run them.
(xtensa_setup_hw_workarounds): Set this new flag for older hardware.
(get_loop_align_size): New.
(xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
(xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
(get_text_align_power): Rewrite to handle inputs in the range 2-8.
(get_noop_aligned_address): Use get_loop_align_size.
(get_aligned_diff): Likewise.
gas/
* config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
(do_t_branch): Encode branches inside IT blocks as unconditional.
(do_t_cps): New function.
(do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
(opcode_lookup): Allow conditional suffixes on all instructions in
Thumb mode.
(md_assemble): Advance condexec state before checking for errors.
(insns): Use do_t_cps.
gas/testsuite/
* gas/arm/thumb2_bcond.d: New test.
* gas/arm/thumb2_bcond.s: New test.
* gas/arm/thumb2_it_bad.d: New test.
* gas/arm/thumb2_it_bad.l: New test.
* gas/arm/thumb2_it_bad.s: New test.
* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerate.
* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
(elf32_arm_vxworks_bed): Add forward declaration.
(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
(elf32_arm_vxworks_exec_plt0_entry): New table.
(elf32_arm_vxworks_exec_plt_entry): Likewise.
(elf32_arm_vxworks_shared_plt_entry): Likewise.
(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
(reloc_section_p): New function.
(create_got_section): Use RELOC_SECTION.
(elf32_arm_create_dynamic_sections): Likewise. Call
elf_vxworks_create_dynamic_sections for VxWorks targets.
Choose between the two possible values of plt_header_size
and plt_entry_size.
(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
(elf32_arm_abs12_reloc): New function.
(elf32_arm_final_link_relocate): Call it. Allow the creation of
dynamic R_ARM_ABS12 relocs on VxWorks. Use reloc_section_p,
RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION. Initialize the
r_addend fields of relocs. On rela targets, skip any code that
adjusts in-place addends. When using _bfd_link_final_relocate
to perform a final relocation, pass rel->r_addend as the addend
argument.
(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
object, ignore flags that are not standard on VxWorks.
(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
relocs on VxWorks. Use reloc_section_p.
(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
(allocate_dynrelocs): Use RELOC_SIZE. Account for the size of
.rela.plt.unloaded relocs on VxWorks targets.
(elf32_arm_size_dynamic_sections): Use RELOC_SIZE. Check for
.rela.plt.unloaded as well as .rel(a).plt. Add DT_RELA* tags
instead of DT_REL* tags on RELA targets.
(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle VxWorks
PLT entries. Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle DT_RELASZ
like DT_RELSZ. Handle the VxWorks form of initial PLT entry.
Correct the .rela.plt.unreloaded symbol indexes.
(elf32_arm_output_symbol_hook): Call the VxWorks version of this
hook on VxWorks targets.
(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
Minor formatting tweak.
(elf32_arm_vxworks_final_write_processing): New function.
(elf_backend_add_symbol_hook): Override for VxWorks and reset
for Symbian.
(elf_backend_final_write_processing): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_want_plt_sym): Likewise.
(ELF_MAXPAGESIZE): Likewise.
(elf_backend_may_use_rel_p): Minor formatting tweak.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_rela_normal): Likewise.
* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.
gas/
* config/tc-arm.c (md_apply_fix): Install a value of zero into a
BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
R_ARM_ABS12 reloc.
(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
gas/testsuite/
* gas/arm/abs12.s, gas/arm/abs12.d: New test.
* gas/arm/pic.d: Skip for *-*-vxworks*...
* gas/arm/pic_vxworks.d: ...use this version instead.
* gas/arm/unwind_vxworks.d: Fix expected output.
ld/
* emulparams/armelf_vxworks.sh: Include vxworks.sh.
(MAXPAGESIZE): Define.
* emulparams/vxworks.sh: Undefine.
* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
* ld-arm/vxworks2-static.sd: New tests.
* ld-arm/arm-elf.exp: Run them.
2006-02-28 Jan Beulich <jbeulich@novell.com>
PR/1070
* macro.c (getstring): Don't treat parentheses special anymore.
(get_any_string): Don't consider '(' and ')' as quoting anymore.
Special-case '(', ')', '[', and ']' when dealing with non-quoting
characters.
gas/testsuite/
2006-02-28 Jan Beulich <jbeulich@novell.com>
* gas/macros/paren[sd]: New.
* gas/macros/macros.exp: Run new test.
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (output_insn): Support Intel Merom New
Instructions.
* gas/config/tc-i386.h (CpuMNI): New.
(CpuUnknownFlags): Add CpuMNI.
gas/testsuite/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add merom and x86-64-merom.
* gas/i386/merom.d: New file.
* gas/i386/merom.s: Likewise.
* gas/i386/x86-64-merom.d: Likewise.
* gas/i386/x86-64-merom.s: Likewise.
include/opcode/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Support Intel Merom New Instructions.
opcodes/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
Intel Merom New Instructions.
(THREE_BYTE_0): Likewise.
(THREE_BYTE_1): Likewise.
(three_byte_table): Likewise.
(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
THREE_BYTE_1 for entry 0x3a.
(twobyte_has_modrm): Updated.
(twobyte_uses_SSE_prefix): Likewise.
(print_insn): Handle 3-byte opcodes used by Intel Merom New
Instructions.
* config/tc-sparc.c (priv_reg_table): Add entry for "gl".
(hpriv_reg_table): New table for hyperprivileged registers.
(sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
register encoding.
* config.bfd (mips*el-*-netbsd*, mips*-*-netbsd*): Use
traditional MIPS ELF targets.
gas:
* configure.tgt: set emulation for mips-*-netbsd*
ld:
* configure.tgt (mips*el-*-netbsd*, mips*-*-netbsd*):
Use the traditional target.
from 1, not 0, in error messages.
(md_assemble): Simplify special-case check for ENTRY instructions.
(tinsn_has_invalid_symbolic_operands): Do not include opcode and
operand in error message.
fields.
* config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
* config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
subtracted symbols.
(relaxation_requirements): Add pfinish_frag argument and use it to
replace setting tinsn->record_fix fields.
(xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
and vinsn_to_insnbuf. Remove references to record_fix and
slot_sub_symbols fields.
(xtensa_mark_narrow_branches): Delete unused code.
(is_narrow_branch_guaranteed_in_range): Handle expr that is not just
a symbol.
(convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
record_fix fields.
(tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
(vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
of the record_fix field. Simplify error messages for unexpected
symbolic operands.
(set_expr_symbol_offset_diff): Delete.
* config/tc-avr.c (mod_index): New union to allow conversion
between pointers and integers.
(md_begin, avr_ldi_expression): Use it.
* config/tc-i370.c (md_assemble): Add cast for argument to print
statement.
* config/tc-tic54x.c (subsym_substitute): Likewise.
* config/tc-mn10200.c (md_assemble): Use a union to convert the
opindex field of fr_cgen structure into a pointer so that it can
be stored in a frag.
* config/tc-mn10300.c (md_assemble): Likewise.
* config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
types.
* config/tc-v850.c: Replace uses of (int) casts with correct
types.
* gas/tic54x/address.d: Work with 64bit hosts.
* gas/tic54x/addrfar.d: Likewise.
* gas/tic54x/align.d: Likewise.
* gas/tic54x/all-opcodes.d: Likewise.
* gas/tic54x/asg.d: Likewise.
* gas/tic54x/cons.d: Likewise.
* gas/tic54x/consfar.d: Likewise.
* gas/tic54x/extaddr.d: Likewise.
* gas/tic54x/field.d: Likewise.
* gas/tic54x/labels.d: Likewise.
* gas/tic54x/loop.d: Likewise.
* gas/tic54x/lp.d: Likewise.
* gas/tic54x/macro.d: Likewise.
* gas/tic54x/math.d: Likewise.
* gas/tic54x/opcodes.d: Likewise.
* gas/tic54x/sections.d: Likewise.
* gas/tic54x/set.d: Likewise.
* gas/tic54x/struct.d: Likewise.
* gas/tic54x/subsym.d: Likewise.
* xtensa-config.h (XCHAL_HAVE_WIDE_BRANCHES): New.
gas:
* config/tc-xtensa.c (op_placement_info_struct): Delete single,
single_size, widest, and widest_size fields. Add narrowest_slot.
(xg_emit_insn_to_buf): Remove fmt parameter and compute it here.
Use xg_get_single_slot to find the slot.
(finish_vinsn): Use emit_single_op instead of bundle_single_op.
(bundle_single_op): Rename this to....
(bundle_tinsn): ...this function, which builds a vliw_insn but does
not call finish_vinsn.
(emit_single_op): Use bundle_tinsn instead of bundle_single_op.
(relax_frag_immed): Get num_slots from cur_vinsn.
(convert_frag_narrow): Update call to xg_emit_insn_to_buf.
(convert_frag_immed): Likewise. Also, get num_slots from cur_vinsn.
(init_op_placement_info_table): Set narrowest_slot field. Remove
code for deleted fields.
(xg_get_single_size): Return narrowest_size field, not single_size.
(xg_get_single_format): Return narrowest field, not single.
(xg_get_single_slot): New.
(tinsn_to_insnbuf): Rewrite to use tinsn_to_slotbuf.
* config/xtensa-relax.c (widen_spec_list): Add wide branch relaxations.
(transition_applies): Check wide branch option availability.
2005-12-22 Jan Beulich <jbeulich@novell.com>
* symbols.h (snapshot_symbol): First parameter is now pointer
to pointer to symbolS.
* symbols.c (snapshot_symbol): Likewise. Store resulting symbol
there. Use symbol_equated_p.
* expr.c (resolve_expression): Change first argument to
snapshot_symbol. Track possibly changed add_symbol consistently
across function. Resolve more special cases with known result.
Also update final_val when replacing add_symbol.
gas/testsuite/
2005-12-22 Jan Beulich <jbeulich@novell.com>
* gas/all/cond.s: Also check .if works on equates to undefined
when the expression value can be known without knowing the
value of the symbol.
* gas/all/cond.l: Adjust.
* gas/i386/equ.s: Also check .if works on (equates to)
registers when the expression value can be known without
knowing the value of the register.
* gas/i386/equ.e: Adjust.
is_aligning_branch flag.
(find_address_of_next_align_frag): Limit by xtensa_fetch_width.
(future_alignment_required): Except for frags with is_aligning_branch
flag set, call frag_wane for frags that do not need to be reexamined
for aligning.
(relax_frag_immed): Replace orig_vinsn with cur_vinsn to fix a leak.
(convert_frag_immed): Likewise.
(convert_frag_narrow): Check is_aligning_branch flag.
* config/tc-xtensa.h (xtensa_frag_type): Add is_aligning_branch flag.
(xg_init_vinsn): Remove redundant initialization.
(xg_clear_vinsn): Zero all the slots with a single memset.
* config/xtensa-istack.h (vliw_insn): Move insnbuf field after slots.
2005-12-14 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (add_prefix): More fine-grained handling of
REX prefixes. Or new prefix value into i.prefix instead of
assigning.
gas/testsuite/
2005-12-14 Jan Beulich <jbeulich@novell.com>
* gas/i386/rex.[sd]: New.
* gas/i386/i386.exp: Run new test.
* config/tc-hppa.c (hppa_fix_adjustable): Don't reject for reduction
R_HPPA relocations that are 32-bits wide.
* gas/all/redef2.d: Allow "$DATA$" as well as ".data" in matches.
* gas/all/weakref1.d: Allow "$CODE$" as well as ".text" in matches.
* gas/hppa/reloc/reloc.exp: Adjust regexp for new output.
2005-11-17 Jan Beulich <jbeulich@novell.com>
* symbols.h (S_CLEAR_VOLATILE): Declare.
* symbols.c (colon): Also accept redefinable symbols for
redefinition. Clone them before modifying.
(S_CLEAR_VOLATILE): Define.
* cond.c (s_ifdef): Also test for equated symbols.
* read.c (s_comm_internal): Also exclude non-redefinable
equated symbols. Clone redefinable ones before modifying.
(s_weakref): Clone redefinable symbols before modifying.
* doc/internals.texi: Document sy_volatile, sy_forward_ref,
S_IS_VOLATILE, S_SET_VOLATILE, S_CLEAR_VOLATILE,
S_IS_FORWARD_REF, and S_SET_FORWARD_REF.
gas/testsuite/
2005-11-17 Jan Beulich <jbeulich@novell.com>
* gas/all/cond.s: Also check ifdef works on equates and
commons.
* gas/all/cond.l: Adjust.
* gas/all/redef2.s: Also test redefining equate to label.
* gas/all/redef2.d: Adjust.
* gas/all/redef3.[sd]: New.
* gas/all/redef4.s: New.
* gas/all/redef5.s: New.
* gas/elf/redef.s: New, copied from original gas/all/redef2.s.
* gas/elf/redef.d: Remove #source.
* gas/all/gas.exp: Remove exclusion of iq2000-*-* from and
adjust xfails for redefinition tests. Run new tests. Exclude
alpha*-*-*, mips*-*-*, *c54x*-*-* from weakref tests.
* config/tc-arm.c (s_arm_unwind_save_core): Don't emit an extra
opcode if r4-r15 are not saved.
gas/testsuite/
* gas/arm/unwind.s, gas/arm/unwind.d, gas/arm/unwind_vxworks.d: Add
a test for saving only the low registers.
2005-11-14 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (md): Rename regsym to indregsym and move
it to the end of the structure.
(ar): Field regnum is unsigned.
(cr): Likewise:
(indirect_reg): Likewise.
(declare_register_set): Parameter regnum is unsigned.
(declare_register): Parameter numregs and base_regnum are
unsigned. So is the local loop variable.
(md_begin): Restrict scope of local variable regnum, which
also is unsigned. Replace loops with function calls where
possible. Re-order things so that register groups are kept
together. Remove all uses of regsym except for indirect
registers. Replace use of regsym by indregsym for indirect
registers.
(ia64_optimize_expr): Replace use of regsym by indregsym for
indirect registers, with appropriate bias.
instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
save/restore encoding of the args field.
* mips16-opc.c: Add MIPS16e save/restore opcodes.
* mips-dis.c (print_mips16_insn_arg): Handle printing of 'm'/'M'
codes for save/restore.
* config/tc-mips.c (mips16_ip): Add handling of 'm' and 'M' codes
for the MIPS16e save/restore instructions.
* gas/mips/mips.exp: Run new save/restore tests.
* gas/testsuite/gas/mips/mips16e-save.s: New test for generating
different styles of save/restore instructions.
* gas/testsuite/gas/mips/mips16e-save.d: New.
(arm_reg_parse_multi): Return NULL rather than FAIL.
(arm_reg_parse): Fix comment, the function returns FAIL rather than NULL if
it is unable to parse the register name.
(do_ldrex): Use BAD_ADDR_MODE.
Change error message for PC-relative addressing.
(do_strex): Likewise.
(do_t_ldrex): Use BAD_ADDR_MODE.
(do_t_strex): Likewise.
* gas/arm/archv6t2-bad.s: Add tests of badly composed ldrex and strex
instructions.
* gas/arm/archv6t2-bad.l: Add expected error messages.
* gas/arm/r15-bad.l: Adjust error messages for r15 usage in ldrex and strex
instructions.
* config/obj-coff.c (obj_coff_section): Set readonly flag with the 'x'
attribute. Remember the actions of the 'w' and 'n' attributes and do not
allow the 'x','s' or 'd' attributes to change them.
Contribute the following change:
2005-09-19 Dave Brolley <brolley@redhat.com>
* config/tc-m32c.c (default_isa): New static variable.
(m32c_isa): Now of type CGEN_BITSET.
(md_begin): Pass &m32c_isa to m32c_cgen_cpu_open.
* elf32-bfin.c (bfd_bfin_elf32_create_embedded_relocs): Fix signedness
warning.
gas/
* Makefile.am (bfin-parse.h): Renamed from bfin-parse.tab.h.
(EXTRA_DIST): Add bfin-parse.h and bfin-lex.c.
* Makefile.in: Regenerate.
* config/bfin-lex.l: Include bfin-parse.h instead of bfin-parse.tab.h.
* config/tc-bfin.c (md_chars_to_number): Change the type of first
argument from unsigned char * to char * to remove signedness warnings.
2005-10-24 Jan Beulich <jbeulich@novell.com>
* ia64.h (enum ia64_opnd): Move memory operand out of set of
indirect operands.
bfd/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* cpu-ia64-opc.c (elf64_ia64_operands): Move memory operand out of
set of indirect operands.
gas/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (enum reg_symbol): Delete IND_MEM.
(dot_rot): Change type of num_* variables. Check for positive count.
(ia64_optimize_expr): Re-structure.
(md_operand): Check for general register.
gas/testsuite/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* gas/ia64/index.[sl]: New.
* gas/ia64/rotX.[sl]: New.
* gas/ia64/ia64.exp: Run new tests.
opcodes/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* ia64-asmtab.c: Regenerate.
2005-10-24 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (declare_register): Call symbol_create.
(md_begin): Remove local variables total, ar_base, and cr_base.
Start loops for registers at their respective first one. Don't
update md.regsym for alias names. Generate alias name tp for r13.
gas/testsuite/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* gas/ia64/regs.pl: Also check tp alias of r13.
* gas/ia64/regs.s: Regenerate.
* gas/ia64/regs.d: Adjust.
into jrc/jalrc versions if ISA_MIPS32+ and not doing the swap,
hence avoiding to emit a nop.
* gas/mips/mips.exp: Run new test.
* gas/testsuite/gas/mips/mips16e-jrc.s: New test for converting
jalr/jr to the compact jalrc/jrc instructions.
* gas/testsuite/gas/mips/mips16e-jrc.d: New.
LEX_BEGIN_NAME.
(bfin_start_line_hook): Remove the workaround for LSETUP(.
(bfin_name_is_register): Remove the workarounds for LSETUP(
and SAA(.
(bfin_start_label): Ditto.
unsigned line number. Do not include "dwarf2dbg.h".
* config/tc-xtensa.c (md_pseudo_table): Remove entry for "loc".
(xtensa_dwarf2_directive_loc, xtensa_dwarf2_emit_insn): Delete.
(xg_build_to_insn, xg_build_token_insn): Update TInsn uses.
(md_assemble): Use as_where instead of dwarf2_where.
(xg_assemble_vliw_tokens): Use unsigned line numbers instead of
dwarf2_line_infos. Change to call new_logical_line followed by
dwarf2_emit_insn.
- allowing true forward references (which will always assume the referenced
symbols have at the point of use) through the new .eqv pseudo-op and the
new == operator
- disallowing changing .equiv-generated equates (so that the protection this
provides is both forward and backward)
- snapshotting equates when their value gets changed so that previous uses
don't get affected by the new value.
- allowing expressions in places where absolute expressions (or register
names) are needed which were not completely resolvable at the point of
their definition but which are fully resolvable at the point of use
In addition it fixes PR/288.
(pa_ip): Promote from PA 1.0 to 1.1 immediately when 1.1 match is
found. Simplify handling of "ma" and "mb" completers.
* hppa.h (FLAG_STRICT): Revise comment.
(pa_opcode): Revise ordering rules. Add/move strict pa10 variants
before corresponding pa11 opcodes. Add strict pa10 register-immediate
entries for "fdc".
(parse_reg_without_prefix): New function.
(parse_reg): Check for '$' register prefix if --allow-reg-prefix is set.
(option md_longopts): Add allow-reg-prefix option.
* doc/c-sh.texi: Document --allow-reg-prefix option.
* NEWS: Mention the new switch.
* gas/sh/basic.exp: Run reg-prefix test.
* gas/sh/reg-prefix.s: New
* gas/sh/reg-prefix.d: New
2005-09-29 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): Always parse first operand of
alloc.
gas/testsuite/
2005-09-29 Jan Beulich <jbeulich@novell.com>
* gas/ia64/alloc.[sl]: New.
* gas/ia64/ia64.exp: Run new test.
2005-09-28 Jan Beulich <jbeulich@novell.com>
* dw2gencfi.c (dot_cfi): Call ignore_rest_of_line when not fully
parsing the input.
(dot_cfi_startproc): Likewise.
(dot_cfi_endproc): Likewise. Also check no extra input was given.
(dot_cfi_escape): Likewise.
2005-09-14 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (tc_x86_regname_to_dw2regnum): Add selector
registers, floating point control and status words, and mxcsr as
well as (for 64-bit code) segment base registers and rflags.
* config/tc-msp430.c (msp430_operands): Undo last changes. Instead...
(msp430_relax_frag): add a guard check to ensure that final fr_subtype
has been reached.
(dwarf2_set_isa): New.
(dwarf2_directive_loc): Rearrange to allow all options on one line.
* dwarf2dbg.h (dwarf2_set_isa): Declare.
* doc/as.texinfo: Update .loc documentation.
* gas/lns/lns-common-1.d: Don't match header or special opcode numbers.
* gas/lns/lns-common-1.s: Update for syntax change.
* gas/lns/lns-diag-1.[sl]: Likewise.
(mips_opts): Add -1 to initialize ase_mt.
(file_ase_mt): New variable for -mmt.
(CPU_HAS_MT): New define.
(validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
formats.
(mips_ip): Check ase_mt to enable MT instructions.
Handle !, $, *, &, +T, +t, g operand formats.
For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
odd float registers.
(OPTION_MT, OPTION_NO_MT): New define.
(OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
(md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
(mips_after_parse_args): Set ase_mt based on CPU.
(s_mipsset): Handle ".set mt" and ".set nomt".
(mips_elf_final_processing): Remind of adding new flag for MT ASE.
(md_show_usage): Show usage of -mmt and -mno-mt.
* doc/as.texinfo: Document -mmt and -mno-mt options.
* doc/c-mips.texi: Likewise, and document ".set mt" and ".set nomt"
directives.
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
when the frags are different for the 2 instructions we want to
swap. If the lengths of the 2 instructions are not the same, we
won't do the swap but emit an nop.
2005-08-26 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (intel_e09): Set JumpAbsolute when seeing a PTR-
qualified operand of a branch.
(intel_bracket_expr): Set JumpAbsolute here...
(intel_e11): ... rather than here.
gas/testsuite/
2005-08-26 Jan Beulich <jbeulich@novell.com>
* gas/i386/intel.s: Adjust.
* gas/i386/intelok.s: Add two more insns.
* gas/i386/intelok.d: Adjust.
(mips_opts): Add -1 to initialize ase_dsp.
(file_ase_dsp): New variable for -mdsp.
(CPU_HAS_DSP): New define.
(validate_mips_insn): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, ', :, @
operand formats.
(mips_ip): Add min_range and max_range for checking singed numbers.
Check ase_dsp to enable DSP instructions.
Handle 3, 4, 5, 6, 7, 8, 9, 0, ', :, @ operand formats.
(OPTION_DSP, OPTION_NO_DSP): New define.
(OPTION_COMPAT_ARCH_BASE): Change because of inserting DSP define.
(md_parse_option): Parse OPTION_DSP and OPTION_NO_DSP.
(mips_after_parse_args): Set ase_dsp based on CPU.
(s_mipsset): Handle ".set dsp" and ".set nodsp".
(mips_elf_final_processing): Remind of adding new flag for DSP ASE.
(md_show_usage): Show usage of -mdsp and -mno-dsp.
2005-08-22 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (object_64bit): New.
(i386_target_format): Initialize it.
(output_disp): Use object_64bit for relocation type determination.
(output_imm): Likewise.
(i386_validate_fix): Likewise.
(tc_gen_reloc): Likewise.
(lex_got): Likewise. Remove static mode_name. Change array size
of gotrel's rel field, and adjust its initializer. Adjust diagnostic.
(x86_cons): Use object_64bit for deciding whether quad fields can
have relocations.
gas/testsuite/
2005-08-22 Jan Beulich <jbeulich@novell.com>
* gas/i386/mixed-mode-reloc.s, gas/i386/mixed-mode-reloc32.d,
gas/i386/mixed-mode-reloc64.d: New.
* gas/i386/i386.exp: Run new tests.
* config/tc-msp430.c (msp430_enable_relax): New flag.
(msp430_enable_polys): Likewise.
(OPTION_RELAX): New option.
(OPTION_POLYMORPHS): Likewise.
(md_longopts): New long options.
(md_show_usage): Updated.
(md_parse_option): Add new options handler.
(msp430_operands): Add check if polymorph insns are enabled.
(msp430_force_relocation_local): New function.
(md_apply_fix): Now delete relocs according to new flags combination.
(msp430_relax_frag): Convert long branches to short branches only if
flag msp430_enable_relax is set.
* config/tc-msp430.h (TC_FORCE_RELOCATION_LOCAL): Defined.
(msp430_force_relocation_local): Likewise.
* doc/c-msp430.texi: Describe new options.
* macro.c (getstring): Do not treat round parentheses exactly the same as angle
brackets - the parentheses need to be preserved and passed on to the macro processing code.
gas/
* config/tc-arm.c (current_it_mask, current_cc): New variables.
(do_t_add_sub): Use correct encodings inside IT block.
(do_t_arit3c): Ditto.
(do_t_it): Simplify logic. Set current_it_mask and current_cc.
(md_assemble): Verify conditional suffixes agains IT blocks.
gas/testsuite/
* gas/arm/thumb32.s: Use correct conditional suffixes inside IT
blocks.
* gas/arm/thumb2_it.d, gas/arm/thumb2_it.s: New test.
instruction.
gas/arm/iwmmxt-bad2.s: New file: Check for error messages about erroneous
offsets in iwmmxt instructions. Cannot be part of iwmmxt-bad.s because
the errors there stop the assembler before it gets to check the offsets
in instructions.
gas/arm/iwmmxt-bad2.d: New file.
gas/arm/iwmmxt-bad2.l: New file: Expected error messages.
gas/arm/iwmmxt.s: Change the offset values of the WLDRD, WSTRD and WSTRW
instructions to be larger than +/-255.
gas/arm/iwmmxt.d: Fix the expected results for these instructions.
2005-07-26 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (optimize_imm): Calculate candidate immediates
mask from guessed suffix, but mask out other immediate types only
if at least on candidate is valid for the insn.
gas/testsuite/
2005-07-26 Jan Beulich <jbeulich@novell.com>
* gas/i386/immed32.[sd]: New.
* gas/i386/immed64.[sd]: New.
* gas/i386/i386.exp: Run new tests.
2005-07-18 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (md_begin): Use IS_ELF.
(tc_i386_fix_adjustable): Likewise.
(md_estimate_size_before_relax): Likewise.
(md_apply_fix): Likewise.
(i386_target_format): Likewise.
(lex_got): Define to NULL when not ELF or when LEX_AT. Check IS_ELF.
(i386_immediate): Remove #ifdef LEX_AT.
(i386_displacement): Likewise.
* config/tc-i386.h (x86_cons): Prototype only when ELF and when not
LEX_AT.
2005-07-18 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (reloc): Convert to ISO C90. Change first
parameter to unsigned. Parameter sign now is tristate - zero/
positive mean unsigned/signed, negative means signedness doesn't
matter. Check field size,
signedness, and pcrel-ness are in agreement between relocated field
and relocation type. Adjust diagnostics.
(optimize_imm): And type mask of operand instead of overwriting it.
(lex_got): Convert to ISO C90. Add third parameter. Add new field to
local structure and initialize gotrel accordingly. Pass caller as
mask of types that the operator can match.
(x86_cons_fix_new): Let reloc know that signedness of relocation
doesn't matter.
(x86_pe_cons_fix_new): Likewise.
(x86_cons): Pass additional argument to lex_got.
(i386_immediate): New local variable 'types'. Pass its address as
additional argument to lex_got. Mask out operand types not supported
befoe returning.
(i386_displacement): Likewise. Set bigdisp to all types supported in
64-bit mode, combining the previously split initialization.
gas/testsuite/
2005-07-18 Jan Beulich <jbeulich@novell.com>
* gas/i386/reloc32.[sdl]: New.
* gas/i386/reloc64.[sdl]: New.
* gas/i386/i386.exp: Run new tests.
2005-07-14 Jim Blandy <jimb@redhat.com>
* configure.in: Add cases for Renesas m32c.
* configure: Regenerated.
bfd/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for m32c-*-elf (Renesas m32c and m16c).
* Makefile.am (ALL_MACHINES): Add cpu-m32c.lo.
(ALL_MACHINES_CFILES): Add cpu-m32c.c.
(BFD32_BACKENDS): Add elf32-m32c.lo.
(BFD32_BACKENDS_CFILES): Add elf32-m32c.c.
(cpu-m32c.lo, elf32-m32c.lo): New rules, generated by 'make dep-am'.
* Makefile.in: Regenerated.
* archures.c (bfd_arch_m32c, bfd_mach_m16c, bfd_mach_m32c): New
arch and mach codes.
(bfd_m32c_arch): New arch info object.
(bfd_archures_list): List bfd_m32c_arch.
* bfd-in2.h: Regenerated.
* config.bfd: Add case for the m32c.
* configure.in: Add case for the m32c.
* configure: Regenerated.
* cpu-m32c.c, elf32-m32c.c: New files.
* libbfd.h: Regenerated.
* targets.c (bfd_elf32_m32c_vec): Declare.
(_bfd_target_vector): List bfd_elf32_m32c_vec.
binutils/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* readelf.c: #include "elf/m32c.h"
(guess_is_rela, dump_relocations, get_machine_name): Add cases for
EM_M32C.
* Makefile.am (readelf.o): Update dependencies.
* Makefile.in: Regenerated.
cpu/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
gas/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C.
* Makefile.am (CPU_TYPES): List m32c.
(TARGET_CPU_CFILES): List config/tc-m32c.c.
(TARGET_CPU_HFILES): List config/tc-m32c.h.
* configure.in: Add case for m32c.
* configure.tgt: Add cases for m32c and m32c-*-elf.
* configure: Regenerated.
* config/tc-m32c.c, config/tc-m32c.h: New files.
* doc/Makefile.am (CPU_DOCS): Add c-m32c.texi.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set M32C.
* doc/as.texinfo: Add text for the M32C-specific options and line
comment characters, and refer to c-m32c.texi.
* doc/c-m32c.texi: New file.
include/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* dis-asm.h (print_insn_m32c): New declaration.
include/elf/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for Renesas M32C and M16C.
* common.h (EM_M32C): New machine number.
* m32c.h: New file.
ld/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* Makefile.am (ALL_EMULATIONS): Add eelf32m32c.o.
(eelf32m32c.c): New target.
* Makefile.in: Regenerated.
* configure.tgt: Add case for m32c-*-elf.
* emulparams/elf32m32c.sh: New file.
opcodes/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
* m32c-desc.h, m32c-opc.h: New.
* Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
(CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
m32c-opc.c.
(ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
m32c-ibld.lo, m32c-opc.lo.
(CLEANFILES): List stamp-m32c.
(M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
(CGEN_CPUS): Add m32c.
(m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
(m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
(m32c_opc_h): New variable.
(stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
(m32c-opc.lo): New rules.
* Makefile.in: Regenerated.
* configure.in: Add case for bfd_m32c_arch.
* configure: Regenerated.
* disassemble.c (ARCH_m32c): New.
[ARCH_m32c]: #include "m32c-desc.h".
(disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
(disassemble_init_for_target) [ARCH_m32c]: Same.
* cgen-ops.h, cgen-types.h: New files.
* Makefile.am (HFILES): List them.
* Makefile.in: Regenerated.
