2005-07-06 H.J. Lu <hongjiu.lu@intel.com>

* config/tc-i386.c (cpu_arch): Add sse3.

	* config/tc-i386.h (CpuSSE3): Renamed from ...
	(CpuPNI): This. Defined as CpuSSE3.

	* doc/c-i386.texi: Document .sse3.
This commit is contained in:
H.J. Lu 2005-07-06 19:11:01 +00:00
parent 3cb3b8dfd1
commit bf50992e53
4 changed files with 13 additions and 2 deletions

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@ -1,3 +1,12 @@
2005-07-06 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add sse3.
* config/tc-i386.h (CpuSSE3): Renamed from ...
(CpuPNI): This. Defined as CpuSSE3.
* doc/c-i386.texi: Document .sse3.
2005-07-06 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (nop): Use zero for L-unit pseudo-nop.

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@ -433,6 +433,7 @@ static const arch_entry cpu_arch[] = {
{".mmx", CpuMMX },
{".sse", CpuMMX|CpuMMX2|CpuSSE },
{".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
{".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
{".3dnow", CpuMMX|Cpu3dnow },
{".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
{".padlock", CpuPadLock },

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@ -182,7 +182,8 @@ typedef struct
#define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */
#define Cpu3dnow 0x8000 /* 3dnow! support required */
#define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */
#define CpuPNI 0x20000 /* Prescott New Instructions required */
#define CpuSSE3 0x20000 /* Streaming SIMD extensions 3 required */
#define CpuPNI CpuSSE3 /* Prescott New Instructions required */
#define CpuPadLock 0x40000 /* VIA PadLock required */
#define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */

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@ -701,7 +701,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
@item @samp{k6} @tab @samp{athlon} @samp{sledgehammer}
@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.3dnow}
@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.sse3} @samp{.3dnow}
@end multitable
Apart from the warning, there are only two other effects on