Commit graph

2257 commits

Author SHA1 Message Date
Jiong Wang
d8282f0eb1 [ARM] Skip private symbol when doing objdump
2015-03-03  Jiong Wang  <jiong.wang@arm.com>

  opcode/
    * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

  binutils/testsuite/
    * binutils-all/arm/rvct_symbol.s: New testcase.
    * binutils-all/arm/objdump.exp: Run it.
2015-03-03 15:00:59 +00:00
Oleg Endo
ac99436572 [SH] Fix clrs, sets, pref insn arch memberships.
opcodes/
	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	arch_sh_up.
	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.

gas/testsuite/
	* gas/sh/arch/arch.exp: Replace dead code to generate expected .s files
	with ...
	* gas/sh/arch/sh-opc-gen-as.pl: ... this new script.
	* gas/sh/arch/arch_expected.txt: Regenerate.
	* gas/sh/arch/sh-dsp.s: Likewise.
	* gas/sh/arch/sh-opc-gen-as.pl: Likewise.
	* gas/sh/arch/sh.s: Likewise.
	* gas/sh/arch/sh2.s: Likewise.
	* gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Likewise.
	* gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Likewise.
	* gas/sh/arch/sh2a-nofpu.s: Likewise.
	* gas/sh/arch/sh2a-or-sh3e.s: Likewise.
	* gas/sh/arch/sh2a-or-sh4.s: Likewise.
	* gas/sh/arch/sh2a.s: Likewise.
	* gas/sh/arch/sh2e.s: Likewise.
	* gas/sh/arch/sh3-dsp.s: Likewise.
	* gas/sh/arch/sh3-nommu.s: Likewise.
	* gas/sh/arch/sh3.s: Likewise.
	* gas/sh/arch/sh3e.s: Likewise.
	* gas/sh/arch/sh4-nofpu.s: Likewise.
	* gas/sh/arch/sh4-nommu-nofpu.s: Likewise.
	* gas/sh/arch/sh4.s: Likewise.
	* gas/sh/arch/sh4a-nofpu.s: Likewise.
	* gas/sh/arch/sh4a.s: Likewise.
	* gas/sh/arch/sh4al-dsp.s: Likewise.

ld/testsuite/
	* ld-sh/arch/arch_expected.txt: Regenerate.
	* ld-sh/arch/sh-dsp.s: Likewise.
	* ld-sh/arch/sh.s: Likewise.
	* ld-sh/arch/sh2.s: Likewise.
	* ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s: Likewise.
	* ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Likewise.
	* ld-sh/arch/sh2a-nofpu.s: Likewise.
	* ld-sh/arch/sh2a-or-sh3e.s: Likewise.
	* ld-sh/arch/sh2a-or-sh4.s: Likewise.
	* ld-sh/arch/sh2a.s: Likewise.
	* ld-sh/arch/sh2e.s: Likewise.
	* ld-sh/arch/sh3-dsp.s: Likewise.
	* ld-sh/arch/sh3-nommu.s: Likewise.
	* ld-sh/arch/sh3.s: Likewise.
	* ld-sh/arch/sh3e.s: Likewise.
	* ld-sh/arch/sh4-nofpu.s: Likewise.
	* ld-sh/arch/sh4-nommu-nofpu.s: Likewise.
	* ld-sh/arch/sh4.s: Likewise.
	* ld-sh/arch/sh4a-nofpu.s: Likewise.
	* ld-sh/arch/sh4a.s: Likewise.
	* ld-sh/arch/sh4al-dsp.s: Likewise.
2015-02-25 21:26:59 +01:00
Vinay
fd63f640f6 Adds a space between the operands of the RL78's MOV instruction for consistency with the disassembling of other instructions.
* rl78-decode.opc (MOV): Added space between two operands for
	'mov' instruction in index addressing mode.
	* rl78-decode.c: Regenerate.
2015-02-23 17:16:30 +00:00
Pedro Alves
f63c17760f Wrap a few opcodes headers in extern "C" for C++
These are sufficient to link an --enable-targets=all GDB build in C++
mode, on x86_64 Fedora 20.

include/opcode/
2015-02-19  Pedro Alves  <palves@redhat.com>

	* cgen.h [__cplusplus]: Wrap in extern "C".
	* msp430-decode.h [__cplusplus]: Likewise.
	* nios2.h [__cplusplus]: Likewise.
	* rl78.h [__cplusplus]: Likewise.
	* rx.h [__cplusplus]: Likewise.
	* tilegx.h [__cplusplus]: Likewise.

opcodes/
2015-02-19  Pedro Alves  <palves@redhat.com>

	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
2015-02-19 22:45:47 +00:00
Pedro Alves
07774fccc3 opcodes/microblaze: Rename 'or', 'and', 'xor' to avoid C++ conflict
Building GDB as a C++ program, we see:

  In file included from gdb/microblaze-tdep.c:37:0:
  gdb/../opcodes/../opcodes/microblaze-opcm.h: At global scope:
  gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected identifier before ‘or’ token
     ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
						     ^
  gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected ‘}’ before ‘or’ token
  gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected unqualified-id before ‘or’ token
  gdb/../opcodes/../opcodes/microblaze-opcm.h:60:1: error: expected declaration before ‘}’ token
   };
   ^

opcodes/ChangeLog:
2015-02-10  Pedro Alves  <palves@redhat.com>
	    Tom Tromey  <tromey@redhat.com>

	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	microblaze_and, microblaze_xor.
	* microblaze-opc.h (opcodes): Adjust.
2015-02-10 18:09:39 +00:00
Alan Modra
3f8107ab38 FT32 initial support
FT32 is a new 32-bit RISC core developed by FTDI for embedded applications.

	* configure.ac: Add FT32 support.
	* configure: Regenerate.
bfd/
	* Makefile.am: Add FT32 files.
	* archures.c (enum bfd_architecture): Add bfd_arch_ft32.
	(bfd_mach_ft32): Define.
	(bfd_ft32_arch): Declare.
	(bfd_archures_list): Add bfd_ft32_arch.
	* config.bfd: Handle FT32.
	* configure.ac: Likewise.
	* cpu-ft32.c: New file.
	* elf32-ft32.c: New file.
	* reloc.c (BFD_RELOC_FT32_10, BFD_RELOC_FT32_20, BFD_RELOC_FT32_17,
	BFD_RELOC_FT32_18): Define.
	* targets.c (_bfd_target_vector): Add ft32_elf32_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
binutils/
	* readelf.c: Add FT32 support.
gas/
	* Makefile.am: Add FT32 files.
	* config/tc-ft32.c: New file.
	* config/tc-ft32.h: New file.
	* configure.tgt: Add FT32 support.
	* Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
gas/testsuite/
	* gas/ft32/ft32.exp: New file.
	* gas/ft32/insn.d: New file.
	* gas/ft32/insn.s: New file.
include/
	* dis-asm.h (print_insn_ft32): Declare.
include/elf/
	* common.h (EM_FT32): Define.
	* ft32.h: New file.
include/opcode/
	* ft32.h: New file.
ld/
	* Makefile.am: Add FT32 files.
	* configure.tgt: Handle FT32 target.
	* emulparams/elf32ft32.sh: New file.
	* scripttempl/ft32.sc: New file.
	* Makefile.in: Regenerate.
opcodes/
	* Makefile.am: Add FT32 files.
	* configure.ac: Handle FT32.
	* disassemble.c (disassembler): Call print_insn_ft32.
	* ft32-dis.c: New file.
	* ft32-opc.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
2015-01-28 16:25:18 +10:30
Kuan-Lin Chen
e5fe4957b4 NDS32/opcodes: Add new system registers. 2015-01-28 09:24:07 +08:00
Andreas Krebbel
1e2e8c529c S/390: Add support for IBM z13.
- 32 128 bit vector registers (overlapping with the existing 16 64 bit
  floating point registers)
- vector double instructions
- vector integer instructions
- scalar vector instructions (allowing to have more floating point
  registers for scalar operations)
- vector string instructions

gas/ChangeLog:

	* config/tc-s390.c (struct pd_reg): Remove.
	(pre_defined_registers): Remove.
	(REG_NAME_CNT): Remove.
	(reg_name_search): Calculate the register number instead of doing
	a lookup.
	(register_name, tc_s390_regname_to_dw2regnum): Adopt to the new
	reg_name_search signature.
	(s390_parse_cpu): Support the new arch string z13.
	(s390_insert_operand): Support for vector registers with the extra
	field for the fifth bit of each vector register operand.
	(md_gather_operand): Adjust to the new handling of optional
	parameters.

	* doc/as.texinfo: Document the z13 cpu string.

gas/testsuite/ChangeLog:

	* gas/s390/esa-g5.d: Add a variant without the optional operand.
	* gas/s390/esa-g5.s: Likewise.
	* gas/s390/esa-z9-109.d: Likewise.
	* gas/s390/esa-z9-109.s: Likewise.
	* gas/s390/zarch-z9-109.d: Likewise.
	* gas/s390/zarch-z9-109.s: Likewise.
	* gas/s390/zarch-z10.d: For variants with a zero optional argument
	it is not dumped by objdump anymore.
	* gas/s390/zarch-zEC12.d: Likewise.

	* gas/s390/zarch-z13.d: New file.
	* gas/s390/zarch-z13.s: New file.
	* gas/s390/s390.exp: Run the test for the z13 files.

include/opcode/ChangeLog:

	* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.

ld/testsuite/ChangeLog:

	* ld-s390/tlsbin.dd: The nopr register operand is optional and not
	printed if 0 anymore.

opcodes/ChangeLog:

	* s390-dis.c (s390_extract_operand): Support vector register
	operands.
	(s390_print_insn_with_opcode): Support new operands types and add
	new handling of optional operands.
	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	and include opcode/s390.h instead.
	(struct op_struct): New field `flags'.
	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	(dumpTable): Dump flags.
	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
	string.
	* s390-opc.c: Add new operands types, instruction formats, and
	instruction masks.
	(s390_opformats): Add new formats for .insn.
	* s390-opc.txt: Add new instructions.
2015-01-16 12:28:58 +01:00
Alan Modra
b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Anthony Green
bffb60047d Limit moxie sto/ldo offsets to 16 bits 2014-12-27 10:57:51 -05:00
Anthony Green
0be40ae409 Add mul.x and umul.x instructions to moxie port 2014-12-24 08:38:09 -05:00
Matthew Fortune
b9121b573e Add in a JALRC alias and fix the NAL instruction.
opcodes/

	* mips-opc.c (mips_builtin_opcodes): Add JALRC alias for JIALC.
	Remove the operand from NAL.

gas/testsuite/

	* gas/mips/r6.s: Test JALRC and NAL
	* gas/mips/r6-n32.d: Add expected output for JALRC and NAL.
	* gas/mips/r6-n64.d: Likewise.
	* gas/mips/r6.d: Likewise.
2014-12-16 22:33:12 +00:00
Anthony Green
26047f76c0 Add zex instructions for moxie port 2014-12-12 08:45:25 -05:00
Eric Botcazou
1945cfa59d Add Visium support to opcodes
include/
	* dis-asm.h (print_insn_visium): Declare.
include/opcode/
	* visium.h: New file.
opcodes/
	* configure.ac: Add Visium support.
	* configure: Regenerate.
	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add visium-dis.c and
	visium-opc.c.
	* Makefile.in: Regenerate.
	* disassemble.c (ARCH_visium): Define if ARCH_all.
	(disassembler): Deal with bfd_arch_visium if ARCH_visium.
	* visium-dis.c: New file.
	* visium-opc.c: Likewise.
	* po/POTFILES.in: Regenerate.
2014-12-06 16:25:55 +01:00
Alan Modra
db76a70026 Power4 should treat mftb as extended mfspr mnemonic
On further reading of ISA manual it appears gas should have been
treating mftb and mftbu as extended mnemonics for mfspr, for ISA 2.03
and later.

opcodes/
	* ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
	power4 and later.
gas/testsuite/
	* gas/ppc/a2.d: Update for mftb change.
	* gas/ppc/476.d: Likewise.
2014-11-30 13:29:24 +10:30
Sandra Loosemore
d306ce58b4 Remove broken nios2 assembler dwim support.
2014-11-28  Sandra Loosemore  <sandra@codesourcery.com>

	include/opcode/
	* nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
	(NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
	(NIOS2_INSN_OPTARG): Renumber.

	opcodes/
	* nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
	from descriptors.

	gas/
	* config/tc-nios2.c (can_evaluate_expr, get_expr_value): Delete.
	(output_addi, output_andi, output_ori, output_xori): Delete.
	(md_assemble): Remove calls to deleted functions.

	gas/testsuite/
	* gas/nios2/nios2.exp: Make "movi" a list test.
	* gas/nios2/movi.s: Adjust comments, add another case.
	* gas/nios2/movi.l: New.
	* gas/nios2/movi.d: Delete.
2014-11-28 14:41:32 -08:00
Alan Modra
8514e4db84 Don't deprecate powerpc mftb insn
mftb is marked phased out in the architecture manual, but we can keep
it as an extended mnemonic for mftbl.

	* ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
	(TB): Delete.
	(insert_tbr, extract_tbr): Validate tbr number.
2014-11-28 14:34:10 +10:30
H.J. Lu
6e733ccea9 Update libtool.m4 from GCC trunk
* libtool.m4: Updated from GCC trunk.

bfd/

	* configure: Regenerated.

binutils/

	* configure: Regenerated.

gas/

	* configure: Regenerated.

gprof/

	* configure: Regenerated.

ld/

	* configure: Regenerated.

opcodes/

	* configure: Regenerated.
2014-11-24 09:14:09 -08:00
Ilya Tocar
14f195c9a0 Add AVX512VBMI instructions
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512vbmi.
	* doc/c-i386.texi: Document it.

opcodes/

	* i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
	vpmultishiftqb.
	* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
	(cpu_flags): Add CpuAVX512VBMI.
	* i386-opc.h (enum): Add CpuAVX512VBMI.
	(i386_cpu_flags): Add cpuavx512vbmi.
	* i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
	vpermt2b.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

/gas/testsuite/

	* gas/i386/i386.exp: Run new tests.
	* gas/i386/avx512vbmi-intel.d: New file.
	* gas/i386/avx512vbmi.d: Likewise.
	* gas/i386/avx512vbmi.s: Likewise.
	* gas/i386/avx512vbmi_vl-intel.d: Likewise.
	* gas/i386/avx512vbmi_vl.d: Likewise.
	* gas/i386/avx512vbmi_vl.s: Likewise.
	* gas/i386/x86-64-avx512vbmi-intel.d: Likewise.
	* gas/i386/x86-64-avx512vbmi.d: Likewise.
	* gas/i386/x86-64-avx512vbmi.s: Likewise.
	* gas/i386/x86-64-avx512vbmi_vl-intel.d: Likewise.
	* gas/i386/x86-64-avx512vbmi_vl.d: Likewise.
	* gas/i386/x86-64-avx512vbmi_vl.s: Likewise.
2014-11-17 06:03:41 -08:00
Ilya Tocar
2cc1b5aad8 Add AVX512IFMA instructions
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512ifma.
	* doc/c-i386.texi: Document it.

opcodes/

	* i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
	* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
	PREFIX_EVEX_0F38B5.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
	(cpu_flags): Add CpuAVX512IFMA.
	* i386-opc.h (enum): Add CpuAVX512IFMA.
	(i386_cpu_flags): Add cpuavx512ifma.
	* i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

/gas/testsuite/

	* gas/i386/i386.exp: Run new tests.
	* gas/i386/avx512ifma-intel.d: New file.
	* gas/i386/avx512ifma.d: Likewise.
	* gas/i386/avx512ifma.s: Likewise.
	* gas/i386/avx512ifma_vl-intel.d: Likewise.
	* gas/i386/avx512ifma_vl.d: Likewise.
	* gas/i386/avx512ifma_vl.s: Likewise.
	* gas/i386/x86-64-avx512ifma-intel.d: Likewise.
	* gas/i386/x86-64-avx512ifma.d: Likewise.
	* gas/i386/x86-64-avx512ifma.s: Likewise.
	* gas/i386/x86-64-avx512ifma_vl-intel.d: Likewise.
	* gas/i386/x86-64-avx512ifma_vl.d: Likewise.
	* gas/i386/x86-64-avx512ifma_vl.s: Likewise.
2014-11-17 06:03:24 -08:00
Ilya Tocar
9d8596f079 Add pcommit instruction
gas/

	* config/tc-i386.c (cpu_arch): Add .pcommit.
	* doc/c-i386.texi: Document it.

/opcodes

	* i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
	(prefix_table): Add pcommit.
	* i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
	(cpu_flags): Add CpuPCOMMIT.
	* i386-opc.h (enum): Add CpuPCOMMIT.
	(i386_cpu_flags): Add cpupcommit.
	* i386-opc.tbl: Add pcommit.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

/gas/testsuite/

	* gas/i386/i386.exp: Run new tests.
	* gas/i386/pcommit-intel.d: New file.
	* gas/i386/pcommit.d: Likewise.
	* gas/i386/pcommit.s: Likewise.
	* gas/i386/x86-64-pcommit-intel.d: Likewise.
	* gas/i386/x86-64-pcommit.d: Likewise.
	* gas/i386/x86-64-pcommit.s: Likewise.
2014-11-17 05:56:47 -08:00
Ilya Tocar
c5e7287a1a Add clwb instruction
gas/

	* config/tc-i386.c (cpu_arch): Add .clwb.
	* doc/c-i386.texi: Document it.

opcodes/
	* i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
	(prefix_table): Add clwb.
	* i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
	(cpu_flags): Add CpuCLWB.
	* i386-opc.h (enum): Add CpuCLWB.
	(i386_cpu_flags): Add cpuclwb.
	* i386-opc.tbl: Add clwb.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

gas/testsuite/

	* gas/i386/i386.exp: Run new tests.
	* gas/i386/clwb-intel.d: New file.
	* gas/i386/clwb.d: Likewise.
	* gas/i386/clwb.s: Likewise.
	* gas/i386/x86-64-clwb-intel.d: Likewise.
	* gas/i386/x86-64-clwb.d: Likewise.
	* gas/i386/x86-64-clwb.s: Likewise.
2014-11-17 05:56:37 -08:00
Sandra Loosemore
b4714c7c30 Add mach parameter to nios2_find_opcode_hash.
2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>

	include/opcode/
	* nios2.h (nios2_find_opcode_hash): Add mach parameter to
	declaration.  Fix obsolete comment.

	opcodes/
	* nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
	(nios2_disassemble): Adjust call to nios2_find_opcode_hash.

	gas/
	* config/tc-nios2.c (nios2_diagnose_overflow): Adjust call to
	nios2_find_opcode_hash.
2014-11-06 13:12:21 -08:00
Nick Clifton
ba241f2d5a Import updated translations supplied by the Translation Project.
bfd, binutils, gprof, opcodes:
	* po/fi.po: Updated Finnish translation.

	binutils:
	* po/sv.po: Updated Swedish translation.

	gprof:
	* po/hu.po: New Hungarian translation.
2014-11-03 12:26:48 +00:00
Naveen H.S
2c62985659 MIPS: Add Octeon 3 support
binutils:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* readelf.c (print_mips_isa_ext): Print the value of Octeon3.

gas:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
	(mips_cpu_info_table): Octeon3 enables virt ase.
	* doc/c-mips.texi: Document octeon3 as an acceptable value for
	-march=.

gas/testsuite:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gas/mips/mips.exp: Add support for Octeon3 architecture.
	Also add in support for running Octeon3 tests.
	* gas/mips/octeon3.d: New test.
	* gas/mips/octeon3.s: New test source.

opcodes:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* mips-dis.c (mips_arch_choices): Add octeon3.
	* mips-opc.c (IOCT): Include INSN_OCTEON3.
	(IOCT2): Likewise.
	(IOCT3): New define.
	(IVIRT): New define.
	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
	IVIRT instructions.
	Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
	operand for IOCT3.

bfd:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* archures.c: Add octeon3 for mips target.
	* bfd-in2.h: Regenerate.
	* bfd/cpu-mips.c: Define I_mipsocteon3.
	nfo_struct): Add octeon3 support.
	* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
	octeon3.
	(mips_set_isa_flags): Add support for octeon3.
	(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
	(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
	extension of bfd_mach_mips_octeon2.
	(print_mips_isa_ext): Print the value of Octeon3.
2014-10-31 13:50:10 -07:00
Nick Clifton
64b588b51e Updated/new translations provided by the Translations Project. 2014-10-29 16:34:04 +00:00
Sandra Loosemore
96ba42336f Refactoring/cleanup of nios2 opcodes and assembler code.
2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>

	include/opcode/
	* nios2.h (enum iw_format_type): New.
	(struct nios2_opcode): Update comments.  Add size and format fields.
	(NIOS2_INSN_OPTARG): New.
	(REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
	(struct nios2_reg): Add regtype field.
	(GET_INSN_FIELD, SET_INSN_FIELD): Delete.
	(IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
	(IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
	(IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
	(IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
	(IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
	(IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
	(IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
	(IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
	(IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
	(IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
	(IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
	(OP_MASK_OP, OP_SH_OP): Delete.
	(OP_MASK_IOP, OP_SH_IOP): Delete.
	(OP_MASK_IRD, OP_SH_IRD): Delete.
	(OP_MASK_IRT, OP_SH_IRT): Delete.
	(OP_MASK_IRS, OP_SH_IRS): Delete.
	(OP_MASK_ROP, OP_SH_ROP): Delete.
	(OP_MASK_RRD, OP_SH_RRD): Delete.
	(OP_MASK_RRT, OP_SH_RRT): Delete.
	(OP_MASK_RRS, OP_SH_RRS): Delete.
	(OP_MASK_JOP, OP_SH_JOP): Delete.
	(OP_MASK_IMM26, OP_SH_IMM26): Delete.
	(OP_MASK_RCTL, OP_SH_RCTL): Delete.
	(OP_MASK_IMM5, OP_SH_IMM5): Delete.
	(OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
	(OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
	(OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
	(OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
	(OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
	(OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
	(OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
	(OP_MASK_<insn>, OP_MASK): Delete.
	(GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
	(GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
	Include nios2r1.h to define new instruction opcode constants
	and accessors.
	(nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
	(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
	(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
	(NUMOPCODES, NUMREGISTERS): Delete.
	* nios2r1.h: New file.

	opcodes/
	* nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
	(nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
	MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
	size and format initializers.  Merge 'b' arguments into 'j'.
	(NIOS2_NUM_OPCODES): Adjust definition.
	(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
	(nios2_opcodes): Adjust.
	(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
	* nios2-dis.c (INSNLEN): Update comment.
	(nios2_hash_init, nios2_hash): Delete.
	(OPCODE_HASH_SIZE): New.
	(nios2_r1_extract_opcode): New.
	(nios2_disassembler_state): New.
	(nios2_r1_disassembler_state): New.
	(nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
	(nios2_find_opcode_hash): Use state object.
	(bad_opcode): New.
	(nios2_print_insn_arg): Add op parameter.  Use it to access
	format.  Remove 'b' case.
	(nios2_disassemble): Remove special case for nop.  Remove
	hard-coded instruction size.

	gas/
	* config/tc-nios2.c (nios2_insn_infoS): Add constant_bits field.
	(nios2_arg_infoS, nios2_arg_hash, nios2_arg_lookup): Delete.
	(nios2_control_register_arg_p): Delete.
	(nios2_coproc_reg): Delete.
	(nios2_relax_frag): Remove hard-coded instruction size.
	(md_convert_frag): Use new insn accessor macros.
	(nios2_diagnose_overflow): Remove hard-coded instruction size.
	(md_apply_fix): Likewise.
	(bad_opcode): New.
	(nios2_parse_reg): New.
	(nios2_assemble_expression): Remove prev_reloc parameter.  Adjust
	uses and callers.
	(nios2_assemble_arg_c): New.
	(nios2_assemble_arg_d): New.
	(nios2_assemble_arg_s): New.
	(nios2_assemble_arg_t): New.
	(nios2_assemble_arg_i): New.
	(nios2_assemble_arg_u): New.
	(nios2_assemble_arg_o): New.
	(nios2_assemble_arg_j): New.
	(nios2_assemble_arg_l): New.
	(nios2_assemble_arg_m): New.
	(nios2_assemble_args): New.
	(nios2_assemble_args_dst): Delete.
	(nios2_assemble_args_tsi): Delete.
	(nios2_assemble_args_tsu): Delete.
	(nios2_assemble_args_sto): Delete.
	(nios2_assemble_args_o): Delete.
	(nios2_assemble_args_is): Delete.
	(nios2_assemble_args_m): Delete.
	(nios2_assemble_args_s): Delete.
	(nios2_assemble_args_tis): Delete.
	(nios2_assemble_args_dc): Delete.
	(nios2_assemble_args_cs): Delete.
	(nios2_assemble_args_ds): Delete.
	(nios2_assemble_args_ldst): Delete.
	(nios2_assemble_args_none): Delete.
	(nios2_assemble_args_dsj): Delete.
	(nios2_assemble_args_d): Delete.
	(nios2_assemble_args_b): Delete.
	(nios2_arg_info_structs): Delete.
	(NIOS2_NUM_ARGS): Delete.
	(nios2_consume_arg): Remove insn parameter.  Use new macros.
	Don't check register arguments here.  Remove 'b' case.
	(nios2_consume_separator): Move check for missing separators to...
	(nios2_parse_args): ...here.  Remove special case for optional
	arguments.
	(output_insn): Avoid using hard-coded insn size.
	(output_ubranch): Likewise.
	(output_cbranch): Likewise.
	(output_call): Use new macros.
	(output_addi): Likewise.
	(output_ori): Likewise.
	(output_xori): Likewise.
	(output_movia): Likewise.
	(md_begin): Remove nios2_arg_info_structs initialization.
	(md_assemble): Initialize constant_bits field.  Use
	nios2_parse_args instead of looking up parse function in hash table.

	gdb/
	* nios2-tdep.c (nios2_analyze_prologue): Use new instruction field
	accessors and constants from nios2 opcodes update.
	(nios2_get_next_pc): Likewise.
2014-10-23 09:54:15 -07:00
Jan Beulich
12e87fac5c ppc: enable msgclr and msgsnd on Power8
According to my reading of the spec it was an oversight for them to
not having got enabled when Power8 support got added.
2014-10-21 09:56:38 +02:00
Jose E. Marchesi
0b6be41550 opcodes, elf: annotate instructions with HWCAP2_VIS3B.
This patch annotates the following SPARC instructions as VIS3B
instructions: ldx *, %efsr, fpadd64, fpsub64, fpcmpule8, fpcmpune8,
fpcmpugt8, fpcmpueq8.  It also improves the documentation of the VIS3B
capability in several headers.

Tested in sparc64-unknown-linux-gnu and sparc-unknown-linux-gnu.
No visible regressions.

opcodes/ChangeLog:

  2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc-opcodes): Annotate several instructions with
	the HWCAP2_VIS3B hwcap.

include/opcodes/ChangeLog:

  2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc.h (HWCAP2_VIS3B): Documentation improved.

include/elf/ChangeLog:

  2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc.h (ELF_SPARC_HWCAP2_VIS3B): Documentation improved.
2014-10-17 22:00:02 +02:00
Jose E. Marchesi
d9490cd487 opcodes: fix several misplaced hwcap entries.
This patch fixes the hwcap entries in `sparc-opcodes' (which were
incorrectly located in the flags field) for the following
instructions:

  wr r,r,%sys_tick
  wr r,i,%sys_tick
  wr r,r,%sys_tick_cmpr
  wr r,i,%sys_tick_cmpr
  edge8n edge8ln edge16n edge16ln edge32n edge32ln
  bmask bshuffle siam

Tested in sparc-unknown-linux-gnu and sparc64-unknown-linux-gnu.
No visible regressions.

opcodes/ChangeLog:

  2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
	entries.
2014-10-17 21:59:56 +02:00
Tristan Gingold
91dc4e0a22 Bump bfd version.
bfd/
2014-10-15  Tristan Gingold  <gingold@adacore.com>

	* version.m4: Bump version to 2.25.51
	* configure: Regenerate.

binutils/
2014-10-15  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

gas/
2014-10-15  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

gprof/
2014-10-15  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

ld/
2014-10-15  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

opcodes/
2014-10-15  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.
2014-10-15 10:21:25 +02:00
Jose E. Marchesi
3d68f91c0f This is a series of patches that add support for the SPARC M7 cpu to
binutils.  They were discussed and approved here:

  https://sourceware.org/ml/binutils/2014-10/msg00038.html
2014-10-09 13:16:53 +01:00
H.J. Lu
68f3446482 Ignore MOD field for control/debug register move
This patch ignores the MOD field in control/debug register move
instructions.

gas/testsuite/

	* gas/i386/cdr.d: New file.
	* gas/i386/cdr.s: Likewise.
	* gas/i386/x86-64-cdr.d: Likewise.

	* gas/i386/i386.exp: Run cdr and x86-64-cdr.

opcodes/

	* i386-dis.c (MOD_0F20): Removed.
	(MOD_0F21): Likewise.
	(MOD_0F22): Likewise.
	(MOD_0F23): Likewise.
	(dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
	MOD_0F23 with "movZ".
	(mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
	(OP_R): Check mod/rm byte and call OP_E_register.
2014-09-22 09:38:53 -07:00
Kuan-Lin Chen
40c7a7cb74 NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.
First, add nds32 audio ISA extension including opcodes and registers.
Second, redesign the disassemble implement.
The original disassemble decode instruction opcode using switch-case.
It is hard to synchronize when adding new instructions.
Therefore, the new implement reuses nds32_opcodes to dump the instructions.
2014-09-16 12:28:11 +08:00
Andrew Bennett
7361da2c95 Add support for MIPS R6.
bfd/
 	* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
 	* archures.c (bfd_architecture): Likewise.
 	* bfd-in2.h (bfd_architecture): Likewise.
 	(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
 	BFD_RELOC_MIPS_19_PCREL_S2.
 	* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
 	* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
 	R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elf64-mips.c: Define REL, and RELA relocations R_MIPS_PC21_S2,
	R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16
	and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elfn32-mips.c: Likewise.
 	* elfxx-mips.c (MIPSR6_P): New define.
 	(mipsr6_exec_plt_entry): New array.
	(hi16_reloc_p): Add support for R_MIPS_PCHI16.
	(lo16_reloc_p): Add support for R_MIPS_PCLO16.
 	(aligned_pcrel_reloc_p): New function.
 	(mips_elf_relocation_needs_la25_stub): Add support for relocs:
 	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
 	(mips_elf_calculate_relocation): Add support for relocs:
 	R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
 	R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
	(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
 	(_bfd_mips_elf_check_relocs): Add support for relocs:
	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
 	(_bfd_mips_elf_relocate_section): Add a check for unaligned
 	pc relative relocs.
 	(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
 	plt entry.
 	(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
 	(_bfd_mips_elf_print_private_bfd_data): Likewise.
 	(mips_32bit_flags_p): Add support for mips32r6.
 	* libbfd.h (bfd_reloc_code_real_names): Add entries for
 	BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
 	BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
 	* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
 	BFD_RELOC_MIPS_19_PCREL_S2.

binutils/
 	* readelf.c (get_machine_flags): Add support for mips32r6 and
 	mips64r6.

elfcpp/
 	* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.

gas/
 	* config/tc-mips.c (mips_nan2008): New static global.
	(mips_flag_nan2008): Removed.
	(LL_SC_FMT): New define.
	(COP12_FMT): Updated.
	(ISA_IS_R6): New define.
 	(ISA_HAS_64BIT_REGS): Add mips64r6.
 	(ISA_HAS_DROR): Likewise.
 	(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
 	(ISA_HAS_ROR): Likewise.
 	(ISA_HAS_ODD_SINGLE_FPR): Likewise.
 	(ISA_HAS_MXHC1): Likewise.
 	(hilo_interlocks): Likewise.
 	(md_longopts): Likewise.
	(ISA_HAS_LEGACY_NAN): New define.
 	(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
 	(mips_ase): Add field rem_rev.
 	(mips_ases): Updated to add which ISA an ASE was removed in.
 	(mips_isa_rev): Add support for mips32r6 and mips64r6.
 	(mips_check_isa_supports_ase): Add support to check if an ASE
 	has been removed in the specified MIPS ISA revision.
 	(validate_mips_insn): Skip '-' character.
	(macro_build): Likewise.
	(mips_check_options): Prevent R6 working with fp32, mips16,
	micromips, or branch relaxation.
	(file_mips_check_options): Set R6 floating point registers to
	64 bit.  Also deal with the nan2008 option.
 	(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
	and OP_NON_ZERO_REG.
 	(match_check_prev_operand): New static function.
 	(match_same_rs_rt_operand): New static function.
	(match_non_zero_reg_operand): New static function.
 	(match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
	and OP_NON_ZERO_REG.
 	(insns_between): Added case to deal with forbidden slots.
 	(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
 	and BFD_RELOC_MIPS_26_PCREL_S2.
 	(match_insn): Add support for operands -A, -B, +' and +".  Also
 	skip '-' character.
 	(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
 	(md_parse_option): Add support for mips32r6 and mips64r6.  Also
	update the nan option handling.
 	(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2.
 	(mips_force_relocation): Prevent forced relaxation for MIPS r6.
 	(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	(s_mipsset): Add support for mips32r6 and mips64r6.
	(s_nan): Update to support the new nan2008 framework.
 	(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
	(mips_elf_final_processing): Updated to use the mips_nan2008.
 	(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
	(macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
	macros for R6.
	(mips_fix_adjustable): Make PC relative R6 relocations relative
	to the symbol and not the section.
 	* configure.ac: Add support for mips32r6 and mips64r6.
 	* configure: Regenerate.
 	* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
 	options.
	* doc/as.texinfo: Likewise.

gas/testsuite/
	* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent
	non-supported instructions from being tested.
	* gas/mips/24k-triple-stores-2.s: Likewise.
	* gas/mips/24k-triple-stores-3.s: Likewise.
	* gas/mips/24k-triple-stores-6.s: Likewise.
	* gas/mips/beq.s: Likewise.
	* gas/mips/eva.s: Likewise.
	* gas/mips/ld-zero-3.s: Likewise.
	* gas/mips/mips32-cp2.s: Likewise.
	* gas/mips/mips32.s: Likewise.
	* gas/mips/mips4.s: Likewise.
	* gas/mips/add.s: Don't test the add instructions if r6, and
	add padding.
	* gas/mips/add.d: Check for a triple dot not a nop at the end of the
	disassembly output.
	* gas/mips/micromips@add.d: Likewise.
	* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-2.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-3.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
	* gas/mips/mipsr6@add.d: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s: New file.
	* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s: New file.
	* gas/mips/mipsr6@beq.d: New file.
	* gas/mips/mipsr6@bge.d: New file.
	* gas/mips/mipsr6@bgeu.d: New file.
	* gas/mips/mipsr6@blt.d: New file.
	* gas/mips/mipsr6@bltu.d: New file.
	* gas/mips/mipsr6@branch-misc-1.d: New file.
	* gas/mips/mipsr6@branch-misc-2-64.d: New file.
	* gas/mips/mipsr6@branch-misc-2pic-64.d: New file.
	* gas/mips/mipsr6@branch-misc-4-64.d: New file.
	* gas/mips/mipsr6@cache.d: New file.
	* gas/mips/mipsr6@eva.d: New file.
	* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
	* gas/mips/mipsr6@jal-svr4pic.d: New file.
	* gas/mips/mipsr6@ld-zero-2.d: New file.
	* gas/mips/mipsr6@ld-zero-3.d: New file.
	* gas/mips/mipsr6@loc-swap-dis.d: New file.
	* gas/mips/mipsr6@mips32-cp2.d: New file.
	* gas/mips/mipsr6@mips32-imm.d: New file.
	* gas/mips/mipsr6@mips32.d: New file.
	* gas/mips/mipsr6@mips32r2.d: New file.
	* gas/mips/mipsr6@mips4-fp.d: New file.
	* gas/mips/mipsr6@mips4-fp.l: New file.
	* gas/mips/mipsr6@mips4-fp.s: New file.
	* gas/mips/mipsr6@mips4.d: New file.
	* gas/mips/mipsr6@mips5-fp.d: New file.
	* gas/mips/mipsr6@mips5-fp.l: New file.
	* gas/mips/mipsr6@mips5-fp.s: New file.
	* gas/mips/mipsr6@mips64.d: New file.
	* gas/mips/mipsr6@msa-branch.d: New file.
	* gas/mips/mipsr6@msa.d: New file.
	* gas/mips/mipsr6@pref.d: New file.
	* gas/mips/mipsr6@relax-swap3.d: New file.
	* gas/mips/r6-64-n32.d: New file.
	* gas/mips/r6-64-n64.d: New file.
	* gas/mips/r6-64-removed.l: New file.
	* gas/mips/r6-64-removed.s: New file.
	* gas/mips/r6-64.s: New file.
	* gas/mips/r6-attr-none-double.d: New file.
	* gas/mips/r6-n32.d: New file.
	* gas/mips/r6-n64.d: New file.
	* gas/mips/r6-removed.l: New file.
	* gas/mips/r6-removed.s: New file.
	* gas/mips/r6.d: New file.
	* gas/mips/r6.s: New file.
	* gas/mips/mipsr6@mips32-dsp.d: New file.
	* gas/mips/mipsr6@mips32-dspr2.d: New file.
	* gas/mips/mipsr6@mips32r2-ill.l: New file.
	* gas/mips/mipsr6@mips32r2-ill.s: New file.
	* gas/mips/cache.s: Add r6 instruction varients.
	* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
	architectures.  Also prevent non r6 supported tests from running.
	Finally, add in support for running the new r6 tests.
	(run_dump_test_arch): Add support for mipsr6 tests.
	(run_list_test_arch): Add support for using files of the
	form arch@testname.l .

include/elf/
 	* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
 	R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(E_MIPS_ARCH_32R6): New define.
 	(E_MIPS_ARCH_64R6): New define.

include/opcode/
 	* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
 	OP_CHECK_PREV and OP_NON_ZERO_REG.  Add descriptions for the MIPS R6
	instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
	 +I, +O, +R, +:, +\, +", +;
	(mips_check_prev_operand): New struct.
 	(INSN2_FORBIDDEN_SLOT): New define.
 	(INSN_ISA32R6): New define.
 	(INSN_ISA64R6): New define.
	(INSN_UPTO32R6): New define.
	(INSN_UPTO64R6): New define.
	(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
 	(ISA_MIPS32R6): New define.
 	(ISA_MIPS64R6): New define.
 	(CPU_MIPS32R6): New define.
 	(CPU_MIPS64R6): New define.
 	(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.

ld/
 	* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.

opcodes/
 	* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 	mips64r6.
 	(parse_mips_dis_option): Allow MSA and virtualization support for
 	mips64r6.
 	(mips_print_arg_state): Add fields dest_regno and seen_dest.
 	(mips_seen_register): New function.
 	(print_insn_arg): Refactored code to use mips_seen_register
	function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
	OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
	the register rather than aborting.
 	(print_insn_args): Add length argument.  Add code to correctly
	calculate the instruction address for pc relative instructions.
	(validate_insn_args): New static function.
 	(print_insn_mips): Prevent jalx disassembling for r6.  Use
	validate_insn_args.
	(print_insn_micromips): Use validate_insn_args.
	all the arguments are valid.
	* mips-formats.h (PREV_CHECK): New define.
 	* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 	-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 	(RD_pc): New define.
 	(FS): New define.
 	(I37): New define.
 	(I69): New define.
 	(mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 	MIPS R6 instructions from MIPS R2 instructions.
2014-09-15 12:15:55 +01:00
H.J. Lu
4b4c407a34 Properly handle suffix for iret and sysret
gas/testsuite/

	* gas/i386/i386.exp: Run suffix-intel, x86-64-suffix and
	x86-64-suffix-intel.

	* gas/i386/suffix.s: Add tests for iret and sysret.
	* gas/i386/suffix.d: Updated.

	* gas/i386/suffix-intel.d: New file.
	* gas/i386/x86-64-suffix-intel.d: Likewise.
	* gas/i386/x86-64-suffix.d: Likewise.
	* gas/i386/x86-64-suffix.s: Likewise.

opcodes/

	* i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
	(putop): Handle "%LP".
2014-09-10 09:39:24 -07:00
Jiong Wang
df7b4545b2 [PATCH/AArch64] Generic support for all system registers using mrs and msr
2014-09-03  Jiong Wang  <jiong.wang@arm.com>

  opcode/
    * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
    * aarch64-dis-2.c: Update auto-generated file.

  gas/
    * config/tc-aarch64.c (parse_sys_reg): Remove the restriction on op0 field.

  gas/testsuite/
    * gas/aarch64/illegal.s: Update testcase.
    * gas/aarch64/illegal.d: Likewise.
    * gas/aarch64/sysreg-1.s: Likewise.
    * gas/aarch64/sysreg-1.d: Likewise.
2014-09-03 14:53:53 +01:00
Jiong Wang
ee804238f0 [PATCH/AArch64] Implement LSE feature
2014-09-03  Jiong Wang  <jiong.wang@arm.com>

  gas/
	* config/tc-aarch64.c (parse_operands): Recognize PAIRREG.
	(aarch64_features): Add entry for lse extension.

  include/opcode/
	* aarch64.h (AARCH64_FEATURE_LSE): New feature added.
	(aarch64_opnd): Add AARCH64_OPND_PAIRREG.
	(aarch64_insn_class): Add lse_atomic.
	(F_LSE_SZ): New field added.
	(opcode_has_special_coder): Recognize F_LSE_SZ.

  opcode/
	* aarch64-tbl.h (QL_R4NIL): New qualifiers.
	(aarch64_feature_lse): New feature added.
	(LSE): New Added.
	(aarch64_opcode_table): New LSE instructions added.  Improve
	descriptions for ldarb/ldarh/ldar.
	(aarch64_opcode_table): Describe PAIRREG.
	* aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
	* aarch64-opc.c (fields): Add entry for F_LSE_SZ.
	(aarch64_print_operand): Recognize PAIRREG.
	(operand_general_constraint_met_p): Check reg pair constraints for CASP
	instructions.
	* aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
	(do_special_decoding): Recognize F_LSE_SZ.
	* aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.

  gas/testsuite/
	* gas/aarch64/lse-atomic.d: New.
	* gas/aarch64/lse-atomic.s: Likewise.
	* gas/aarch64/illegal-lse.d: Likewise.
	* gas/aarch64/illegal-lse.l: Likewise.
	* gas/aarch64/illegal-lse.s: Likewise.
	* gas/aarch64/diagnostic.s: Check processor feature detect for lse
	instruction.
	* gas/aarch64/diagnostic.l: Likewise.
2014-09-03 14:53:53 +01:00
Maciej W. Rozycki
5575639b8d MIPS: Make the CODE10 operand code consistent between ISAs
This change moves the microMIPS 10-bit uninterpreted immediate code
embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL
instructions from `B' over to `+J' which is the operand code used in
the standard MIPS instruction set for a similar code embedded at bits
20..11, currently used by HYPCALL only in that set.

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
	(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
	"sdbbp", "syscall" and "wait".

	include/opcode/
	* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
	over to `+J'.
2014-08-26 13:44:34 +01:00
Maciej W. Rozycki
84919466a8 ARM/opcodes: Fix negative hexadecimal offset disassembly
2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	opcodes/
	* arm-dis.c (print_arm_address): Negate the GPR-relative offset
	returned if the U bit is set.

2014-08-21  Paul Brook  <paul@codesourcery.com>

	gas/testsuite/
	* gas/arm/arch7a-mp.d: Adjust according to `print_arm_address'
	offset fix.
	* gas/arm/arch7r-mp.d: Likewise.
2014-08-22 16:42:12 +01:00
Maciej W. Rozycki
a6c7053929 MIPS/opcodes: Remove microMIPS 48-bit LI instruction
The 48-bit LI instruction encoding has been removed from the microMIPS
ISA and no implementation ever made that included it.

	* micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
	48-bit "li" encoding.
2014-08-21 12:57:00 +01:00
Andreas Arnez
9ace48f3d7 This patch set mainly aims at improving the S/390 disassembler's
readability and also fixes some minor issues.

  S/390: Split disassembler routine into smaller functions
  S/390: Fix disassembler's treatment of signed/unsigned operands
  S/390: Fix off-by-one error in disassembler initialization
  S/390: Simplify opcode search loop in disassembler
  S/390: Drop function pointer dereferences in disassembler
  S/390: Various minor simplifications in disassembler
2014-08-19 15:42:13 +01:00
Mike Frysinger
60ac5798c8 opcodes: blackfin: convert ad-hoc ints to bfd_boolean
These various int fields are being used as booleans, so change to the
existing bfd_boolean style.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2014-08-14 09:14:39 -04:00
Mike Frysinger
b3f3b4b030 opcodes: blackfin: simplify decode_CC2stat_0 logic
These multiple if statements can be condensed down into a single if
statement and an array of strings.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2014-08-14 09:10:12 -04:00
Mike Frysinger
a4e600b22e opcodes: blackfin: avoid duplicate memory reads
Rather than reading the same memory twice, pass the value back up.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2014-08-14 09:07:37 -04:00
Mike Frysinger
703ec4e8d0 opcodes: blackfin: push down global state
The variables used to track insn state should be pushed down into the
private_data structure to avoid pollution across calls.

This also happens to fix the output when hitting comments/invalid insns
which needs to tweak a gas test.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2014-08-13 07:06:15 -04:00
Mike Frysinger
ed2c487956 opcodes: blackfin: do not force align the PC
If the user gives us an unaligned PC, then dump an error as such.
Otherwise if you try to disassemble at an odd address, the output
will look weird (it'll read one byte earlier).

This can be seen in one of the gas tests where data is in the middle
of .text, so move the data to .data like it should be in the first place.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2014-08-13 06:58:34 -04:00
Mike Frysinger
ba32981791 opcodes: blackfin: handle memory read errors
The current code ignores memory read errors which isn't a great idea.
So add a helper function which takes care of error checking and update
the code to use that.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2014-08-13 06:49:47 -04:00
Matthew Fortune
43885403ed [MIPS] Rename COPROC related macros
gas/

	* config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC
	and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout.

include/opcode/

	* mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
	(INSN_LOAD_COPROC): New define.
	(INSN_COPROC_MOVE_DELAY): Rename to...
	(INSN_COPROC_MOVE): New define.

opcodes/

	* micromips-opc.c (COD): Rename throughout to...
	(CM): New define, update to use INSN_COPROC_MOVE.
	(LCD): Rename throughout to...
	(LC): New define, update to use INSN_LOAD_COPROC.
	* mips-opc.c: Likewise.
2014-07-29 13:58:54 +01:00
Matthew Fortune
351cdf24d2 [MIPS] Implement O32 FPXX, FP64 and FP64A ABI extensions
Specification:
https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking

include/

	* elf/mips.h (PT_MIPS_ABIFLAGS, SHT_MIPS_ABIFLAGS): Define.
	(Val_GNU_MIPS_ABI_FP_OLD_64): Rename from Val_GNU_MIPS_ABI_FP_64.
	(Val_GNU_MIPS_ABI_FP_64): Redefine.
	(Val_GNU_MIPS_ABI_FP_XX): Define.
	(Elf_External_ABIFlags_v0, Elf_Internal_ABIFlags_v0): New structures.
	(AFL_REG_NONE, AFL_REG_32, AFL_REG_64, AFL_REG_128): Define.
	(AFL_ASE_DSP, AFL_ASE_DSPR2, AFL_ASE_EVA, AFL_ASE_MCU): Likewise.
	(AFL_ASE_MDMX, AFL_ASE_MIPS3D, AFL_ASE_MT, AFL_ASE_SMARTMIPS): Likewise.
	(AFL_ASE_VIRT, AFL_ASE_MSA, AFL_ASE_MIPS16): Likewise.
	(AFL_ASE_MICROMIPS, AFL_ASE_XPA): Likewise.
	(AFL_EXT_XLR, AFL_EXT_OCTEON2, AFL_EXT_OCTEONP): Likewise.
	(AFL_EXT_LOONGSON_3A, AFL_EXT_OCTEON, AFL_EXT_5900): Likewise.
	(AFL_EXT_4650, AFL_EXT_4010, AFL_EXT_4100, AFL_EXT_3900): Likewise.
	(AFL_EXT_10000, AFL_EXT_SB1, AFL_EXT_4111, AFL_EXT_4120): Likewise.
	(AFL_EXT_5400, AFL_EXT_5500, AFL_EXT_LOONGSON_2E): Likewise.
	(AFL_EXT_LOONGSON_2F): Likewise.
	(bfd_mips_elf_swap_abiflags_v0_in): Prototype.
	(bfd_mips_elf_swap_abiflags_v0_out): Likewise.
	(bfd_mips_isa_ext): Likewise.

bfd/

	* elfxx-mips.c (ABI_O32_P, MIPS_ELF_ABIFLAGS_SECTION_NAME_P): New macro.
	(mips_elf_obj_tdata): Add abiflags and abiflags_valid fields.
	(bfd_mips_elf_swap_abiflags_v0_in): New function.
	(bfd_mips_elf_swap_abiflags_v0_out): Likewise.
	(_bfd_mips_elf_section_from_shdr): Handle SHT_MIPS_ABIFLAGS.
	(_bfd_mips_elf_fake_sections): Likewise.
	(_bfd_mips_elf_always_size_sections): Handle .MIPS.abiflags.
	(_bfd_mips_elf_additional_program_headers): Account for new
	PT_MIPS_ABIFLAGS program header.
	(_bfd_mips_elf_modify_segment_map): Create PT_MIPS_ABIFLAGS segment and
	associate with .MIPS.abiflags.
	(_bfd_mips_elf_gc_mark_extra_sections): New function.
	(bfd_mips_isa_ext, update_mips_abiflags_isa): New static function.
	(infer_mips_abiflags): Likewise.
	(_bfd_mips_elf_final_link): Handle .MIPS.abiflags.
	(mips_32bit_flags_p): Moved higher.
	(mips_elf_merge_obj_attributes, _bfd_mips_fp_abi_string): Error
	checking for FP ABIs.
	(_bfd_mips_elf_merge_private_bfd_data): Restructure and add abiflags
	checks.  Check EF_MIPS_FP64 flag consistency.
	(print_mips_ases, print_mips_isa_ext): New static function.
	(print_mips_fp_abi_value, get_mips_reg_size): Likewise.
	(_bfd_mips_elf_print_private_bfd_data): Display abiflags data.
	(_bfd_mips_post_process_headers): Set EI_ABIVERSION = 3 for
	Val_GNU_MIPS_ABI_FP_64 or Val_GNU_MIPS_ABI_FP_64A.
	* elfxx-mips.h (_bfd_mips_elf_gc_mark_extra_sections): New prototype.
	* elf32-mips.c (elf_backend_gc_mark_extra_sections): Implement.
	* elfn32-mips.c (elf_backend_gc_mark_extra_sections): Implement.
	* elf64-mips.c (elf_backend_gc_mark_extra_sections): Implement.

binutils/

	* readelf.c (get_mips_segment_type): Display name for PT_MIPS_ABIFLAGS.
	(get_mips_section_type_name): Display name for SHT_MIPS_ABIFLAGS.
	(display_mips_gnu_attribute): Abstracted fp abi printing to...
	(print_mips_fp_abi_value): New static function. Handle new FP ABIs.
	(print_mips_ases, print_mips_isa_ext): New static functions.
	(get_mips_reg_size): Likewise.
	(process_mips_specific): Display abiflags data.

elfcpp/

	* elfcpp.h (PT_MIPS_ABIFLAGS): New program header type.

gas/

	* config/tc-mips.c (mips_flags_frag): New static global.
	(struct mips_set_options): Add oddspreg field.
	(file_mips_opts, mips_opts): Initialize oddspreg.
	(ISA_HAS_ODD_SINGLE_FPR): Add CPU argument and update for R5900 and
	Loongson-3a.
	(enum options, md_longopts, md_parse_option): Add -mfpxx, -modd-spreg
	and -mno-odd-spreg options.
	(md_begin): Create .MIPS.abiflags section.
	(fpabi_incompatible_with, fpabi_requires): New static function.
	(check_fpabi): Likewise.
	(mips_check_options): Handle fp=xx and oddspreg restrictions.
	(file_mips_check_options): Set oddspreg by default for fp=xx.
	(mips_oddfpreg_ok): Re-write function.
	(check_regno): Check odd numbered registers regardless of FPR size.
	For fp != 32 use as_bad instead of as_warn.
	(match_float_constant): Rewrite check regarding FP register width.  Add
	support for generating constants when MXHC1 is present.  Handle fp=xx
	to comply with the ABI.
	(macro): Update M_LI_DD similarly to match_float_constant.  Generate
	MTHC1 when available.  Check that correct code can be generated for
	fp=xx and fp=64 ABIs.
	(parse_code_option, s_mipsset): Add fp=xx, oddspreg and nooddspreg
	options.
	(mips_convert_ase_flags): New static function.
	(mips_elf_final_processing): Use fpabi == Val_GNU_MIPS_ABI_FP_OLD_64
	to determine when to add the EF_MIPS_FP64 flag.  Populate the
	.MIPS.abiflags section.
	(md_mips_end): Update .gnu_attribute based on command line and .module
	as applicable.  Use check_fpabi to ensure .gnu.attribute and command
	line/.module options are consistent.
	* doc/as.texinfo: Add missing -mgp64/-mfp64 options and document new
	-mfpxx, -modd-spreg and -mno-odd-spreg options.
	* doc/c-mips.texi: Document -mfpxx, -modd-spreg, -mno-odd-spreg,
	gnu_attribute values and FP ABIs.

ld/

	* emulparams/elf32bmip.sh: Add .MIPS.abiflags.
	* emulparams/elf32bmipn32-defs.sh: Likewise.
	* emulparams/elf64bmip-defs.sh: Likewise.

opcodes/

	* micromips-opc.c (COD, LCD) New macros.
	(cfc1, ctc1): Remove FP_S attribute.
	(dmfc1, mfc1, mfhc1): Add LCD attribute.
	(dmtc1, mtc1, mthc1): Add COD attribute.
	* mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.

binutils/testsuite/

	* binutils-all/readelf.s: Account for .MIPS.abiflags and
	.gnu.attributes.
	* binutils-all/readelf.ss-tmips: Likewise.
	* binutils-all/strip-3.d: Likewise.

gas/testsuite/

	* gas/mips/attr-gnu-4-0.d: New.
	* gas/mips/attr-gnu-4-0.s: Likewise.
	* gas/mips/attr-gnu-4-1-mfp32.l: Likewise.
	* gas/mips/attr-gnu-4-1-mfp32.s: Likewise.
	* gas/mips/attr-gnu-4-1-mfp64.l: Likewise.
	* gas/mips/attr-gnu-4-1-mfp64.s: Likewise.
	* gas/mips/attr-gnu-4-1-mfpxx.s: Likewise.
	* gas/mips/attr-gnu-4-1-msingle-float.l: Likewise.
	* gas/mips/attr-gnu-4-1-msingle-float.s: Likewise.
	* gas/mips/attr-gnu-4-1-msoft-float.l: Likewise.
	* gas/mips/attr-gnu-4-1-msoft-float.s: Likewise.
	* gas/mips/attr-gnu-4-1.d: Likewise.
	* gas/mips/attr-gnu-4-1.s: Likewise.
	* gas/mips/attr-gnu-4-2-mdouble-float.l: Likewise.
	* gas/mips/attr-gnu-4-2-mdouble-float.s: Likewise.
	* gas/mips/attr-gnu-4-2-msoft-float.l: Likewise.
	* gas/mips/attr-gnu-4-2-msoft-float.s: Likewise.
	* gas/mips/attr-gnu-4-2.d: Likewise.
	* gas/mips/attr-gnu-4-2.s: Likewise.
	* gas/mips/attr-gnu-4-3-mhard-float.l: Likewise.
	* gas/mips/attr-gnu-4-3-mhard-float.s: Likewise.
	* gas/mips/attr-gnu-4-3.d: Likewise.
	* gas/mips/attr-gnu-4-3.s: Likewise.
	* gas/mips/attr-gnu-4-4.l: Likewise.
	* gas/mips/attr-gnu-4-4.s: Likewise.
	* gas/mips/attr-gnu-4-5-64.l: Likewise.
	* gas/mips/attr-gnu-4-5-64.s: Likewise.
	* gas/mips/attr-gnu-4-5.d: Likewise.
	* gas/mips/attr-gnu-4-5.l: Likewise.
	* gas/mips/attr-gnu-4-5.s: Likewise.
	* gas/mips/attr-gnu-4-6-64.l: Likewise.
	* gas/mips/attr-gnu-4-6-64.s: Likewise.
	* gas/mips/attr-gnu-4-6.d: Likewise.
	* gas/mips/attr-gnu-4-6.l: Likewise.
	* gas/mips/attr-gnu-4-6.s: Likewise.
	* gas/mips/attr-gnu-4-6-msingle-float.l: Likewise.
	* gas/mips/attr-gnu-4-6-msingle-float.s: Likewise.
	* gas/mips/attr-gnu-4-6-msoft-float.l: Likewise.
	* gas/mips/attr-gnu-4-6-msoft-float.s: Likewise.
	* gas/mips/attr-gnu-4-6-noodd.l: Likewise.
	* gas/mips/attr-gnu-4-6-noodd.s: Likewise.
	* gas/mips/attr-gnu-4-7-64.l: Likewise.
	* gas/mips/attr-gnu-4-7-64.s: Likewise.
	* gas/mips/attr-gnu-4-7-msingle-float.l: Likewise.
	* gas/mips/attr-gnu-4-7-msingle-float.s: Likewise.
	* gas/mips/attr-gnu-4-7-msoft-float.l: Likewise.
	* gas/mips/attr-gnu-4-7-msoft-float.s: Likewise.
	* gas/mips/attr-gnu-4-7-odd.l: Likewise.
	* gas/mips/attr-gnu-4-7-odd.s: Likewise.
	* gas/mips/attr-gnu-4-7.d: Likewise.
	* gas/mips/attr-gnu-4-7.l: Likewise.
	* gas/mips/attr-gnu-4-7.s: Likewise.
	* gas/mips/attr-none-double.d: Likewise.
	* gas/mips/attr-none-o32-fp64.d: Likewise.
	* gas/mips/attr-none-o32-fp64-nooddspreg.d
	* gas/mips/attr-none-o32-fpxx.d: Likewise.
	* gas/mips/attr-none-single-float.d: Likewise.
	* gas/mips/attr-none-soft-float.d: Likewise.
	* gas/mips/elf_arch_mips32r3.d: Likewise.
	* gas/mips/elf_arch_mips32r5.d: Likewise.
	* gas/mips/elf_arch_mips64r3.d: Likewise.
	* gas/mips/elf_arch_mips64r5.d: Likewise.
	* gas/mips/li-d.d: Likewise.
	* gas/mips/li-d.s: Likewise.
	* gas/mips/module-check-warn.l: Likewise.
	* gas/mips/module-check-warn.s: Likewise.
	* gas/mips/module-check.d: Likewise.
	* gas/mips/module-check.s: Likewise.
	* gas/mips/module-mfp32.d: Likewise.
	* gas/mips/module-mfp32.s: Likewise.
	* gas/mips/module-mfp64.d: Likewise.
	* gas/mips/module-mfp64.s: Likewise.
	* gas/mips/module-mfp64-noodd.d: Likewise.
	* gas/mips/module-mfp64-noodd.s: Likewise.
	* gas/mips/module-mfpxx.d: Likewise.
	* gas/mips/module-mfpxx.s: Likewise.
	* gas/mips/module-msingle-float.d: Likewise.
	* gas/mips/module-msingle-float.s: Likewise.
	* gas/mips/module-msoft-float.d: Likewise.
	* gas/mips/module-msoft-float.s: Likewise.
	* gas/mips/module-set-mfpxx.d: Likewise.
	* gas/mips/module-set-mfpxx.s: Likewise.
	* gas/mips/fpxx-oddfpreg.d: Likewise.
	* gas/mips/fpxx-oddfpreg.l: Likewise.
	* gas/mips/fpxx-oddfpreg.s: Likewise.
	* gas/mips/no-odd-spreg.d: Likewise.
	* gas/mips/odd-spreg.d: Likewise.
	* gas/elf/section2.e-mips: Adjust expected output.
	* gas/mips/attr-gnu-abi-fp-1.d: Likewise.
	* gas/mips/attr-gnu-abi-msa-1.d: Likewise.
	* gas/mips/call-nonpic-1.d: Likewise.
	* gas/mips/elf_arch_mips1.d: Likewise.
	* gas/mips/elf_arch_mips2.d: Likewise.
	* gas/mips/elf_arch_mips3.d: Likewise.
	* gas/mips/elf_arch_mips32.d: Likewise.
	* gas/mips/elf_arch_mips32r2.d: Likewise.
	* gas/mips/elf_arch_mips4.d: Likewise.
	* gas/mips/elf_arch_mips5.d: Likewise.
	* gas/mips/elf_arch_mips64.d: Likewise.
	* gas/mips/elf_arch_mips64r2.d: Likewise.
	* gas/mips/elf_ase_micromips-2.d: Likewise.
	* gas/mips/elf_ase_micromips.d: Likewise.
	* gas/mips/elf_ase_mips16-2.d: Likewise.
	* gas/mips/elf_ase_mips16.d: Likewise.
	* gas/mips/module-defer-warn1.d: Likewise.
	* gas/mips/module-override.d: Likewise.
	* gas/mips/n32-consec.d: Likewise.
	* gas/mips/nan-2008-1.d: Likewise.
	* gas/mips/nan-2008-2.d: Likewise.
	* gas/mips/nan-2008-3.d: Likewise.
	* gas/mips/nan-2008-4.d: Likewise.
	* gas/mips/nan-legacy-1.d: Likewise.
	* gas/mips/nan-legacy-2.d: Likewise.
	* gas/mips/nan-legacy-3.d: Likewise.
	* gas/mips/nan-legacy-4.d: Likewise.
	* gas/mips/nan-legacy-5.d: Likewise.
	* gas/mips/tmips16-e.d: Likewise.
	* gas/mips/tmips16-f.d: Likewise.
	* gas/mips/tmipsel16-e.d: Likewise.
	* gas/mips/tmipsel16-f.d: Likewise.
	* gas/testsuite/gas/mips/mips.exp: Add new tests.

ld/testsuite/

	* ld-mips-elf/abiflags-strip1-ph.d: New.
	* ld-mips-elf/abiflags-strip2-ph.d: Likewise.
	* ld-mips-elf/abiflags-strip3-ph.d: Likewise.
	* ld-mips-elf/abiflags-strip4-ph.d: Likewise.
	* ld-mips-elf/abiflags-strip5-ph.d: Likewise.
	* ld-mips-elf/abiflags-strip6-ph.d: Likewise.
	* ld-mips-elf/abiflags-strip7-ph.d: Likewise.
	* ld-mips-elf/abiflags-strip8-ph.d: Likewise.
	* ld-mips-elf/abiflags-strip9-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-0-n32-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-0-n64-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-0-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-06.d: Likewise.
	* ld-mips-elf/attr-gnu-4-07.d: Likewise.
	* ld-mips-elf/attr-gnu-4-08.d: Likewise.
	* ld-mips-elf/attr-gnu-4-1-n32-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-1-n64-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-1-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-16.d: Likewise.
	* ld-mips-elf/attr-gnu-4-17.d: Likewise.
	* ld-mips-elf/attr-gnu-4-18.d: Likewise.
	* ld-mips-elf/attr-gnu-4-2-n32-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-2-n64-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-2-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-26.d: Likewise.
	* ld-mips-elf/attr-gnu-4-27.d: Likewise.
	* ld-mips-elf/attr-gnu-4-28.d: Likewise.
	* ld-mips-elf/attr-gnu-4-3-n32-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-3-n64-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-3-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-36.d: Likewise.
	* ld-mips-elf/attr-gnu-4-37.d: Likewise.
	* ld-mips-elf/attr-gnu-4-38.d: Likewise.
	* ld-mips-elf/attr-gnu-4-4-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-46.d: Likewise.
	* ld-mips-elf/attr-gnu-4-47.d: Likewise.
	* ld-mips-elf/attr-gnu-4-48.d: Likewise.
	* ld-mips-elf/attr-gnu-4-5-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-50.d: Likewise.
	* ld-mips-elf/attr-gnu-4-52.d: Likewise.
	* ld-mips-elf/attr-gnu-4-53.d: Likewise.
	* ld-mips-elf/attr-gnu-4-54.d: Likewise.
	* ld-mips-elf/attr-gnu-4-55.d: Likewise.
	* ld-mips-elf/attr-gnu-4-56.d: Likewise.
	* ld-mips-elf/attr-gnu-4-57.d: Likewise.
	* ld-mips-elf/attr-gnu-4-58.d: Likewise.
	* ld-mips-elf/attr-gnu-4-6-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-6.s: Likewise.
	* ld-mips-elf/attr-gnu-4-60.d: Likewise.
	* ld-mips-elf/attr-gnu-4-61.d: Likewise.
	* ld-mips-elf/attr-gnu-4-62.d: Likewise.
	* ld-mips-elf/attr-gnu-4-63.d: Likewise.
	* ld-mips-elf/attr-gnu-4-64.d: Likewise.
	* ld-mips-elf/attr-gnu-4-65.d: Likewise.
	* ld-mips-elf/attr-gnu-4-66.d: Likewise.
	* ld-mips-elf/attr-gnu-4-67.d: Likewise.
	* ld-mips-elf/attr-gnu-4-68.d: Likewise.
	* ld-mips-elf/attr-gnu-4-7-ph.d: Likewise.
	* ld-mips-elf/attr-gnu-4-7.s: Likewise.
	* ld-mips-elf/attr-gnu-4-70.d: Likewise.
	* ld-mips-elf/attr-gnu-4-71.d: Likewise.
	* ld-mips-elf/attr-gnu-4-72.d: Likewise.
	* ld-mips-elf/attr-gnu-4-73.d: Likewise.
	* ld-mips-elf/attr-gnu-4-74.d: Likewise.
	* ld-mips-elf/attr-gnu-4-75.d: Likewise.
	* ld-mips-elf/attr-gnu-4-76.d: Likewise.
	* ld-mips-elf/attr-gnu-4-77.d: Likewise.
	* ld-mips-elf/attr-gnu-4-78.d: Likewise.
	* ld-mips-elf/attr-gnu-4-8.s: Likewise.
	* ld-mips-elf/attr-gnu-4-81.d: Likewise.
	* ld-mips-elf/empty.s: Likewise.
	* ld-mips-elf/attr-gnu-4-00.d: Adjust expected output.
	* ld-mips-elf/attr-gnu-4-01.d: Likewise.
	* ld-mips-elf/attr-gnu-4-02.d: Likewise.
	* ld-mips-elf/attr-gnu-4-03.d: Likewise.
	* ld-mips-elf/attr-gnu-4-04.d: Likewise.
	* ld-mips-elf/attr-gnu-4-05.d: Likewise.
	* ld-mips-elf/attr-gnu-4-10.d: Likewise.
	* ld-mips-elf/attr-gnu-4-11.d: Likewise.
	* ld-mips-elf/attr-gnu-4-14.d: Likewise.
	* ld-mips-elf/attr-gnu-4-15.d: Likewise.
	* ld-mips-elf/attr-gnu-4-2.s: Likewise.
	* ld-mips-elf/attr-gnu-4-20.d: Likewise.
	* ld-mips-elf/attr-gnu-4-22.d: Likewise.
	* ld-mips-elf/attr-gnu-4-24.d: Likewise.
	* ld-mips-elf/attr-gnu-4-25.d: Likewise.
	* ld-mips-elf/attr-gnu-4-3.s: Likewise.
	* ld-mips-elf/attr-gnu-4-30.d: Likewise.
	* ld-mips-elf/attr-gnu-4-33.d: Likewise.
	* ld-mips-elf/attr-gnu-4-34.d: Likewise.
	* ld-mips-elf/attr-gnu-4-35.d: Likewise.
	* ld-mips-elf/attr-gnu-4-40.d: Likewise.
	* ld-mips-elf/attr-gnu-4-41.d: Likewise.
	* ld-mips-elf/attr-gnu-4-42.d: Likewise.
	* ld-mips-elf/attr-gnu-4-43.d: Likewise.
	* ld-mips-elf/attr-gnu-4-44.d: Likewise.
	* ld-mips-elf/attr-gnu-4-45.d: Likewise.
	* ld-mips-elf/attr-gnu-4-5.s: Likewise.
	* ld-mips-elf/attr-gnu-4-51.d: Likewise.
	* ld-mips-elf/attr-gnu-8-00.d: Likewise.
	* ld-mips-elf/attr-gnu-8-01.d: Likewise.
	* ld-mips-elf/attr-gnu-8-02.d: Likewise.
	* ld-mips-elf/attr-gnu-8-10.d: Likewise.
	* ld-mips-elf/attr-gnu-8-11.d: Likewise.
	* ld-mips-elf/attr-gnu-8-20.d: Likewise.
	* ld-mips-elf/attr-gnu-8-22.d: Likewise.
	* ld-mips-elf/jalx-2.dd: Likewise.
	* ld-mips-elf/mips16-pic-1.gd: Likewise.
	* ld-mips-elf/mips16-pic-2.gd: Likewise.
	* ld-mips-elf/mips16-pic-3.gd: Likewise.
	* ld-mips-elf/mips16-pic-4a.gd: Likewise.
	* ld-mips-elf/multi-got-no-shared.d: Likewise.
	* ld-mips-elf/nan-2008.d: Likewise.
	* ld-mips-elf/nan-legacy.d: Rework test.
	* ld-mips-elf/pic-and-nonpic-3a.gd: Likewise.
	* ld-mips-elf/pic-and-nonpic-3b.gd: Likewise.
	* ld-mips-elf/pic-and-nonpic-5b.gd: Likewise.
	* ld-mips-elf/pic-and-nonpic-6.ld: Likewise.
	* ld-mips-elf/rel32-n32.d: Likewise.
	* ld-mips-elf/rel32-o32.d: Likewise.
	* ld-mips-elf/rel64.d: Likewise.
	* ld-mips-elf/tls-multi-got-1.r: Likewise.
	* ld-elf/group.ld: Discard .MIPS.abiflags and .gnu.attributes.
	* ld-elf/orphan-region.ld: Likewise.
	* ld-elf/orphan.ld: Likewise.
	* ld-mips-elf/compressed-plt-1.ld: Likewise.
	* ld-mips-elf/dyn-sec64.ld: Likewise.
	* ld-mips-elf/got-dump-1.ld: Likewise.
	* ld-mips-elf/got-dump-2.ld: Likewise.
	* ld-mips-elf/got-page-1.ld: Likewise.
	* ld-mips-elf/mips-dyn.ld: Likewise.
	* ld-mips-elf/mips-lib.ld: Likewise.
	* ld-mips-elf/pic-and-nonpic-3a.ld: Likewise.
	* ld-mips-elf/pic-and-nonpic-3b.ld: Likewise.
	* ld-mips-elf/pic-and-nonpic-4b.ld: Likewise.
	* ld-mips-elf/pic-and-nonpic-5b.ld: Likewise.
	* ld-mips-elf/region1.t: Likewise.
	* ld-mips-elf/stub-dynsym-1.ld: Likewise.
	* ld-mips-elf/tls-hidden3.ld: Likewise.
	* ld-mips-elf/vxworks1.ld: Likewise.
	* ld-scripts/overlay-size.t: Likewise.
	* ld-mips-elf/elf-rel-got-n32-embed.d: Remove .MIPS.abiflags from
	objects.
	* ld-mips-elf/elf-rel-got-n32.d: Likewise.
	* ld-mips-elf/elf-rel-got-n64-embed.d: Likewise.
	* ld-mips-elf/elf-rel-got-n64-linux.d: Likewise.
	* ld-mips-elf/elf-rel-got-n64.d: Likewise.
	* ld-mips-elf/elf-rel-xgot-n32.d: Likewise.
	* ld-mips-elf/elf-rel-xgot-n32-embed.d: Likewise.
	* ld-mips-elf/elf-rel-xgot-n64.d: Likewise.
	* ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise.
	* ld-mips-elf/elf-rel-xgot-n64-embed.d: Likewise.
	* ld-mips-elf/mips-elf.exp: Add new tests.
2014-07-29 11:27:59 +01:00
Ilya Tocar
90a915bf0c Add AVX512DQ instructions and their AVX512VL variants.
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512dq, CPU_AVX512DQ_FLAGS.
	* doc/c-i386.texi: Document avx512dq/.avx512dq.

gas/testsuite/

	* gas/i386/avx512dq-intel.d: New.
	* gas/i386/avx512dq.d: New.
	* gas/i386/avx512dq.s: New.
	* gas/i386/avx512dq_vl-intel.d: New.
	* gas/i386/avx512dq_vl.d: New.
	* gas/i386/avx512dq_vl.s: New.
	* gas/i386/i386.exp: Run new AVX-512 tests.
	* gas/i386/x86-64-avx512dq-intel.d: New.
	* gas/i386/x86-64-avx512dq.d: New.
	* gas/i386/x86-64-avx512dq.s: New.
	* gas/i386/x86-64-avx512dq_vl-intel.d: New.
	* gas/i386/x86-64-avx512dq_vl.d: New.
	* gas/i386/x86-64-avx512dq_vl.s: New.

opcodes/

	* i386-dis-evex.h: Updated.
	* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
	PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
	PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
	PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
	PREFIX_EVEX_0F3A67.
	(VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
	VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
	(VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
	EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
	EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
	EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
	EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
	EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
	EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
	(prefix_table): Add entries for new instructions.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(OP_E_memory): Update xmmq_mode handling.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
	(cpu_flags): Add CpuAVX512DQ.
	* i386-init.h: Regenerared.
	* i386-opc.h (CpuAVX512DQ): New.
	(i386_cpu_flags): Add cpuavx512dq.
	* i386-opc.tbl: Add AVX512DQ instructions.
	* i386-tbl.h: Regenerate.
2014-07-22 10:23:49 -07:00
Ilya Tocar
1ba585e8f4 Add support for AVX512BW instructions and their AVX512VL versions.
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS.
	* doc/c-i386.texi: Document avx512bw/.avx512bw.

gas/testsuite/

	* gas/i386/avx512bw-intel.d: New.
	* gas/i386/avx512bw-opts-intel.d: New.
	* gas/i386/avx512bw-opts.d: New.
	* gas/i386/avx512bw-opts.s: New.
	* gas/i386/avx512bw-wig.s: New.
	* gas/i386/avx512bw-wig1-intel.d: New.
	* gas/i386/avx512bw-wig1.d: New.
	* gas/i386/avx512bw.d: New.
	* gas/i386/avx512bw.s: New.
	* gas/i386/avx512bw_vl-intel.d: New.
	* gas/i386/avx512bw_vl-opts-intel.d: New.
	* gas/i386/avx512bw_vl-opts.d: New.
	* gas/i386/avx512bw_vl-opts.s: New.
	* gas/i386/avx512bw_vl-wig.s: New.
	* gas/i386/avx512bw_vl-wig1-intel.d: New.
	* gas/i386/avx512bw_vl-wig1.d: New.
	* gas/i386/avx512bw_vl.d: New.
	* gas/i386/avx512bw_vl.s: New.
	* gas/i386/i386.exp: Run new AVX-512 tests.
	* gas/i386/x86-64-avx512bw-intel.d: New.
	* gas/i386/x86-64-avx512bw-opts-intel.d: New.
	* gas/i386/x86-64-avx512bw-opts.d: New.
	* gas/i386/x86-64-avx512bw-opts.s: New.
	* gas/i386/x86-64-avx512bw-wig.s: New.
	* gas/i386/x86-64-avx512bw-wig1-intel.d: New.
	* gas/i386/x86-64-avx512bw-wig1.d: New.
	* gas/i386/x86-64-avx512bw.d: New.
	* gas/i386/x86-64-avx512bw.s: New.
	* gas/i386/x86-64-avx512bw_vl-intel.d: New.
	* gas/i386/x86-64-avx512bw_vl-opts-intel.d: New.
	* gas/i386/x86-64-avx512bw_vl-opts.d: New.
	* gas/i386/x86-64-avx512bw_vl-opts.s: New.
	* gas/i386/x86-64-avx512bw_vl-wig.s: New.
	* gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New.
	* gas/i386/x86-64-avx512bw_vl-wig1.d: New.
	* gas/i386/x86-64-avx512bw_vl.d: New.
	* gas/i386/x86-64-avx512bw_vl.s: New.

opcodes/

	* i386-dis-evex.h: Add new instructions (prefixes bellow).
	* i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
	(enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
	(PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
	PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
	PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
	PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
	PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
	PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
	PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
	PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
	PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
	PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
	PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
	PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
	PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
	PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
	PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
	PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
	PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
	PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
	PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
	PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
	(VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
	VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
	VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
	VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
	VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
	VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
	VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
	VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
	VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
	VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
	VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
	(VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
	EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
	EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
	EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
	EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
	EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
	EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
	(prefix_table): Add entries for new instructions.
	(vex_table) : Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
	mask_bd_mode handling.
	(OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
	handling.
	(OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
	handling.
	(OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
	(OP_EX): Add dqw_swap_mode handling.
	(OP_VEX): Add mask_bd_mode handling.
	(OP_Mask): Add mask_bd_mode handling.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
	(cpu_flags): Add CpuAVX512BW.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuAVX512BW): New.
	(i386_cpu_flags): Add cpuavx512bw.
	* i386-opc.tbl: Add AVX512BW instructions.
	* i386-tbl.h: Regenerate.
2014-07-22 10:23:44 -07:00
Ilya Tocar
99282af656 Add support for AVX512VL versions of AVX512CD instructions.
gas/testsuite/

	* gas/i386/avx512cd_vl-intel.d: New.
	* gas/i386/avx512cd_vl.d: New.
	* gas/i386/avx512cd_vl.s: New.
	* gas/i386/i386.exp: Run new AVX-512 tests.
	* gas/i386/x86-64-avx512cd_vl-intel.d: New.
	* gas/i386/x86-64-avx512cd_vl.d: New.
	* gas/i386/x86-64-avx512cd_vl.s: New.

opcodes/

	* i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
	* i386-tbl.h: Regenerate.
2014-07-22 10:23:40 -07:00
Ilya Tocar
b28d1bda54 Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512vl, CPU_AVX512VL_FLAGS.
	(build_vex_prefix): Don't abort on VEX.W.
	(check_VecOperands): Support BROADCAST_1TO4 and BROADCAST_1TO2.
	(check_VecOperations): Ditto.
	* doc/c-i386.texi: Document avx512vl/.avx512vl.

gas/testsuite/

	* gas/i386/avx512f_vl-intel.d: New.
	* gas/i386/avx512f_vl-opts-intel.d: New.
	* gas/i386/avx512f_vl-opts.d: New.
	* gas/i386/avx512f_vl-opts.s: New.
	* gas/i386/avx512f_vl-wig.s: New.
	* gas/i386/avx512f_vl-wig1-intel.d: New.
	* gas/i386/avx512f_vl-wig1.d: New.
	* gas/i386/avx512f_vl.d: New.
	* gas/i386/avx512f_vl.s: New.
	* gas/i386/i386.exp: Run new AVX-512 tests.
	* gas/i386/x86-64-avx512f_vl-intel.d: New.
	* gas/i386/x86-64-avx512f_vl-opts-intel.d: New.
	* gas/i386/x86-64-avx512f_vl-opts.d: New.
	* gas/i386/x86-64-avx512f_vl-opts.s: New.
	* gas/i386/x86-64-avx512f_vl-wig.s: New.
	* gas/i386/x86-64-avx512f_vl-wig1-intel.d: New.
	* gas/i386/x86-64-avx512f_vl-wig1.d: New.
	* gas/i386/x86-64-avx512f_vl.d: New.
	* gas/i386/x86-64-avx512f_vl.s: New.

opcodes/

	* i386-dis.c (intel_operand_size): Support 128/256 length in
	vex_vsib_q_w_dq_mode.
	(OP_E_memory): Add ymmq_mode handling, handle new broadcast.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
	(cpu_flags): Add CpuAVX512VL.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuAVX512VL): New.
	(i386_cpu_flags): Add cpuavx512vl.
	(BROADCAST_1TO4, BROADCAST_1TO2): Define.
	* i386-opc.tbl: Add AVX512VL instructions.
	* i386-tbl.h: Regenerate.
2014-07-22 10:23:40 -07:00
Stefan Kristiansson
018dc9bedf or1k: add missing l.msync, l.psync and l.psync instructions.
Even though the opcodes were defined for these instructions,
the actual instruction definitions were lacking.

cpu/
	* or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.

opcodes/
	* or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
	* or1k-opinst.c: Regenerate.
2014-07-20 20:26:09 +03:00
Ilya Tocar
792f7758e3 Fix disasm of vmovsd/vmovss with different length values.
gas/testsuite

	* gas/i386/evex-lig256-intel.d: Updated.
	* gas/i386/evex-lig256.d: Updated.
	* gas/i386/evex-lig512-intel.d: Updated.
	* gas/i386/evex-lig512-intel.d: Updated.
	* gas/i386/x86-64-evex-lig256-intel.d: Updated.
	* gas/i386/x86-64-evex-lig256.d: Updated.
	* gas/i386/x86-64-evex-lig512-intel.d: Updated.
	* gas/i386/x86-64-evex-lig512-intel.d: Updated.

opcodes

	* i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
	(EVEX_W_0F10_P_3_M_1): Fix vmovsd.
2014-07-08 08:07:41 -07:00
Alan Modra
35eafcc71b Rename configure.in to configure.ac
bfd/
	* configure.ac: Rename from configure.in.
	* Makefile.in: Regenerate.
	* config.in: Regenerate.
	* doc/Makefile.in: Regenerate.
opcodes/
	* configure.ac: Rename from configure.in.
	* Makefile.in: Regenerate.
	* config.in: Regenerate.
binutils/
	* configure.ac: Rename from configure.in.
	* Makefile.in: Regenerate.
	* config.in: Regenerate.
	* doc/Makefile.in: Regenerate.
gas/
	* configure.ac: Rename from configure.in.
	* Makefile.in: Regenerate.
	* config.in: Regenerate.
	* doc/Makefile.in: Regenerate.
gprof/
	* configure.ac: Rename from configure.in.
	* configure.ac: Rename from configure.in.
	* Makefile.in: Regenerate.
	* gconfig.in: Regenerate.
ld/
	* configure.ac: Rename from configure.in.
	* Makefile.in: Regenerate.
	* config.in: Regenerate.
2014-07-04 13:40:28 +09:30
Alan Modra
2e98a7bd88 Use modern AC_INIT in configure.in
This removes usage of the obsolete AC_INIT and AM_INIT_AUTOMAKE in all
binutils configure.in files.  The BFD version is now in bfd/version.m4
rather than bfd/configure.in, which allows automake to automatically
track this dependency.

bfd/
	* version.m4: New file.
	* configure.in: Include version.m4.
	(AC_INIT): Update.
	* Makefile.am (RELEASE): Delete.
	(bfdver.h): Depend on development.sh, use instead of RELEASE.
	* Makefile.in: Regenerate.
	* doc/Makefile.in: Regenerate.
opcodes/
	* configure.in: Include bfd/version.m4.
	(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
	(BFD_VERSION): Delete.
	* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
	* configure: Regenerate.
	* Makefile.in: Regenerate.
binutils/
	* configure.in: Include bfd/version.m4.
	(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
	(BFD_VERSION): Delete.
	* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
	* configure: Regenerate.
	* Makefile.in: Regenerate.
	* doc/Makefile.in: Regenerate.
gas/
	* configure.in: Include bfd/version.m4.
	(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
	(BFD_VERSION): Delete.
	* configure.com: Get bfd version from bfd/version.m4.
	* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
	* configure: Regenerate.
	* Makefile.in: Regenerate.
	* doc/Makefile.in: Regenerate.
gprof/
	* configure.in: Include bfd/version.m4.
	(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
	(BFD_VERSION): Delete.
	* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
	* configure: Regenerate.
	* Makefile.in: Regenerate.
ld/
	* configure.in: Include bfd/version.m4.
	(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
	(BFD_VERSION): Delete.
	* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
	* configure: Regenerate.
	* Makefile.in: Regenerate.
2014-07-04 12:41:26 +09:30
Barney Stratford
f36e88862f Add support for the AVR Tiny series of microcontrollers.
* archures.c: add avrtiny architecture for avr target.
	* bfd-in2.h: Regenerate.
	* cpu-avr.c (arch_info_struct): add avrtiny arch info.
	* elf32-avr.c (elf_avr_howto_table): new relocation R_AVR_LDS_STS_16
	added for 16 bit LDS/STS instruction of avrtiny arch.
	(avr_reloc_map): reloc R_AVR_LDS_STS_16 is mapped to
	BFD_RELOC_AVR_LDS_STS_16.
	(bfd_elf_avr_final_write_processing): select machine number avrtiny arch.
	(elf32_avr_object_p): set machine number for avrtiny arch.
	* libbfd.h: Regenerate.
	* reloc.c: Add documentation for BFD_RELOC_AVR_LDS_STS_16 reloc.

         * config/tc-avr.c (mcu_types): Add avrtiny arch.
	Add avrtiny arch devices attiny4, attiny5, attiny9, attiny10, attiny20
	and attiny40.
	(md_show_usage): Add avrtiny arch in usage message.
	(avr_operand): validate and issue error for invalid register for avrtiny.
	add new reloc exp for 16 bit lds/sts instruction.
	(md_apply_fix): check 16 bit lds/sts operand for out of range and encode.
	(md_assemble): check ISA for arch and issue diagnostic.

	* include/elf/avr.h (E_AVR_MACH_AVRTINY): define avrtiny machine number.
	(R_AVR_LDS_STS_16): define 16 bit lds/sts reloc number.
	* include/opcode/avr.h (AVR_ISA_TINY): define avrtiny specific ISA.
	(AVR_ISA_2xxxa): define ISA without LPM.
	(AVR_ISA_AVRTINY): define avrtiny arch ISA.
	Add doc for contraint used in 16 bit lds/sts.
	Adjust ISA group for icall, ijmp, pop and push.
	Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
	* opcodes/avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
	(print_insn_avr): do not select opcode if insn ISA is avrtiny and machine
	is not avrtiny.

	* Makefile.am (ALL_EMULATION_SOURCES): add avrtiny emulation source.
	(eavrtiny.c): add rules for avrtiny emulation source.
	* Makefile.in: Regenerate.
	* configure.tgt: Add avrtiny to avr target emulations.
	* scripttempl/avrtiny.sc: New file.
	linker script template for avrtiny arch.
	* emulparams/avrtiny.sh: New file.
	emulation parameters for avrtiny arch.
2014-07-01 10:20:17 +01:00
Philippe De Muyter
6ddf779d8e Fix a compile time warning on 32-bit hosts.
* or1k-desc.h (spr_field_masks): Add U suffix to the end of long
	constants.
2014-06-26 13:18:04 +01:00
Alan Modra
c151b1c645 Whitespace fixes for cpu/or1k.opc
* or1k.opc: Whitespace fixes.
2014-06-12 12:30:57 +09:30
H.J. Lu
d9949a3673 Only print prefixes before fwait
gas/testsuite/

	* gas/i386/prefix.s: Add another fwait test.
	* gas/i386/prefix.d: Updated.

opcodes/

	* i386-dis.c (fwait_prefix): New.
	(ckprefix): Set fwait_prefix.
	(print_insn): Properly print prefixes before fwait.
2014-06-10 11:16:41 -07:00
Alan Modra
a47622ac1b Allow both signed and unsigned fields in PowerPC cmpli insn
There are legitimate reasons to allow a signed value in a cmpli insn
field, for example to test for a "stw r1,lock@sdarel(r13)" instruction
in user code, a kernel might use
	subis r3,r3,STW_R1_0R13@ha	# subtract off high part
	cmplwi r3,lock@sdarel		# is low part accessing lock?
Since the lock@sdarel may take a range of -32768 to 32767,
the allowed range of cmpli immediate must be at least [-32768,65535].

bfd/
	* elf32-ppc.c (ppc_elf_relocate_section): Treat field of cmpli
	insn as a bitfield; Use complain_overflow_bitfield.
	* elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
opcodes/
	* ppc-opc.c (UISIGNOPT): Define and use with cmpli.
gas/
	* config/tc-ppc.c (ppc_insert_operand): Handle PPC_OPERAND_SIGNOPT
	on unsigned fields.  Comment on PPC_OPERAND_SIGNOPT signed fields
	in 64-bit mode.
gold/
	* powerpc.cc (relocate): Treat field of cmpli insn as a bitfield.
2014-06-07 14:55:11 +09:30
Joel Brobecker
270c993744 Make it easy to make --disable-werror the default for both binutils and gdb
The goal of this patch is to provide an easy way to make
--disable-werror the default when building binutils, or the parts
of binutils that need to get built when building GDB. In development
mode, we want to continue making -Werror the default with GCC.
But, when making releases, I think we want to make it as easy as
possible for regular users to successfully build from sources.

GDB already has this kind of feature to turn -Werror as well as
the use of the libmcheck library. As GDB Release Manager, I take
advantage of it to turn those off after having cut the branch.
I'd like to be able to do the same for the binutils bits. And
perhaps Tristan will want to do the same for his releases too
(not sure, binutils builders might be a little savvier than GDB
builders).

This patch introduces a new file, called development.sh, which
just sets a variable called $development. In our development branches
(Eg. "master"), it's set to true. But setting it to false would allow
us to change the default behavior of various development-related
features to be turned off; in this case, it turns off the use of
-Werror by default (use --enable-werror to turn it back on).

bfd/ChangeLog:

        * development.sh: New file.
        * warning.m4 (AM_BINUTILS_WARNINGS): Source bfd/development.sh.
        Make -Werror the default with GCC only if DEVELOPMENT is true.
        * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add
        $(srcdir)/development.sh.
        * Makefile.in, configure: Regenerate.

binutils/ChangeLog:

        * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
        bfd's development.sh.
        * Makefile.in, configure: Regenerate.

gas/ChangeLog:

        * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
        bfd's development.sh.
        * Makefile.in, configure: Regenerate.

gold/ChangeLog:

        * Makefile.am (CONFIG_STATUS_DEPENDENCIES): New.
        * Makefile.in, configure: Regenerate.

gprof/ChangeLog:

        * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
        bfd's development.sh.
        * Makefile.in, configure: Regenerate.

ld/ChangeLog:

        * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
        bfd's development.sh.
        * Makefile.in, configure: Regenerate.

opcodes/ChangeLog:

        * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
        bfd's development.sh.
        * Makefile.in, configure: Regenerate.

gdb/ChangeLog:

        * development.sh: Delete.
        * Makefile.in (config.status): Adjust dependency on development.sh.
        * configure.ac: Adjust development.sh source call.
        * configure: Regenerate.

gdb/gdbserver/ChangeLog:

        * configure.ac: Adjust development.sh source call.
        * Makefile.in (config.status): Adjust dependency on development.sh.
        * configure: Regenerate.

Tested on x86_64-linux by building two ways: One with DEVELOPMENT
set to true, and one with DEVELOPMENT set to false. In the first
case, I could see the use of -Werror, while it disappeared in
the second case.
2014-06-05 05:47:29 -07:00
Nick Clifton
9f44512958 Fix the disassembly of MSP430 extended index addressing mode.
* msp430-dis.c (msp430_doubleoperand): Use extension_word to
	decide when extended addressing is being used.
2014-06-03 08:54:04 +01:00
Eric Botcazou
ec9a8169c3 This fixes a thinko in the LEON support recently added to the assembler.
opcodes/
	* sparc-opc.c (cas): Disable for LEON.
	(casl): Likewise.
2014-06-02 13:11:17 +02:00
Alan Modra
cdf2a8b762 Remove unnecessary header from m68k-dis.c
* m68k-dis.c: Don't include setjmp.h.
2014-05-20 13:15:18 +09:30
H.J. Lu
df18fdba5d Properly display extra data/address size prefixes
X86 disassembler checks data and address size prefixes when displaying
instruction mnemonic and operands.  For the extra data and address size
prefixes, their names depend only on the address mode, not the data and
address size prefixes.  This patch changes x86 disassembler not to check
the data and address size prefix when printing extra data and address size
prefixes.

gas/testsuite/

	* gas/i386/nops-1-core2.d: Replace data32 with data16.
	* gas/i386/nops-4a-i686.d: Likewise.
	* gas/i386/nops-5-i686.d: Likewise.
	* gas/i386/nops-5.d: Likewise.
	* gas/i386/x86-64-cbw-intel.d: Likewise.
	* gas/i386/x86-64-cbw.d: Likewise.
	* gas/i386/x86-64-io-intel.d: Likewise.
	* gas/i386/x86-64-io-suffix.d: Likewise.
	* gas/i386/x86-64-io.d: Likewise.
	* gas/i386/x86-64-nops-1-core2.d: Likewise.
	* gas/i386/x86-64-nops-1-g64.d: Likewise.
	* gas/i386/x86-64-nops-1-nocona.d: Likewise.
	* gas/i386/x86-64-nops-1.d: Likewise.
	* gas/i386/x86-64-nops-2.d: Likewise.
	* gas/i386/x86-64-nops-3.d: Likewise.
	* gas/i386/x86-64-nops-4-core2.d: Likewise.
	* gas/i386/x86-64-nops-4.d: Likewise.
	* gas/i386/x86-64-nops-5-k8.d: Likewise.
	* gas/i386/x86-64-nops-5.d: Likewise.
	* gas/i386/x86-64-stack-intel.d: Likewise.
	* gas/i386/x86-64-stack-suffix.d: Likewise.
	* gas/i386/x86-64-stack.d: Likewise.
	* gas/i386/ilp32/x86-64-cbw-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-cbw.d: Likewise.
	* gas/i386/ilp32/x86-64-io-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-io-suffix.d: Likewise.
	* gas/i386/ilp32/x86-64-io.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1-core2.d:
	* gas/i386/ilp32/x86-64-nops-1-nocona.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-2.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-3.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-4.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-5.: Likewise.
	* gas/i386/ilp32/x86-64-stack-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-stack-suffix.: Likewise.
	* gas/i386/ilp32/x86-64-stack.d: Likewise.

ld/testsuite/

	* ld-x86-64/tlsbin.dd: Replace data32 with data16.
	* ld-x86-64/tlsdesc-nacl.pd: Likewise.
	* ld-x86-64/tlsgdesc.dd: Likewise.
	* ld-x86-64/tlsld1.dd: Likewise.
	* ld-x86-64/tlsld3.dd: Likewise.
	* ld-x86-64/tlspic.dd: Likewise.

opcodes/

2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (ADDR16_PREFIX): Removed.
	(ADDR32_PREFIX): Likewise.
	(DATA16_PREFIX): Likewise.
	(DATA32_PREFIX): Likewise.
	(prefix_name): Updated.
	(print_insn): Simplify data and address size prefixes processing.
2014-05-09 10:58:00 -07:00
Stefan Kristiansson
999b995ddc or1k: add support for l.swa/l.lwa atomic instructions
This adds support for the load-link/store-conditional
l.lwa/l.swa atomic instructions.
The support is added in such way, that the cpu description not
only describes the mnemonics, but also the functionality.

A couple of fixes to typos in nearby/related code are also snuck
into this.

cpu/
	* or1korbis.cpu (h-atomic-reserve): New hardware.
	(h-atomic-address): Likewise.
	(insn-opcode): Add opcodes for LWA and SWA.
	(atomic-reserve): New operand.
	(atomic-address): Likewise.
	(l-lwa, l-swa): New instructions.
	(l-lbs): Fix typo in comment.
	(store-insn): Clear atomic reserve on store to atomic-address.
	Fix register names in fmt field.

opcodes/
	* or1k-desc.c: Regenerated.
	* or1k-desc.h: Likewise.
	* or1k-opc.c: Likewise.
	* or1k-opc.h: Likewise.
	* or1k-opinst.c: Likewise.
2014-05-08 09:02:50 +03:00
Andrew Bennett
ae52f48306 Add MIPS r3 and r5 support.
This patch firstly adds support for mips32r3 mips32r5, mips64r3
and mips64r5.  Secondly it adds support for the eretnc instruction.

ChangeLog:

bfd/
	* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
	mips32r5 and mips64r5.
	* archures.c (bfd_architecture): Likewise.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (arch_info_struct): Likewise.
	* elfxx-mips.c (mips_set_isa_flags): Likewise.

gas/
	* tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
	and mips64r5.
	(ISA_HAS_64BIT_FPRS): Likewise.
	(ISA_HAS_ROR): Likewise.
	(ISA_HAS_ODD_SINGLE_FPR): Likewise.
	(ISA_HAS_MXHC1): Likewise.
	(hilo_interlocks): Likewise.
	(md_longopts): Likewise.
	(ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
	(ISA_HAS_DROR): Likewise.
	(options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
	OPTION_MIPS64R5.
	(mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
	mips64r5.
	(md_parse_option): Likewise.
	(s_mipsset): Likewise.
	(mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
	and mips64r5.  Also change p5600 entry to be mips32r5.
	* configure.in: Add support for mips32r3, mips32r5, mips64r3 and
	mips64r5.
	* configure: Regenerate.
	* doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
	-mips64r5 command line options.
	* doc/as.texinfo: Likewise.

gas/testsuite/
	* gas/mips/mips.exp: Add MIPS32r5 tests.  Also add the mips32r3,
	mips32r5, mips64r3 and mips64r5 isas to the testsuite.
	* gas/mips/r5.s: New test.
	* gas/mips/r5.d: Likewise.

include/opcode/
	* mips.h (INSN_ISA_MASK): Updated.
	(INSN_ISA32R3): New define.
	(INSN_ISA32R5): New define.
	(INSN_ISA64R3): New define.
	(INSN_ISA64R5): New define.
	(INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
	INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
	(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
	mips64r5.
	(INSN_UPTO32R3): New define.
	(INSN_UPTO32R5): New define.
	(INSN_UPTO64R3): New define.
	(INSN_UPTO64R5): New define.
	(ISA_MIPS32R3): New define.
	(ISA_MIPS32R5): New define.
	(ISA_MIPS64R3): New define.
	(ISA_MIPS64R5): New define.
	(CPU_MIPS32R3): New define.
	(CPU_MIPS32R5): New define.
	(CPU_MIPS64R3): New define.
	(CPU_MIPS64R5): New define.

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
	(I34): New define.
	(I36): New define.
	(I66): New define.
	(I68): New define.
	* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
	mips64r5.
	(parse_mips_dis_option): Update MSA and virtualization support to
	allow mips64r3 and mips64r5.
2014-05-07 11:47:29 +01:00
Andrew Bennett
f7730599d8 Fix an issue with "Rearrange MIPS INSN* masks" patch.
This fixes an issue with Mark Shinwell's "Rearrange MIPS INSN* masks" patch
(https://sourceware.org/ml/binutils/2007-11/msg00231.html).  In the patch
the pref instruction had its membership flags changed from I4|I32|G3 to
I4_32|G3.  Unfortunately G3 was defined as being I4, which made the actual
expanded flags as: I4|I32|I4 and therefore the membership flags should have
been I4_32.  Since the patch was committed G3 was redefined to be I4|EE.  This
fix just removes I4 from G3 making the expanded membership flags for pref as
I4_32|EE.

ChangeLog:

opcodes/
	* mips-opc.c (G3): Remove I4.
2014-05-07 10:44:15 +01:00
H.J. Lu
285ca99246 Properly handle multiple opcode prefixes
This patch updates multiple opcode prefix processing:

1. Always print prefix together with bad opcode.
2. Since the last seen segment register prefix is active, we only print
the active segment register in the memory operand.
3. The 0xf2 and 0xf3 prefixes take precedence over the 0x66 prefix as the
opcode prefix.  Also the last of the 0xf2 and 0xf3 prefixes wins.
4. Ignore invalid 0xf2/0xf3 prefixes if they aren't mandatory.

gas/testsuite/

	PR binutils/16893
	* gas/i386/katmai.d: Expect "gs" as prefix.

	* gas/i386/long-1.s: Replace movapd with movss.
	* gas/i386/x86-64-long-1.s: Likewise.
	* gas/i386/long-1-intel.d: Updated.
	* gas/i386/long-1.d: Likewise.
	* gas/i386/x86-64-long-1-intel.d: Likewise.
	* gas/i386/x86-64-long-1.d: Likewise.

	* gas/i386/prefix.s: Add tests for multiple 0x66, 0x67, 0xf0,
	0xf2 and 0xf3 prefixes.
	* gas/i386/prefix.d: Updated.

opcodes/

	PR binutils/16893
	* i386-dis.c (twobyte_has_mandatory_prefix): New variable.
	(end_codep): Likewise.
	(mandatory_prefix): Likewise.
	(active_seg_prefix): Likewise.
	(ckprefix): Set active_seg_prefix to the active segment register
	prefix.
	(seg_prefix): Removed.
	(get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
	for prefix index.  Ignore the index if it is invalid and the
	mandatory prefix isn't required.
	(print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
	mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
	in used_prefixes here.  Don't print unused prefixes.  Check
	active_seg_prefix for the active segment register prefix.
	Restore the DFLAG bit in sizeflag if the data size prefix is
	unused.  Check the unused mandatory PREFIX_XXX prefixes
	(append_seg): Only print the segment register which gets used.
	(OP_E_memory): Check active_seg_prefix for the segment register
	prefix.
	(OP_OFF): Likewise.
	(OP_OFF64): Likewise.
	(OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
2014-05-05 14:25:14 -07:00
H.J. Lu
8df14d78dc Use sigsetjmp/siglongjmp in opcodes
sigsetjmp/siglongjmp without saving the signal mask is faster than
setjmp/longjmp on systems where the signal mask is saved.  This patch
uses sigsetjmp/siglongjmp without saving the signal mask if possible.

	PR binutils/16886
	* config.in: Regenerated.
	* configure: Likewise.
	* configure.in: Check if sigsetjmp is available.
	* h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
	(print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
	* i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
	(print_insn): Replace setjmp with OPCODES_SIGSETJMP.
	* ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
	(print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
	* sysdep.h (OPCODES_SIGJMP_BUF): New macro.
	(OPCODES_SIGSETJMP): Likewise.
	(OPCODES_SIGLONGJMP): Likewise.
	* vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
	(print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
	* xtensa-dis.c (dis_private): Replace jmp_buf with
	OPCODES_SIGJMP_BUF.
	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
	(print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
	* z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
	(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
	(print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
2014-05-02 08:27:16 -07:00
H.J. Lu
86a80a50f2 Handle prefixes before fwait
0x9b (fwait) is both an instruction and an opcode prefix.  When 0x9b is
treated as an instruction, we need to handle any prefixes before it.
This patch handles it properly.

gas/testsuite/

	PR binutils/16891
	* gas/i386/opcode.s: Add test for fwait with prefix.
	* gas/i386/opcode-intel.d: Updated.
	* gas/i386/opcode-suffix.d: Likewise.
	* gas/i386/opcode.d: Likewise.

opcodes/

	PR binutils/16891
	* i386-dis.c (print_insn): Handle prefixes before fwait.
2014-05-01 09:45:06 -07:00
Alan Modra
a9e18c6a3c Regenerate files for openrisk -> or1k change
bfd/
	* po/SRC-POTFILES.in: Regenerate.
	* configure: Regenerate.
gas/
	* po/POTFILES.in: Regenerate.
opcodes/
	* po/POTFILES.in: Regenerate.
2014-04-26 23:03:04 +09:30
Andrew Bennett
7d64c587c1 Add support for the MIPS eXtended Physical Address (XPA) ASE.
ChangeLog:

binutils/
	* doc/binutils.texi: Document the disassemble MIPS XPA instructions
	command line option.

gas/
	* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
 	(md_longopts): Add xpa and no-xpa command line options.
 	(mips_ases): Add MIPS XPA ASE.
 	(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
 	* doc/as.texinfo: Document the MIPS XPA command line options.
 	* doc/c-mips.texi: Document the MIPS XPA command line options,
 	and assembler directives.

gas/testsuite/
 	* gas/mips/mips.exp: Add xpa tests.
 	* gas/mips/xpa.s: New test.
 	* gas/mips/xpa.d: Likewise.

include/
 	* opcode/mips.h (ASE_XPA): New define.

opcodes/
 	* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 	to allow the MIPS XPA ASE.
 	(parse_mips_dis_option): Process the -Mxpa option.
 	* mips-opc.c (XPA): New define.
 	(mips_builtin_opcodes): Add MIPS XPA instructions and move the
 	locations of the ctc0 and cfc0 instructions.
2014-04-23 13:01:18 +01:00
Christian Svensson
73589c9dbd Remove support for the (deprecated) openrisc and or32 configurations and replace
with support for the new or1k configuration.
2014-04-22 15:57:47 +01:00
Ilya Tocar
2cf200a4c8 Add support for Intel SGX instructions
Add Intel SGX instructions support to assembler and disassembler.

gas/

	* config/tc-i386.c (cpu_arch): Add .se1.
	* doc/c-i386.texi: Document .se1/se1.

gas/testsuite/

	* gas/i386/i386.exp: Run SE1 tests.
	* gas/i386/se1.d: New file.
	* gas/i386/se1.s: Ditto.
	* gas/i386/x86-64-se1.d: Ditto.
	* gas/i386/x86-64-se1.s: Ditto.

opcodes/

	* i386-dis.c (rm_table): Add encls, enclu.
	* i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
	(cpu_flags): Add CpuSE1.
	* i386-opc.h (enum): Add CpuSE1.
	(i386_cpu_flags): Add cpuse1.
	* i386-opc.tbl: Add encls, enclu.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2014-04-04 08:24:47 -07:00
Anthony Green
31c981bc36 Add new sign-extension instructions to moxie port 2014-04-02 20:04:23 -04:00
Yufeng Zhang
76dfed02aa [AArch64 disassembler] Add missing checks of undefine encodings on
st1/st2/st3/st4 instructions.

opcodes/

	* aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
	instructions.

binutils/testsuite/

	* binutils-all/aarch64/aarch64.exp: New test driver for AArch64.
	* binutils-all/aarch64/unallocated-encoding.s: New testcase.
	* binutils-all/aarch64/unallocated-encoding.d: Ditto.
2014-03-26 18:44:27 +00:00
Ilya Tocar
5fc35d961b Fix memory size for gather/scatter instructions
For gathers with indices larger than elements (e. g.)

vpgatherqd      ymm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123]

We currently treat memory size as a size of index register, while it is
actually should be size of destination register:

vpgatherqd      ymm6{k1}, YMMWORD PTR [ebp+zmm7*8-123]

This patch fixes it.

opcodes/

        * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
        vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
        vscatterqps.
        * i386-tbl.h: Regenerate.

gas/testsuite/

        * gas/i386/avx512pf-intel.d: Change memory size for vgatherpf0qps,
        vgatherpf1qps, vscatterpf0qps, vscatterpf1qps.
        * gas/i386/avx512pf.s: Ditto.
        * gas/i386/x86-64-avx512pf-intel.d: Ditto.
        * gas/i386/x86-64-avx512pf.s: Ditto.
        * gas/i386/avx512f-intel.d: Change memory size for vgatherqps,
        vpgatherqd, vpscatterqd, vscatterqps.
        * gas/i386/avx512f.s: Ditto.
        * gas/i386/x86-64-avx512f-intel.d: Ditto.
        * gas/i386/x86-64-avx512f.s: Ditto.
2014-03-20 08:13:30 -07:00
Jose E. Marchesi
ec92c392f7 This patch adds support for the hyperprivileged registers %hstick_offset
and %hstick_enable to the Sparc assembler.

	* config/tc-sparc.c (hpriv_reg_table): Added entries for
	%hstick_offset and %hstick_enable.
	* doc/c-sparc.texi (Sparc-Regs): Document the %hstick_offset and
	%hstick_enable hyperprivileged registers.

	* sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
	%hstick_enable added.

	* gas/sparc/rdhpr.s: Test rd %hstick_offset and %hstick_enable.
	* gas/sparc/rdhpr.d: Likewise.

	* gas/sparc/wrhpr.s: Test wr %hstick_offset and %hstick_enable.
	* gas/sparc/wrhpr.d: Likewise.
2014-03-19 16:43:41 +00:00
Nick Clifton
b41c812c96 Fix typo in changelog entry. 2014-03-19 09:40:21 +00:00
Nick Clifton
b8985e5c0e Fix RX gas testsuite failures by accounting for new variations in the disassembler's output.
* rx-decode.opc (bwl): Allow for bogus instructions with a size
	field of 3.
	(sbwl, ubwl, SCALE): Likewise.
	* rx-decode.c: Regenerate.

	* gas/rx/mov.d: Update expected disassembly.
2014-03-19 09:38:25 +00:00
Alan Modra
fa47fa9246 autoreconf
Regenerate Makefile.in in bfd, binutils, gas, gold, gprof, ld, opcodes.
Regenerate gas/config.in.
2014-03-12 15:02:00 +10:30
Alan Modra
4b95cf5c0c Update copyright years 2014-03-05 22:16:15 +10:30
Richard Sandiford
cd0c81e90f Fix changelog formatting in last commit -- sorry 2014-03-04 21:30:39 +00:00
Richard Sandiford
4ba154f579 bfd/
2014-02-04  Heiher <r@hev.cc>

	* elfxx-mips.c (mips_set_isa_flags): Use E_MIPS_ARCH_64R2 for
	Loongson-3A.
	(mips_mach_extensions): Make bfd_mach_mips_loongson_3a an
	extension of bfd_mach_mipsisa64r2.

opcodes/
2014-02-04  Heiher <r@hev.cc>

	* mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.

gas/
2014-02-04  Heiher <r@hev.cc>

	* config/tc-mips.c (mips_cpu_info_table): Use ISA_MIPS64R2 for
	Loongson-3A.
2014-03-04 21:18:02 +00:00
Richard Sandiford
079b5aec63 opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
	so that they come after the Loongson extensions.
2014-03-04 21:16:38 +00:00
Alan Modra
2c80b75360 Fix various copyright issues
binutils/
	* README: Add "Copyright Notices" paragraph.
gas/
	* config/bfin-lex-wrapper.c: Correct copyright date.
	* config/tc-frv.c: Correct copyright punctuation.
	* config/tc-ip2k.c: Likewise.
	* config/tc-iq2000.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-tic4x.h: Likewise.
ld/testsuite/
	* ld-scripts/phdrs2.exp: Correct copyright punctuation.
	* ld-v850/v850.exp: Correct copyright typo.
opcodes/
	* i386-gen.c (process_copyright): Emit copyright notice on one line.
gold/
	* dwp.cc (print_version): Update copyright year to current.
2014-03-03 11:03:08 +10:30
Alan Modra
b721f1faaf Regenerate opcodes/msp430-decode.c
Cosmetic changes.

	* msp430-decode.c: Regenerate.
2014-02-28 14:35:54 +10:30
Yufeng Zhang
f17c8bfcc8 opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
	FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.

gas/testsuite/

	* gas/aarch64/fp-const0-parsing.s: New test.
	* gas/aarch64/fp-const0-parsing.d: Likewise.
2014-02-27 15:06:56 +00:00
Yufeng Zhang
a58549dda5 opcodes/
* aarch64-opc.c (print_register_offset_address): Call
	get_int_reg_name to prepare the register name.

gas/testsuite/

	* gas/aarch64/ldst-reg-reg-offset.s: Add tests.
	* gas/aarch64/ldst-reg-reg-offset.d: Update.
2014-02-27 14:55:46 +00:00
Ilya Tocar
d6e9dd78c4 Remove bogus vcvtps2ph variant.
We currently support version of vcvtps2ph with sae and only 1 register operand.
This version is encoded as if missing operand was equal to ymm0.
I didn't found any references to this variant in
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
This patch removes it.

opcodes/

        * i386-opc.tbl: Remove wrong variant of vcvtps2ph
        * i386-tbl.h: Regenerate.
2014-02-25 08:52:02 -08:00
Ilya Tocar
dcf893b581 Add support for CPUID PREFETCHWT1
Latest AVX512 spec
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
Has CPUID PREFETCHWT1 for prefetchwt1 instruction, which we list as AVX512PF.
This patch introduces CPUID PREFETCHWT1.

gas/

        * config/tc-i386.c (cpu_arch): Add .prefetchwt1.
        * doc/c-i386.texi: Document .prefetchwt1/prefetchwt1.

opcodes/

        * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
        (cpu_flags): Add CpuPREFETCHWT1.
        * i386-init.h: Regenerate.
        * i386-opc.h (CpuPREFETCHWT1): New.
        (i386_cpu_flags): Add cpuprefetchwt1.
        * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
        * i386-tbl.h: Regenerate.

gas/testsuite

        * gas/i386/avx512pf-intel.d: Remove prefetchwt1.
        * gas/i386/avx512pf.s: Ditto.
        * gas/i386/avx512pf.d: Ditto.
        * gas/i386/x86-64-avx512pf-intel.d: Ditto.
        * gas/i386/x86-64-avx512pf.s: Ditto.
        * gas/i386/x86-64-avx512pf.d: Ditto.
        * gas/i386/prefetchwt1-intel.d: New file.
        * gas/i386/prefetchwt1.s: Ditto.
        * gas/i386/prefetchwt1.d: Ditto.
        * gas/i386/x86-64-prefetchwt1-intel.d: Ditto.
        * gas/i386/x86-64-prefetchwt1.s: Ditto.
        * gas/i386/x86-64-prefetchwt1.d: Ditto.
2014-02-21 08:04:00 -08:00
Ilya Tocar
957d095533 Change cpu for vptestnmd and vptestnmq instructions.
In latest release of AVX512 spec
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
Vptestnmq and vptestnmq instructions have CPUID AVX512F, not AVX512CD.
This patch fixes it.

opcodes/

        * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
        to CpuAVX512F.
        * i386-tbl.h: Regenerate.

gas/testsuite/

        * gas/i386/avx512cd-intel.d: Remove vptestnmq, vptestnmd.
        * gas/i386/avx512cd.s: Ditto.
        * gas/i386/avx512cd.d: Ditto.
        * gas/i386/x86-64-avx512cd-intel.d: Ditto.
        * gas/i386/x86-64-avx512cd.s: Ditto.
        * gas/i386/x86-64-avx512cd.d: Ditto.
        * gas/i386/avx512f-intel.d: Add vptestnmq, vptestnmd.
        * gas/i386/avx512f.s: Ditto.
        * gas/i386/avx512f.d: Ditto.
        * gas/i386/x86-64-avx512f-intel.d: Ditto.
        * gas/i386/x86-64-avx512f.s: Ditto.
        * gas/i386/x86-64-avx512f.d: Ditto.
2014-02-20 07:53:55 -08:00
H.J. Lu
10632b7999 Don't output trailing space
* i386-gen.c (output_cpu_flags): Don't output trailing space.
	(output_opcode_modifier): Likewise.
	(output_operand_type): Likewise.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2014-02-19 12:53:27 -08:00
Ilya Tocar
963f35869d Add clflushopt, xsaves, xsavec, xrstors
gas/

2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>

	* config/tc-i386.c (cpu_arch): Add .clflushopt, .xsavec, .xsaves.
	* doc/c-i386.texi: Document .xsavec/xsavec/.xsaves/xsaves/
	clflushopt/.clfushopt.

gas/testsuite/

2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>

	* gas/i386/clflushopt-intel.d: New.
	* gas/i386/clflushopt.d: Ditto.
	* gas/i386/clflushopt.s: Ditto.
	* gas/i386/i386.exp: Run new tests.
	* gas/i386/x86-64-clflushopt-intel.d: New.
	* gas/i386/x86-64-clflushopt.d: Ditto.
	* gas/i386/x86-64-clflushopt.s: Ditto.
	* gas/i386/x86-64-xsavec-intel.d: Ditto.
	* gas/i386/x86-64-xsavec.d: Ditto.
	* gas/i386/x86-64-xsavec.s: Ditto.
	* gas/i386/x86-64-xsaves-intel.d: Ditto.
	* gas/i386/x86-64-xsaves.d: Ditto.
	* gas/i386/x86-64-xsaves.s: Ditto.
	* gas/i386/xsavec-intel.d: Ditto.
	* gas/i386/xsavec.d: Ditto.
	* gas/i386/xsavec.s: Ditto.
	* gas/i386/xsaves-intel.d: Ditto.
	* gas/i386/xsaves.d: Ditto.
	* gas/i386/xsaves.s: Ditto.

opcodes/

2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>

	* i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
	MOD_0FC7_REG_5.
	(PREFIX enum): Add PREFIX_0FAE_REG_7.
	(reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
	(prefix_table): Add clflusopt.
	(mod_table): Add xrstors, xsavec, xsaves.
	* i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
	CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
	(cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
	* i386-init.h: Regenerate.
	* i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
	xsaves64, xsavec, xsavec64.
	* i386-tbl.h: Regenerate.
2014-02-12 07:50:24 -08:00
Alan Modra
c1c69e839e binutils potfiles regen
Adds nds32 files to POTFILES.in
2014-02-10 09:59:35 +10:30
Michael Zolotukhin
eaa9d1ad0e Fix shift for AVX512F gather/scatter instructions
opcodes/

2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
	    Jan Beulich  <jbeulich@suse.com>

	PR binutils/16490
	* i386-dis.c (OP_E_memory): Fix shift computation for
	vex_vsib_q_w_dq_mode.

gas/testsuite/

2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
	    Jan Beulich  <jbeulich@suse.com>

	PR binutils/16490
	* gas/i386/avx512f.d: Fix test output.
	* gas/i386/avx512f-intel.d: Likewise.
	* gas/i386/x86-64-avx512f.d: Likewise.
	* gas/i386/x86-64-avx512f-intel.d: Likewise.
2014-01-30 07:38:09 -08:00
Roland McGrath
e2e6193d65 Fix buffer underrun in i386-dis.c.
opcodes/
	* i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
	last_rex_prefix is -1.
2014-01-09 11:22:59 -08:00
H.J. Lu
221fd5d598 Update copyright year to 2014
binutils/

	* version.c (print_version): Update copyright year to 2014.

gas/

	* as.c (parse_args): Update copyright year to 2014.

gold/

	* version.cc (print_version): Update copyright year to 2014.

ld/

	* ldver.c (ldversion): Update copyright year to 2014.

opcodes/

	* i386-gen.c (process_copyright): Update copyright year to 2014.
2014-01-08 05:48:12 -08:00
H.J. Lu
5fb776a637 New Year - binutils ChangeLog rotation 2014-01-08 05:32:12 -08:00
Maciej W. Rozycki
b0b0c9fc49 * nds32-asm.c (parse_operand): Fix out-of-range integer constant. 2014-01-06 10:44:23 +08:00
Kuan-Lin Chen
6b9d3259c3 Add system register and embedded debug register support.
Add two more as test files for user special and system register.
Fix typo.

2013-12-17  Kuan-Lin Chen  <kuanlinchentw@gmail.com>

	* gas/nds32/nds32.exp: Add system and user special register tests.
	* gas/nds32/sys-reg.s: New test.
	* gas/nds32/sys-reg.d: Likewise.
	* gas/nds32/usr-spe-reg.s: Likewise.
	* gas/nds32/usr-spe-reg.d: Likewise.
	* gas/nds32/alu-2.d: Delete the new blank line at EOF.
	* gas/nds32/br-1.d: Likewise.
	* gas/nds32/br-2.d: Likewise.
	* gas/nds32/ji-jr.d: Likewise.
	* gas/nds32/lsi.d: Likewise.
	* nds32-dis.c (sr_map): Add system register table for disassembling.
	(usr_map): Fix typo.
	* nds32-asm.c (keyword_sr): Add embedded debug registers.
2013-12-18 11:02:12 +08:00
Michael Zolotukhin
4a357820ad Properly handle ljmp/lcall with invalid MODRM byte
gas/testsuite/

2013-12-17  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>

	* gas/i386/disassem.s: New.
	* gas/i386/disassem.d: Likewise.
	* gas/i386/x86-64-disassem.s: Likewise.
	* gas/i386/x86-64-disassem.d: Likewise.
	* gas/i386/i386.exp: Run disassem and x86-64-disassem.

opcodes/

2013-12-17  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>

	* i386-dis.c (MOD_FF_REG_3): New.
	(MOD_FF_REG_5): Likewise.
	(mod_table): Add MOD_FF_REG_3 and MOD_FF_REG_5.
	(reg_table): Use MOD_FF_REG_3 and MOD_FF_REG_5.
2013-12-17 09:06:57 -08:00
Andrew Bennett
dc76d75756 Add support to show the symbolic names of the MIPS CP1 registers.
2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>

	gas/testsuite/gas/mips/
	* mips.exp: Add CP1 register name tests.
	* cp1-names-mips32.d: New test.
	* cp1-names-mips32r2.d: New test.
	* cp1-names-mips64.d: New test.
	* cp1-names-mips64r2.d: New test.
	* cp1-names-numeric.d: New test.
	* cp1-names-r3000.d: New test.
	* cp1-names-r4000.d: New test.
	* cp1-names-sb1.d: New test.
	* cp1-names.s: New test.
	* micromips-insn32.d: Add the correct symbolic names for the CP1
	registers.
	* micromips-noinsn32.d: Likewise.
	* micromips-trap.d: Likewise.
	* micromips.d: Likewise.

	opcodes/
	* mips-dis.c: Add mips_cp1_names pointer.
	(mips_cp1_names_numeric): New array.
	(mips_cp1_names_mips3264): New array.
	(mips_arch_choice): Add cp1_names.
	(mips_arch_choices): Add relevant cp1 register name array to each of
	the elements.
	(set_default_mips_dis_options): Add support for setting up the
	mips_cp1_names pointer.
	(parse_mips_dis_option): Add support for the cp1-names command line
	variable.  Also setup the mips_cp1_names pointer.
	(print_reg): Print out name of the cp1 register.
2013-12-16 17:09:58 +00:00
Andrew Bennett
e269fea784 Range of element index is too large on MIPS MSA element selection instructions.
The element index range for the following MIPS MSA instructions: sldi, splati,
copy_s, copy_u, insert and insve is 1 bit too large.  This patch fixes this issue.

ChangeLog:

	gas/testsuite/gas/mips/
	* msa.s: Reduced maximum element index range for sldi, splati,
	copy_s, copy_u, insert and insve instructions.
	* msa64.s: Likewise.
	* micromips@msa.d: Likewise.
	* micromips@msa64.d: Likewise.
	* msa.d: Likewise.
	* msa64.d: Likewise.

	include/opcode/
	* mips.h: Updated description of +o, +u, +v and +w for MIPS and
	microMIPS.

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
	+v and +w.
	(micromips_opcodes): Reduced element index range for sldi, splati,
	copy_s, copy_u, insert and insve instructions.
	* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
	+v and +w.
	(mips_builtin_opcodes): Reduced element index range for sldi, splati,
	copy_s, copy_u, insert and insve instructions.
2013-12-16 07:43:20 -08:00
Jan-Benedict Glaw
1332de018c 2013-12-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>
* nds32-dis.c (mnemonic_96): Fix typo.

[BR]: https://sourceware.org/ml/binutils/2013-12/msg00184.html
2013-12-13 17:43:59 +01:00
Kuan-Lin Chen
35c081572f Add support for Andes NDS32:
BFD:
	* Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Add nds32
	files.
	* Makefile.in: Regenerate.
	* archures.c (bfd_nds32_arch): Add nds32 target.
	* bfd-in2.h: Regenerate.
	* config.bfd (nds32*le-*-linux): Add bfd_elf32_nds32lelin_vec
	and bfd_elf32_nds32belin_vec.
	(nds32*be-*-linux*): Likewise.
	(nds32*le-*-*): Add bfd_elf32_nds32le_vec and bfd_elf32_nds32be_vec.
	(nds32*be-*-*): Likewise.
	* configure.in (bfd_elf32_nds32be_vec): Add elf32-nds32.lo.
	(bfd_elf32_nds32le_vec): Likewise.
	(bfd_elf32_nds32belin_vec): Likewise.
	(bfd_elf32_nds32lelin_vec): Likewise.
	* configure: Regenerate.
	* cpu-nds32.c: New file for nds32.
	* elf-bfd.h: Add NDS32_ELF_DATA.
	* elf32-nds32.c: New file for nds32.
	* elf32-nds32.h: New file for nds32.
	* libbfd.h: Regenerate.
	* reloc.c: Add relocations for nds32.
	* targets.c (bfd_elf32_nds32be_vec): New declaration for nds32.
	(bfd_elf32_nds32le_vec): Likewise.
	(bfd_elf32_nds32belin_vec): Likewise.
	(bfd_elf32_nds32lelin_vec): Likewise.

BINUTILS:
	* readelf.c: Include elf/nds32.h
	(guess_is_rela): Add case for EM_NDS32.
	(dump_relocations): Add case for EM_NDS32.
	(decode_NDS32_machine_flags): New.
	(get_machine_flags): Add case for EM_NDS32.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(process_nds32_specific): New.
	(process_arch_specific): Add case for EM_NDS32.
	* NEWS: Announce Andes nds32 support.
	* MAINTAINERS: Add nds32 maintainers.
  TESTSUITE:
	* binutils-all/objdump.exp: Add NDS32 cpu.
	* binutils-all/readelf.r: Skip extra reloc created by NDS32.

GAS:
	* Makefile.am (TARGET_CPU_CFILES): Add config/tc-nds32.c.
	(TARGET_CPU_HFILES): Add config/tc-nds32.h.
	* Makefile.in: Regenerate.
	* configure.in (nds32): Add nds32 target extension config support.
	* configure.tgt : Add case for nds32-*-elf* and nds32-*-linux*.
	* configure: Regenerate.
	* config/tc-nds32.c: New file for nds32.
	* config/tc-nds32.h: New file for nds32.
	* doc/Makefile.am (CPU_DOCS): Add c-nds32.texi.
	* doc/Makefile.in: Regenerate.
	* doc/as.texinfo: Add nds32 options.
	* doc/all.texi: Set NDS32.
	* doc/c-nds32.texi: New file dor nds32 document.
	* NEWS: Announce Andes nds32 support.
  TESTSUITE:
	* gas/all/gas.exp: Add expected failures for NDS32.
	* gas/elf/elf.exp: Likewise.
	* gas/lns/lns.exp: Use alternate test.
	* gas/macros/irp.d: Skip for NDS32.
	* gas/macros/macros.exp: Skip some tests for the NDS32.
	* gas/macros/rept.d: Skip for NDS32.
	* gas/macros/test3.d: Skip for NDS32.
	* gas/nds32: New directory.
	* gas/nds32/alu-1.s: New test.
	* gas/nds32/alu-1.d: Likewise.
	* gas/nds32/alu-2.s: Likewise.
	* gas/nds32/alu-2.d: Likewise.
	* gas/nds32/br-1.d: Likewise.
	* gas/nds32/br-1.s: Likewise.
	* gas/nds32/br-2.d: Likewise.
	* gas/nds32/br-2.s: Likewise.
	* gas/nds32/ji-jr.d: Likewise.
	* gas/nds32/ji-jr.s: Likewise.
	* gas/nds32/ls.d: Likewise.
	* gas/nds32/ls.s: Likewise.
	* gas/nds32/lsi.d: Likewise.
	* gas/nds32/lsi.s: Likewise.
	* gas/nds32/to-16bit-v1.d: Likewise.
	* gas/nds32/to-16bit-v1.s: Likewise.
	* gas/nds32/to-16bit-v2.d: Likewise.
	* gas/nds32/to-16bit-v2.s: Likewise.
	* gas/nds32/to-16bit-v3.d: Likewise.
	* gas/nds32/to-16bit-v3.s: Likewise.
	* gas/nds32/nds32.exp: New test driver.

LD:
	* Makefile.am (ALL_EMULATION_SOURCES): Add nds32 target.
	* Makefile.in: Regenerate.
	* configure.tgt: Add case for nds32*le-*-elf*, nds32*be-*-elf*,
	nds32*le-*-linux-gnu*, and nds32*be-*-linux-gnu*.
	* emulparams/nds32belf.sh: New file for nds32.
	* emulparams/nds32belf_linux.sh: Likewise.
	* emulparams/nds32belf16m.sh: Likewise.
	* emulparams/nds32elf.sh: Likewise.
	* emulparams/nds32elf_linux.sh: Likewise.
	* emulparams/nds32elf16m.sh: Likewise.
	* emultempl/nds32elf.em: Likewise.
	* scripttempl/nds32elf.sc}: Likewise.
	* gen-doc.texi: Set NDS32.
	* ld.texinfo: Set NDS32.
	* NEWS: Announce Andes nds32 support.
  TESTSUITE:
	* lib/ld-lib.exp: Add NDS32 to list of targets that do not support
	shared library generation.
	* ld-nds32: New directory.
	* ld-nds32/branch.d: New test.
	* ld-nds32/branch.ld: New test.
	* ld-nds32/branch.s: New test.
	* ld-nds32/diff.d: New test.
	* ld-nds32/diff.ld: New test.
	* ld-nds32/diff.s: New test.
	* ld-nds32/gp.d: New test.
	* ld-nds32/gp.ld: New test.
	* ld-nds32/gp.s: New test.
	* ld-nds32/imm.d: New test.
	* ld-nds32/imm.ld: New test.
	* ld-nds32/imm.s: New test.
	* ld-nds32/imm_symbol.s: New test.
	* ld-nds32/relax_jmp.d: New test.
	* ld-nds32/relax_jmp.ld: New test.
	* ld-nds32/relax_jmp.s: New test.
	* ld-nds32/relax_load_store.d: New test.
	* ld-nds32/relax_load_store.ld: New test.
	* ld-nds32/relax_load_store.s: New test.
	* ld-nds32/nds32.exp: New file.

OPCODES:
	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
	and nds32-dis.c.
	* Makefile.in: Regenerate.
	* configure.in: Add case for bfd_nds32_arch.
	* configure: Regenerate.
	* disassemble.c (ARCH_nds32): Define.
	* nds32-asm.c: New file for nds32.
	* nds32-asm.h: New file for nds32.
	* nds32-dis.c: New file for nds32.
	* nds32-opc.h: New file for nds32.

INCLUDE:
	* dis-asm.h (print_insn_nds32): Add nds32 target.
	* elf/nds32.h: New file for nds32.
	* opcode/nds32.h: New file for nds32.
2013-12-13 11:52:32 +00:00
Nick Clifton
61d4014c3c * s390-mkopc.c (dumpTable): Provide a format string to printf so
that compiling with -Werror=format-security does not produce an
	error.
2013-12-05 13:36:17 +00:00
Yufeng Zhang
87b8eed7fb gas/testsuite/
* gas/aarch64/msr.s: Add tests.
	* gas/aarch64/msr.d: Update.

include/opcode

	* aarch64.h (aarch64_pstatefields): Change element type to
	aarch64_sys_reg.

opcodes/

	* aarch64-opc.c (aarch64_pstatefields): Update.
2013-11-20 11:22:53 +00:00
Catherine Moore
8f8c3854e0 2013-11-19 Catherine Moore <clm@codesourcery.com>
* micromips-opc.c (LM): Define.
	(micromips_opcodes): Add LM to load instructions.
	* mips-opc.c (prefe): Add LM attribute.
2013-11-19 05:25:32 -08:00
Yufeng Zhang
a203d9b72f Revert "Add support for AArch64 trace unit registers."
This reverts commit 75468c93c1.
2013-11-18 11:42:41 +00:00
Yufeng Zhang
75468c93c1 gas/
* config/tc-aarch64.c (set_other_error): New function.
	(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
	the variable to which it points with 'o'.
	(parse_operands): Update; check for write to read-only system
	registers or read from write-only ones.

gas/testsuite/

	* gas/aarch64/diagnostic.s: Add tests.
	* gas/aarch64/diagnostic.l: Update.
	* gas/aarch64/tracereg-illegal.d: New file.
	* gas/aarch64/tracereg-illegal.l: Ditto.
	* gas/aarch64/tracereg-illegal.s: Ditto.
	* gas/aarch64/tracereg.d: Ditto.
	* gas/aarch64/tracereg.s: Ditto.

include/opcode

	* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
	(aarch64_sys_reg_writeonly_p): Ditto.

opcodes/

	* aarch64-opc.c (CPENT): New define.
	(F_READONLY, F_WRITEONLY): Likewise.
	(aarch64_sys_regs): Add trace unit registers.
	(aarch64_sys_reg_readonly_p): New function.
	(aarch64_sys_reg_writeonly_p): Ditto.
2013-11-15 23:40:34 +00:00
Maciej W. Rozycki
caeba11c83 MIPS/opcodes: Add MFCR and MTCR data dependencies
* mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
	"mtcr".
2013-11-15 21:57:11 +00:00
Catherine Moore
b83a9376e9 Fix ChangeLog entries from earlier commit. 2013-11-11 15:34:48 -08:00
H.J. Lu
d56da83e58 Remove CpuNop from CPU_K6_2_FLAGS
PR gas/16140
	* i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
	* i386-init.h: Regenerated.
2013-11-08 09:42:08 -08:00
Yufeng Zhang
49eec19300 gas/
* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg;
	call aarch64_sys_reg_deprecated_p and warn about the deprecated
	system registers.

gas/testsuite/

	* gas/aarch64/deprecated.d: New file.
	* gas/aarch64/deprecated.l: New file.
	* gas/aarch64/deprecated.s: New file.
	* gas/aarch64/sysreg-1.s: Add tests.
	* gas/aarch64/sysreg-1.d: Add tests.

include/opcode/

	* aarch64.h (aarch64_sys_reg): New typedef.
	(aarch64_sys_regs): Change to define with the new type.
	(aarch64_sys_reg_deprecated_p): Declare.

opcodes/

	* aarch64-opc.c (F_DEPRECATED): New macro.
	(aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
	F_DEPRECATED.
	(aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
	AARCH64_OPND_SYSREG.
2013-11-05 20:54:22 +00:00
Yufeng Zhang
68a6428382 gas/
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1.

gas/testsuite/

	* gas/aarch64/alias.s: Add tests.
	* gas/aarch64/alias.d: Update.
	* gas/aarch64/no-aliases.d: Update.
	* gas/aarch64/diagnostic.s: Add tests.
	* gas/aarch64/diagnostic.l: Update.
	* gas/aarch64/illegal.s: Add tests.
	* gas/aarch64/illegal.l: Update.

include/opcode/

	* aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
	(enum aarch64_opnd): Add AARCH64_OPND_COND1.

opcodes/

	* aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
	(convert_from_csel): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Handle
	AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
	(aarch64_print_operand): Handle AARCH64_OPND_COND1.
	* aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
	COND for cinc, cset, cinv, csetm and cneg.
	(AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
	* aarch64-asm-2.c: Re-generated.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.
2013-11-05 20:50:18 +00:00
Yufeng Zhang
4e50d5f863 opcodes/
* aarch64-opc.c (set_syntax_error): New function.
	(operand_general_constraint_met_p): Replace set_other_error
	with set_syntax_error.

gas/testsuite/

	* gas/aarch64/diagnostic.s: Add tests of ldp/stp.
	* gas/aarch64/diagnostic.l: Update.
2013-11-05 20:46:24 +00:00
Andreas Arnez
7d4a7d107a S/390: Disassemble 31-bit binaries with "zarch" opcode set by default
Currently the disassembler for s390 (by default) assumes that a 31-bit
binary was compiled in "ESA" mode -- and then only disassembles a
limited opcode set.  The change upgrades the default to the full "zarch"
opcode set even for 31-bit binaries.

opcodes/
	* s390-dis.c (init_disasm): Default to full 'zarch' opcode
	availability even for 31-bit programs.
2013-10-30 18:04:32 +01:00
Ramana Radhakrishnan
8518117318 Fix neon vshll disassembly.
opcodes/
2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* arm-dis.c (neon_opcodes): Adjust print string for vshll.

gas/testsuite/
2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gas/arm/neon-cov.d: Adjust output.
2013-10-15 13:30:40 +00:00
Chao-ying Fu
4edbb8e35a 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
	+d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
	+~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
	(MSA): New define.
	(MSA64): New define.
	(micromips_opcodes): Add MSA instructions.
	* mips-dis.c (msa_control_names): New array.
	(mips_abi_choice): Add ASE_MSA to mips32r2.
	Remove ASE_MDMX from mips64r2.
	Add ASE_MSA and ASE_MSA64 to mips64r2.
	(parse_mips_dis_option): Handle -Mmsa.
	(print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
	(print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
	(print_mips_disassembler_options): Print -Mmsa.
	* mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
	+l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
	(MSA): New define.
	(MSA64): New define.
	(mips_builtin_op): Add MSA instructions.
2013-10-14 18:58:15 +00:00
Sandra Loosemore
ae335a4e26 2013-10-13 Sandra Loosemore <sandra@codesourcery.com>
opcodes/
	* nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
	as the primary name of r30.

	gas/
	* config/tc-nios2.c (nios2_consume_arg): Make the "ba" warning
	also test/refer to "sstatus".  Reformat the warning message.

	gas/testsuite/
	* gas/nios2/warn_nobreak.l: Update text of warning messages.
	* gas/nios2/registers.s: Use "sstatus" rather than "ba"
	as the primary name of r30.
	* gas/nios2/registers.d: Likewise.
2013-10-14 00:42:28 +00:00
H.J. Lu
6c75cc62a3 Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn
gas/testsuite/

	* gas/i386/mpx.s: Remove bndcl/bndcu/bndcn tests with AX.
	* gas/i386/x86-64-mpx.s: Likwise.

	* gas/i386/mpx.d: Updated.
	* gas/i386/x86-64-mpx.d: Likewise.

opcodes/

	* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
	default case.
	(OP_E_register): Move v_bnd_mode alongside m_mode.
	* i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
	Drop Reg16 and Disp16. Add NoRex64.
	(bndmk, bndmov, bndldx, bndstx): Drop Disp16.
	* i386-tbl.h: Re-generate.
2013-10-12 15:57:07 +00:00
Sean Keys
0e1c243401 * Removed short_hand field from opcode table and
refactored assembler/disassember accordingly.
     Testsuite checkout OK.
2013-10-11 04:55:42 +00:00
Roland McGrath
9ce09ba2d7 opcodes/
* i386-dis.c (oappend_maybe_intel): New function.
	(OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
	(OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
	(VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
2013-10-11 00:58:29 +00:00
Roland McGrath
2b4e983c39 opcodes/
* cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
	possible compiler warnings when the union's initializer is
	actually meant for the 'preg' enum typed member.
	* crx-opc.c (REG): Likewise.
2013-10-10 17:43:37 +00:00
Roland McGrath
7903e53098 opcodes/
* v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
	Remove duplicate const qualifier.
2013-10-10 17:19:49 +00:00
Jan Beulich
79e0e31dc9 opcodes/
2013-10-08  Jan Beulich <jbeulich@suse.com>

	* i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
	(clflush): Use Anysize instead of Byte|Unspecified.
	(prefetch*): Likewise.
	* i386-tbl.h: Re-generate.
2013-10-08 15:12:59 +00:00
Chao-ying Fu
45099dfad2 2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
2013-10-07 18:02:47 +00:00
H.J. Lu
916fae9135 Add Size64 to movq/vmovq with Reg64 operand
* i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
	* i386-init.h: Regenerated.
2013-09-30 17:48:11 +00:00
Saravanan Ekanathan
c7b0bd56ce Add AMD bdver4 support.
gas/
	* config/tc-i386.c (cpu_arch): Add CPU_BDVER4_FLAGS.
	* doc/c-i386.texi: Add -march=bdver4 option.

gas/testsuite/
	* gas/i386/i386.exp: Run bdver4 test cases.
	* gas/i386/nops-1-bdver4.d: New.
	* gas/i386/arch-10-bdver4.d: New.
	* gas/i386/x86-64-nops-1-bdver4.d: New.
	* gas/i386/x86-64-arch-2-bdver4.d: New.

opcodes/
	* i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
	* i386-init.h: Regenerated.
2013-09-30 17:02:07 +00:00
Alan Modra
cc9afea3e4 * libtool.m4 (_LT_ENABLE_LOCK <ld -m flags>): Remove non-canonical
ppc host match.  Support little-endian powerpc linux hosts.
Regenerate binutils configure files.
2013-09-20 09:51:25 +00:00
Richard Sandiford
e3f9e85275 opcodes/
* s390-opc.txt (clih): Make the immediate unsigned.

gas/testsuite/
	* gas/s390/zarch-z196.s, gas/s390/zarch-z196.d: Test CLIH with
	4000000000.
2013-09-17 09:02:37 +00:00
Nick Clifton
74db7efbe3 PR gas/15914
* config/tc-arm.c (T16_32_TAB): Add _udf.
	(do_t_udf): New function.
	(insns): Add "udf".

	* gas/arm/udf-bad.s: New file.
	* gas/arm/udf-bad.d: New file.
	* gas/arm/udf-bad.l: New file.
	* gas/arm/udf.s: New file.
	* gas/arm/udf.d: New file.
	* gas/arm/udf.l: New file.

	* arm-dis.c (arm_opcodes): Add udf.
	(thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
	(thumb32_opcodes): Add udf.w.
	(print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
2013-09-04 07:59:33 +00:00
Andreas Krebbel
c8094e012c 2013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
	For the load fp integer instructions only the suppression flag was
	new with z196 version.
2013-09-02 11:42:38 +00:00
Nick Clifton
7e10503172 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
immediate is not suitable for the 32-bit ABI.

	* gas/aarch64/illegal.s: Add illegal constant for logical
	operation.
	* gas/aarch64/illegal.l: Add expected error message.
2013-08-28 10:25:36 +00:00
Maciej W. Rozycki
fb6f389526 opcodes/
* micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
	replacing NODS.

	gas/testsuite/
	* gas/testsuite/gas/mips/micromips-insn32.d: Adjust for delay
	slot scheduling of ALNV.PS.
	* gas/testsuite/gas/mips/micromips-noinsn32.d: Likewise.
	* gas/testsuite/gas/mips/micromips-trap.d: Likewise.
	* gas/testsuite/gas/mips/micromips.d: Likewise.
	* gas/testsuite/gas/mips/micromips@alnv_ps-swap.d: Likewise.
2013-08-23 14:12:59 +00:00
Nick Clifton
9aff4b7ac1 PR binutils/15834
Fix typos:
---
 bfd/bfdio.c                                  |  2 +-
 bfd/elf32-spu.c                              |  2 +-
 bfd/elfnn-aarch64.c                          |  2 +-
 binutils/od-xcoff.c                          |  2 +-
 config/tcl.m4                                |  2 +-
 gas/config/tc-ia64.c                         |  2 +-
 gas/config/tc-sparc.c                        |  2 +-
 gas/config/tc-z80.c                          | 12 ++++++------
 gas/doc/c-i386.texi                          |  6 +++---
 gas/doc/c-m32r.texi                          |  2 +-
 gas/testsuite/gas/d10v/instruction_packing.d |  2 +-
 gas/testsuite/gas/z80/atend.d                |  2 +-
 gold/object.h                                |  2 +-
 include/gdb/remote-sim.h                     |  2 +-
 include/opcode/ChangeLog                     |  2 +-
 include/opcode/i960.h                        |  2 +-
 ld/testsuite/ld-mips-elf/mips16-pic-1.inc    |  2 +-
 opcodes/aarch64-asm.c                        |  2 +-
 opcodes/aarch64-dis.c                        |  2 +-
 opcodes/msp430-dis.c                         |  2 +-
2013-08-23 07:54:19 +00:00
Richard Sandiford
5e0dc5bae9 include/opcode/
* mips.h (M_DEXT, M_DINS): Delete.

opcodes/
	* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
	macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
	Use +H rather than +C for the real "dext".
	* mips-opc.c (mips_builtin_opcodes): Likewise.

gas/
	* config/tc-mips.c (report_bad_range, report_bad_field): Delete.
	(macro): Remove M_DEXT and M_DINS handling.

gas/testsuite/
	* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
	error messages to have the same form as the EXT and INS ones.
	* gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d,
	gas/mips/micromips-trap.d, gas/mips/micromips.d,
	gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect
	"dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
2013-08-19 19:54:41 +00:00
Richard Sandiford
0f35dbc4d9 include/opcode/
* mips.h (OP_OPTIONAL_REG): New mips_operand_type.
	(mips_optional_operand_p): New function.

opcodes/
	* mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
	* micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
	and OPTIONAL_MAPPED_REG.
	* mips-opc.c (decode_mips_operand): Likewise.
	* mips16-opc.c (decode_mips16_operand): Likewise.
	* mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.

gas/
	* config/tc-mips.c (operand_reg_mask, match_operand): Handle
	OP_OPTIONAL_REG.
	(mips_ip, mips16_ip): Use mips_optional_operand_p to check
	for optional operands.
2013-08-19 18:57:00 +00:00
H.J. Lu
79ceb7cb73 Remove PREFIX_EVEX_0F3A3E and PREFIX_EVEX_0F3A3F
* i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
	(PREFIX_EVEX_0F3A3F): Likewise.
	* i386-dis-evex.h (evex_table): Updated.
2013-08-19 15:58:52 +00:00
Richard Sandiford
ee5734f078 opcodes/
2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
	VCLIPW.

gas/
2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>

	* config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel
	suffixes to be elided too.
	(mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here.
	(mips_ip): Assume .xyzw if no VU0 suffix is specified.  Allow +N
	to be omitted too.

gas/testsuite/
2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>

	* gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l,
	gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d: Allow
	single-channel suffixes to be elided.
2013-08-06 19:27:07 +00:00
Eric Botcazou
d6787ef95c gas/
* config/tc-sparc.c (sparc_arch_types): Add leon.
	(sparc_arch): Move sparc4 around and add leon.
	(sparc_target_format): Document -Aleon.
	* doc/c-sparc.texi: Likewise.
include/
	* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON.
opcodes/
	* sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
	bfd_mach_sparc.
	* sparc-opc.c (MASK_LEON): Define.
	(v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
	(letandleon): New macro.
	(v9andleon): Likewise.
	(sparc_opc): Add leon.
	(umac): Enable for letandleon.
	(smac): Likewise.
	(casa): Enable for v9andleon.
	(cas): Likewise.
	(casl): Likewise.
2013-08-05 16:11:07 +00:00
Richard Sandiford
14daeee3ae include/opcode/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* mips.h: Document new VU0 operand characters.
	(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
	(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
	(OP_REG_R5900_ACC): New mips_reg_operand_types.
	(INSN2_VU0_CHANNEL_SUFFIX): New macro.
	(mips_vu0_channel_mask): Declare.

opcodes/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
	OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
	(print_vu0_channel): New function.
	(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
	(print_insn_args): Handle '#'.
	(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
	* mips-opc.c (mips_vu0_channel_mask): New constant.
	(decode_mips_operand): Handle new VU0 operand types.
	(VU0, VU0CH): New macros.
	(mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
	for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
	Use "+6" rather than "G" for QMFC2 and QMTC2.

gas/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
	(RWARN): Bump to 0x8000000.
	(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
	(RTYPE_R5900_ACC): New register types.
	(RTYPE_MASK): Include them.
	(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
	macros.
	(reg_names): Include them.
	(mips_parse_register_1): New function, split out from...
	(mips_parse_register): ...here.  Add a channels_ptr parameter.
	Look for VU0 channel suffixes when nonnull.
	(reg_lookup): Update the call to mips_parse_register.
	(mips_parse_vu0_channels): New function.
	(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
	(mips_operand_token): Add a "channels" field to the union.
	Extend the comment above "ch" to OT_DOUBLE_CHAR.
	(mips_parse_base_start): Match -- and ++.  Handle channel suffixes.
	(mips_parse_argument_token): Handle channel suffixes here too.
	(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
	Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
	Handle '#' formats.
	(md_begin): Register $vfN and $vfI registers.
	(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
	(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
	OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
	(match_vu0_suffix_operand): New function.
	(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
	(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
	(mips_lookup_insn): New function.
	(mips_ip): Use it.  Allow "+K" operands to be elided at the end
	of an instruction.  Handle '#' sequences.

gas/testsuite/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>

	* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
	coprocessor registers.
	* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
	gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
	gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
	* gas/mips/mips.exp: Run them.
2013-08-04 07:31:39 +00:00
Richard Sandiford
3ccad066ac include/opcode/
* mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
	(mips_int_operand_min, mips_int_operand_max): New functions.
	(mips_decode_pcrel_operand): Use mips_decode_int_operand.

opcodes/
	* mips-formats.h (PCREL): Reorder parameters and update the definition
	to match new mips_pcrel_operand layout.
	(JUMP, JALX, BRANCH): Update accordingly.
	* mips16-opc.c (decode_mips16_operand): Likewise.

gas/
	* config/tc-mips.c (match_int_operand): Use mips_int_operand_min
	and mips_int_operand_max.
	(mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
	Delete.
	(mips16_immed_operand, mips16_immed_in_range_p): New functions.
	(mips16_immed, mips16_extended_frag): Use them.  Use mips_int_operand
	instead of mips16_immed_operand.
2013-08-03 10:49:48 +00:00
Richard Sandiford
df34fbcce8 opcodes/
* micromips-opc.c (WR_s): Delete.
2013-08-01 22:33:24 +00:00
Richard Sandiford
fc76e73056 include/opcode/
* mips.h (mips_decode_reg_operand): New function.
	(INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
	(INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
	(INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
	New macros.
	(INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
	(INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
	(INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
	(INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
	(INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
	(INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
	(INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
	(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
	(INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
	(INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
	macros to cover the gaps.
	(INSN2_MOD_SP): Replace with...
	(INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
	(MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
	(MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
	(MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
	(MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
	Delete.

opcodes/
	* mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
	New macros.
	(WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
	(WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
	(mips_builtin_opcodes): Use the new position-based read-write flags
	instead of field-based ones.  Use UDI for "udi..." instructions.
	* mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
	New macros.
	(WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
	(RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
	(WR_SP, RD_16): New macros.
	(RD_SP): Redefine as an INSN2_* flag.
	(MOD_SP): Redefine in terms of RD_SP and WR_SP.
	(mips16_opcodes): Use the new position-based read-write flags
	instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
	pinfo2 field.
	* micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
	New macros.
	(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
	(WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
	(WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
	(RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
	(micromips_opcodes): Use the new position-based read-write flags
	instead of field-based ones.
	* mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
	(print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
	of field-based flags.

gas/
	* config/tc-mips.c (MAX_OPERANDS): New macro.
	(mips_operand_array): New structure.
	(mips_operands, mips16_operands, micromips_operands): New arrays.
	(micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
	(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map)
	(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map)
	(micromips_to_32_reg_q_map): Delete.
	(insn_operands, insn_opno, insn_extract_operand): New functions.
	(validate_mips_insn): Take a mips_operand_array as argument and
	use it to build up a list of operands.  Extend to handle INSN_MACRO
	and MIPS16.
	(validate_mips16_insn): New function.
	(validate_micromips_insn): Take a mips_operand_array as argument.
	Handle INSN_MACRO.
	(md_begin): Initialize mips_operands, mips16_operands and
	micromips_operands.  Call validate_mips_insn and
	validate_micromips_insn for macro instructions too.
	Call validate_mips16_insn for MIPS16 instructions.
	(insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask):
	New functions.
	(gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use
	them.  Handle INSN_UDI.
	(get_append_method): Use gpr_read_mask.
2013-08-01 20:55:25 +00:00