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Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.

Browse source 
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512vl, CPU_AVX512VL_FLAGS.
	(build_vex_prefix): Don't abort on VEX.W.
	(check_VecOperands): Support BROADCAST_1TO4 and BROADCAST_1TO2.
	(check_VecOperations): Ditto.
	* doc/c-i386.texi: Document avx512vl/.avx512vl.

gas/testsuite/

	* gas/i386/avx512f_vl-intel.d: New.
	* gas/i386/avx512f_vl-opts-intel.d: New.
	* gas/i386/avx512f_vl-opts.d: New.
	* gas/i386/avx512f_vl-opts.s: New.
	* gas/i386/avx512f_vl-wig.s: New.
	* gas/i386/avx512f_vl-wig1-intel.d: New.
	* gas/i386/avx512f_vl-wig1.d: New.
	* gas/i386/avx512f_vl.d: New.
	* gas/i386/avx512f_vl.s: New.
	* gas/i386/i386.exp: Run new AVX-512 tests.
	* gas/i386/x86-64-avx512f_vl-intel.d: New.
	* gas/i386/x86-64-avx512f_vl-opts-intel.d: New.
	* gas/i386/x86-64-avx512f_vl-opts.d: New.
	* gas/i386/x86-64-avx512f_vl-opts.s: New.
	* gas/i386/x86-64-avx512f_vl-wig.s: New.
	* gas/i386/x86-64-avx512f_vl-wig1-intel.d: New.
	* gas/i386/x86-64-avx512f_vl-wig1.d: New.
	* gas/i386/x86-64-avx512f_vl.d: New.
	* gas/i386/x86-64-avx512f_vl.s: New.

opcodes/

	* i386-dis.c (intel_operand_size): Support 128/256 length in
	vex_vsib_q_w_dq_mode.
	(OP_E_memory): Add ymmq_mode handling, handle new broadcast.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
	(cpu_flags): Add CpuAVX512VL.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuAVX512VL): New.
	(i386_cpu_flags): Add cpuavx512vl.
	(BROADCAST_1TO4, BROADCAST_1TO2): Define.
	* i386-opc.tbl: Add AVX512VL instructions.
	* i386-tbl.h: Regenerate.
This commit is contained in:
Ilya Tocar 2014-07-18 14:59:54 +04:00 committed by H.J. Lu
parent 50d13ae760
commit b28d1bda54
30 changed files with 96273 additions and 4513 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
gas/ChangeLog
View file

@ -1,3 +1,20 @@
2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512vl, CPU_AVX512VL_FLAGS.
(build_vex_prefix): Don't abort on VEX.W.
(check_VecOperands): Support BROADCAST_1TO4 and BROADCAST_1TO2.
(check_VecOperations): Ditto.
* doc/c-i386.texi: Document avx512vl/.avx512vl.
2014-07-21 Joel Sherrill <joel.sherrill@oarcorp.com>
Add or reactivate or1k-*-rtems*

20
gas/config/tc-i386.c
View file

@ -916,6 +916,8 @@ static const arch_entry cpu_arch[] =
CPU_PREFETCHWT1_FLAGS, 0, 0 },
{ STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
CPU_SE1_FLAGS, 0, 0 },
{ STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
CPU_AVX512VL_FLAGS, 0, 0 },
};
#ifdef I386COFF
@ -3163,14 +3165,8 @@ build_vex_prefix (const insn_template *t)
/* Check the REX.W bit. */
w = (i.rex & REX_W) ? 1 : 0;
if (i.tm.opcode_modifier.vexw)
{
if (w)
abort ();
if (i.tm.opcode_modifier.vexw == VEXW1)
w = 1;
}
if (i.tm.opcode_modifier.vexw == VEXW1)
w = 1;
i.vex.bytes[2] = (w << 7
| register_specifier << 3
@ -4450,6 +4446,10 @@ check_VecOperands (const insn_template *t)
broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
else if (i.broadcast->type == BROADCAST_1TO8)
broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
else if (i.broadcast->type == BROADCAST_1TO4)
broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
else if (i.broadcast->type == BROADCAST_1TO2)
broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
else
goto bad_broadcast;
@ -7752,6 +7752,10 @@ check_VecOperations (char *op_string, char *op_end)
op_string += 3;
if (*op_string == '8')
bcst_type = BROADCAST_1TO8;
else if (*op_string == '4')
bcst_type = BROADCAST_1TO4;
else if (*op_string == '2')
bcst_type = BROADCAST_1TO2;
else if (*op_string == '1'
&& *(op_string+1) == '6')
{

2
gas/doc/c-i386.texi
View file

@ -188,6 +188,7 @@ accept various extension mnemonics. For example,
@code{svme},
@code{abm} and
@code{padlock}.
@code{avx512vl},
Note that rather than extending a basic instruction set, the extension
mnemonics starting with @code{no} revoke the respective functionality.
@ -1070,6 +1071,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.smap} @tab @samp{.sha}
@item @samp{.smap} @tab @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves}
@item @samp{.smap} @tab @samp{.prefetchwt1}
@item @samp{.smap} @tab @samp{.avx512vl}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}

31
gas/testsuite/ChangeLog
View file

@ -1,3 +1,34 @@
2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/i386/avx512f_vl-intel.d: New.
* gas/i386/avx512f_vl-opts-intel.d: New.
* gas/i386/avx512f_vl-opts.d: New.
* gas/i386/avx512f_vl-opts.s: New.
* gas/i386/avx512f_vl-wig.s: New.
* gas/i386/avx512f_vl-wig1-intel.d: New.
* gas/i386/avx512f_vl-wig1.d: New.
* gas/i386/avx512f_vl.d: New.
* gas/i386/avx512f_vl.s: New.
* gas/i386/i386.exp: Run new AVX-512 tests.
* gas/i386/x86-64-avx512f_vl-intel.d: New.
* gas/i386/x86-64-avx512f_vl-opts-intel.d: New.
* gas/i386/x86-64-avx512f_vl-opts.d: New.
* gas/i386/x86-64-avx512f_vl-opts.s: New.
* gas/i386/x86-64-avx512f_vl-wig.s: New.
* gas/i386/x86-64-avx512f_vl-wig1-intel.d: New.
* gas/i386/x86-64-avx512f_vl-wig1.d: New.
* gas/i386/x86-64-avx512f_vl.d: New.
* gas/i386/x86-64-avx512f_vl.s: New.
2014-07-17 Ilya Tocar <ilya.tocar@intel.com>
* gas/i386/x86-64-equ.d: New.

11402
gas/testsuite/gas/i386/avx512f_vl-intel.d Normal file
View file

File diff suppressed because it is too large Load diff

268
gas/testsuite/gas/i386/avx512f_vl-opts-intel.d Normal file
View file

@ -0,0 +1,268 @@
#as:
#objdump: -dw -Mintel -Msuffix
#name: i386 AVX512F/VL opts insns (Intel disassembly)
#source: avx512f_vl-opts.s
.*: +file format .*
Disassembly of section \.text:
00000000 <_start>:
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 28 f5[ ]*vmovapd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 29 ee[ ]*vmovapd\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 28 f5[ ]*vmovapd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 29 ee[ ]*vmovapd\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 28 f5[ ]*vmovapd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 29 ee[ ]*vmovapd\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 28 f5[ ]*vmovapd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 29 ee[ ]*vmovapd\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 28 f5[ ]*vmovapd ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 29 ee[ ]*vmovapd\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 28 f5[ ]*vmovapd ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 29 ee[ ]*vmovapd\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 28 f5[ ]*vmovapd ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 29 ee[ ]*vmovapd\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 28 f5[ ]*vmovapd ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 29 ee[ ]*vmovapd\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 28 f5[ ]*vmovaps xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 29 ee[ ]*vmovaps\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 28 f5[ ]*vmovaps xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 29 ee[ ]*vmovaps\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 28 f5[ ]*vmovaps xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 29 ee[ ]*vmovaps\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 28 f5[ ]*vmovaps xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 29 ee[ ]*vmovaps\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 28 f5[ ]*vmovaps ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 29 ee[ ]*vmovaps\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 28 f5[ ]*vmovaps ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 29 ee[ ]*vmovaps\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 28 f5[ ]*vmovaps ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 29 ee[ ]*vmovaps\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 28 f5[ ]*vmovaps ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 29 ee[ ]*vmovaps\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 6f f5[ ]*vmovdqa32 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 7f ee[ ]*vmovdqa32\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 6f f5[ ]*vmovdqa32 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 7f ee[ ]*vmovdqa32\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 6f f5[ ]*vmovdqa32 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 7f ee[ ]*vmovdqa32\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 6f f5[ ]*vmovdqa32 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 7f ee[ ]*vmovdqa32\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 6f f5[ ]*vmovdqa32 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 7f ee[ ]*vmovdqa32\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 6f f5[ ]*vmovdqa32 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 7f ee[ ]*vmovdqa32\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 6f f5[ ]*vmovdqa32 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 7f ee[ ]*vmovdqa32\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 6f f5[ ]*vmovdqa32 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 7f ee[ ]*vmovdqa32\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 6f f5[ ]*vmovdqa64 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 7f ee[ ]*vmovdqa64\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 6f f5[ ]*vmovdqa64 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 7f ee[ ]*vmovdqa64\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 6f f5[ ]*vmovdqa64 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 7f ee[ ]*vmovdqa64\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 6f f5[ ]*vmovdqa64 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 7f ee[ ]*vmovdqa64\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 6f f5[ ]*vmovdqa64 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 7f ee[ ]*vmovdqa64\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 6f f5[ ]*vmovdqa64 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 7f ee[ ]*vmovdqa64\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 6f f5[ ]*vmovdqa64 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 7f ee[ ]*vmovdqa64\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 6f f5[ ]*vmovdqa64 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 7f ee[ ]*vmovdqa64\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 6f f5[ ]*vmovdqu32 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 7f ee[ ]*vmovdqu32\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 6f f5[ ]*vmovdqu32 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 7f ee[ ]*vmovdqu32\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 6f f5[ ]*vmovdqu32 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 7f ee[ ]*vmovdqu32\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 6f f5[ ]*vmovdqu32 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 7f ee[ ]*vmovdqu32\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 6f f5[ ]*vmovdqu32 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 7f ee[ ]*vmovdqu32\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 6f f5[ ]*vmovdqu32 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 7f ee[ ]*vmovdqu32\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 6f f5[ ]*vmovdqu32 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 7f ee[ ]*vmovdqu32\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 6f f5[ ]*vmovdqu32 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 7f ee[ ]*vmovdqu32\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 6f f5[ ]*vmovdqu64 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 7f ee[ ]*vmovdqu64\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 6f f5[ ]*vmovdqu64 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 7f ee[ ]*vmovdqu64\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 6f f5[ ]*vmovdqu64 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 7f ee[ ]*vmovdqu64\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 6f f5[ ]*vmovdqu64 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 7f ee[ ]*vmovdqu64\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 6f f5[ ]*vmovdqu64 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 7f ee[ ]*vmovdqu64\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 6f f5[ ]*vmovdqu64 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 7f ee[ ]*vmovdqu64\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 6f f5[ ]*vmovdqu64 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 7f ee[ ]*vmovdqu64\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 6f f5[ ]*vmovdqu64 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 7f ee[ ]*vmovdqu64\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 10 f5[ ]*vmovupd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 11 ee[ ]*vmovupd\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 10 f5[ ]*vmovupd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 11 ee[ ]*vmovupd\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 10 f5[ ]*vmovupd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 11 ee[ ]*vmovupd\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 10 f5[ ]*vmovupd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 11 ee[ ]*vmovupd\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 10 f5[ ]*vmovupd ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 11 ee[ ]*vmovupd\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 10 f5[ ]*vmovupd ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 11 ee[ ]*vmovupd\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 10 f5[ ]*vmovupd ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 11 ee[ ]*vmovupd\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 10 f5[ ]*vmovupd ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 11 ee[ ]*vmovupd\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 10 f5[ ]*vmovups xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 11 ee[ ]*vmovups\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 10 f5[ ]*vmovups xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 11 ee[ ]*vmovups\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 10 f5[ ]*vmovups xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 11 ee[ ]*vmovups\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 10 f5[ ]*vmovups xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 11 ee[ ]*vmovups\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 10 f5[ ]*vmovups ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 11 ee[ ]*vmovups\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 10 f5[ ]*vmovups ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 11 ee[ ]*vmovups\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 10 f5[ ]*vmovups ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 11 ee[ ]*vmovups\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 10 f5[ ]*vmovups ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 11 ee[ ]*vmovups\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 28 f5[ ]*vmovapd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 29 ee[ ]*vmovapd\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 28 f5[ ]*vmovapd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 29 ee[ ]*vmovapd\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 28 f5[ ]*vmovapd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 29 ee[ ]*vmovapd\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 28 f5[ ]*vmovapd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 29 ee[ ]*vmovapd\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 28 f5[ ]*vmovapd ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 29 ee[ ]*vmovapd\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 28 f5[ ]*vmovapd ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 29 ee[ ]*vmovapd\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 28 f5[ ]*vmovapd ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 29 ee[ ]*vmovapd\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 28 f5[ ]*vmovapd ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 29 ee[ ]*vmovapd\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 28 f5[ ]*vmovaps xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 29 ee[ ]*vmovaps\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 28 f5[ ]*vmovaps xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 29 ee[ ]*vmovaps\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 28 f5[ ]*vmovaps xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 29 ee[ ]*vmovaps\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 28 f5[ ]*vmovaps xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 29 ee[ ]*vmovaps\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 28 f5[ ]*vmovaps ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 29 ee[ ]*vmovaps\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 28 f5[ ]*vmovaps ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 29 ee[ ]*vmovaps\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 28 f5[ ]*vmovaps ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 29 ee[ ]*vmovaps\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 28 f5[ ]*vmovaps ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 29 ee[ ]*vmovaps\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 6f f5[ ]*vmovdqa32 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 7f ee[ ]*vmovdqa32\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 6f f5[ ]*vmovdqa32 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 7f ee[ ]*vmovdqa32\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 6f f5[ ]*vmovdqa32 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 7f ee[ ]*vmovdqa32\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 6f f5[ ]*vmovdqa32 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 7f ee[ ]*vmovdqa32\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 6f f5[ ]*vmovdqa32 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 7f ee[ ]*vmovdqa32\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 6f f5[ ]*vmovdqa32 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 7f ee[ ]*vmovdqa32\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 6f f5[ ]*vmovdqa32 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 7f ee[ ]*vmovdqa32\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 6f f5[ ]*vmovdqa32 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 7f ee[ ]*vmovdqa32\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 6f f5[ ]*vmovdqa64 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 7f ee[ ]*vmovdqa64\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 6f f5[ ]*vmovdqa64 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 7f ee[ ]*vmovdqa64\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 6f f5[ ]*vmovdqa64 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 7f ee[ ]*vmovdqa64\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 6f f5[ ]*vmovdqa64 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 7f ee[ ]*vmovdqa64\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 6f f5[ ]*vmovdqa64 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 7f ee[ ]*vmovdqa64\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 6f f5[ ]*vmovdqa64 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 7f ee[ ]*vmovdqa64\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 6f f5[ ]*vmovdqa64 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 7f ee[ ]*vmovdqa64\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 6f f5[ ]*vmovdqa64 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 7f ee[ ]*vmovdqa64\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 6f f5[ ]*vmovdqu32 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 7f ee[ ]*vmovdqu32\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 6f f5[ ]*vmovdqu32 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 7f ee[ ]*vmovdqu32\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 6f f5[ ]*vmovdqu32 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 7f ee[ ]*vmovdqu32\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 6f f5[ ]*vmovdqu32 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 7f ee[ ]*vmovdqu32\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 6f f5[ ]*vmovdqu32 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 7f ee[ ]*vmovdqu32\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 6f f5[ ]*vmovdqu32 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 7f ee[ ]*vmovdqu32\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 6f f5[ ]*vmovdqu32 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 7f ee[ ]*vmovdqu32\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 6f f5[ ]*vmovdqu32 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 7f ee[ ]*vmovdqu32\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 6f f5[ ]*vmovdqu64 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 7f ee[ ]*vmovdqu64\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 6f f5[ ]*vmovdqu64 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 7f ee[ ]*vmovdqu64\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 6f f5[ ]*vmovdqu64 xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 7f ee[ ]*vmovdqu64\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 6f f5[ ]*vmovdqu64 xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 7f ee[ ]*vmovdqu64\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 6f f5[ ]*vmovdqu64 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 7f ee[ ]*vmovdqu64\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 6f f5[ ]*vmovdqu64 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 7f ee[ ]*vmovdqu64\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 6f f5[ ]*vmovdqu64 ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 7f ee[ ]*vmovdqu64\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 6f f5[ ]*vmovdqu64 ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 7f ee[ ]*vmovdqu64\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 10 f5[ ]*vmovupd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 11 ee[ ]*vmovupd\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 10 f5[ ]*vmovupd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 11 ee[ ]*vmovupd\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 10 f5[ ]*vmovupd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 11 ee[ ]*vmovupd\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 10 f5[ ]*vmovupd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 11 ee[ ]*vmovupd\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 10 f5[ ]*vmovupd ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 11 ee[ ]*vmovupd\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 10 f5[ ]*vmovupd ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 11 ee[ ]*vmovupd\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 10 f5[ ]*vmovupd ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 11 ee[ ]*vmovupd\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 10 f5[ ]*vmovupd ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 11 ee[ ]*vmovupd\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 10 f5[ ]*vmovups xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 11 ee[ ]*vmovups\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 10 f5[ ]*vmovups xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 11 ee[ ]*vmovups\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 10 f5[ ]*vmovups xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 11 ee[ ]*vmovups\.s xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 10 f5[ ]*vmovups xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 11 ee[ ]*vmovups\.s xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 10 f5[ ]*vmovups ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 11 ee[ ]*vmovups\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 10 f5[ ]*vmovups ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 11 ee[ ]*vmovups\.s ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 10 f5[ ]*vmovups ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 11 ee[ ]*vmovups\.s ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 10 f5[ ]*vmovups ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 11 ee[ ]*vmovups\.s ymm6\{k7\}\{z\},ymm5
#pass

268
gas/testsuite/gas/i386/avx512f_vl-opts.d Normal file
View file

@ -0,0 +1,268 @@
#as:
#objdump: -dw -Msuffix
#name: i386 AVX512F/VL opts insns
#source: avx512f_vl-opts.s
.*: +file format .*
Disassembly of section \.text:
00000000 <_start>:
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 28 f5[ ]*vmovapd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 29 ee[ ]*vmovapd\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 28 f5[ ]*vmovapd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 29 ee[ ]*vmovapd\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 28 f5[ ]*vmovapd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 29 ee[ ]*vmovapd\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 28 f5[ ]*vmovapd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 29 ee[ ]*vmovapd\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 28 f5[ ]*vmovapd %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 29 ee[ ]*vmovapd\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 28 f5[ ]*vmovapd %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 29 ee[ ]*vmovapd\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 28 f5[ ]*vmovapd %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 29 ee[ ]*vmovapd\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 28 f5[ ]*vmovapd %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 29 ee[ ]*vmovapd\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 28 f5[ ]*vmovaps %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 29 ee[ ]*vmovaps\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 28 f5[ ]*vmovaps %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 29 ee[ ]*vmovaps\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 28 f5[ ]*vmovaps %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 29 ee[ ]*vmovaps\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 28 f5[ ]*vmovaps %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 29 ee[ ]*vmovaps\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 28 f5[ ]*vmovaps %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 29 ee[ ]*vmovaps\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 28 f5[ ]*vmovaps %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 29 ee[ ]*vmovaps\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 28 f5[ ]*vmovaps %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 29 ee[ ]*vmovaps\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 28 f5[ ]*vmovaps %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 29 ee[ ]*vmovaps\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 6f f5[ ]*vmovdqa32 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 7f ee[ ]*vmovdqa32\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 6f f5[ ]*vmovdqa32 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 7f ee[ ]*vmovdqa32\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 6f f5[ ]*vmovdqa32 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 7f ee[ ]*vmovdqa32\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 6f f5[ ]*vmovdqa32 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 7f ee[ ]*vmovdqa32\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 6f f5[ ]*vmovdqa32 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 7f ee[ ]*vmovdqa32\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 6f f5[ ]*vmovdqa32 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 7f ee[ ]*vmovdqa32\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 6f f5[ ]*vmovdqa32 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 7f ee[ ]*vmovdqa32\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 6f f5[ ]*vmovdqa32 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 7f ee[ ]*vmovdqa32\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 6f f5[ ]*vmovdqa64 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 7f ee[ ]*vmovdqa64\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 6f f5[ ]*vmovdqa64 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 7f ee[ ]*vmovdqa64\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 6f f5[ ]*vmovdqa64 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 7f ee[ ]*vmovdqa64\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 6f f5[ ]*vmovdqa64 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 7f ee[ ]*vmovdqa64\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 6f f5[ ]*vmovdqa64 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 7f ee[ ]*vmovdqa64\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 6f f5[ ]*vmovdqa64 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 7f ee[ ]*vmovdqa64\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 6f f5[ ]*vmovdqa64 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 7f ee[ ]*vmovdqa64\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 6f f5[ ]*vmovdqa64 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 7f ee[ ]*vmovdqa64\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 6f f5[ ]*vmovdqu32 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 7f ee[ ]*vmovdqu32\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 6f f5[ ]*vmovdqu32 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 7f ee[ ]*vmovdqu32\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 6f f5[ ]*vmovdqu32 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 7f ee[ ]*vmovdqu32\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 6f f5[ ]*vmovdqu32 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 7f ee[ ]*vmovdqu32\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 6f f5[ ]*vmovdqu32 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 7f ee[ ]*vmovdqu32\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 6f f5[ ]*vmovdqu32 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 7f ee[ ]*vmovdqu32\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 6f f5[ ]*vmovdqu32 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 7f ee[ ]*vmovdqu32\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 6f f5[ ]*vmovdqu32 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 7f ee[ ]*vmovdqu32\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 6f f5[ ]*vmovdqu64 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 7f ee[ ]*vmovdqu64\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 6f f5[ ]*vmovdqu64 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 7f ee[ ]*vmovdqu64\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 6f f5[ ]*vmovdqu64 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 7f ee[ ]*vmovdqu64\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 6f f5[ ]*vmovdqu64 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 7f ee[ ]*vmovdqu64\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 6f f5[ ]*vmovdqu64 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 7f ee[ ]*vmovdqu64\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 6f f5[ ]*vmovdqu64 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 7f ee[ ]*vmovdqu64\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 6f f5[ ]*vmovdqu64 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 7f ee[ ]*vmovdqu64\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 6f f5[ ]*vmovdqu64 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 7f ee[ ]*vmovdqu64\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 10 f5[ ]*vmovupd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 11 ee[ ]*vmovupd\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 10 f5[ ]*vmovupd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 11 ee[ ]*vmovupd\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 10 f5[ ]*vmovupd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 11 ee[ ]*vmovupd\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 10 f5[ ]*vmovupd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 11 ee[ ]*vmovupd\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 10 f5[ ]*vmovupd %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 11 ee[ ]*vmovupd\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 10 f5[ ]*vmovupd %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 11 ee[ ]*vmovupd\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 10 f5[ ]*vmovupd %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 11 ee[ ]*vmovupd\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 10 f5[ ]*vmovupd %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 11 ee[ ]*vmovupd\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 10 f5[ ]*vmovups %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 11 ee[ ]*vmovups\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 10 f5[ ]*vmovups %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 11 ee[ ]*vmovups\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 10 f5[ ]*vmovups %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 11 ee[ ]*vmovups\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 10 f5[ ]*vmovups %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 11 ee[ ]*vmovups\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 10 f5[ ]*vmovups %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 11 ee[ ]*vmovups\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 10 f5[ ]*vmovups %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 11 ee[ ]*vmovups\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 10 f5[ ]*vmovups %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 11 ee[ ]*vmovups\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 10 f5[ ]*vmovups %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 11 ee[ ]*vmovups\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 28 f5[ ]*vmovapd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 29 ee[ ]*vmovapd\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 28 f5[ ]*vmovapd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 29 ee[ ]*vmovapd\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 28 f5[ ]*vmovapd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 29 ee[ ]*vmovapd\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 28 f5[ ]*vmovapd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 29 ee[ ]*vmovapd\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 28 f5[ ]*vmovapd %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 29 ee[ ]*vmovapd\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 28 f5[ ]*vmovapd %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 29 ee[ ]*vmovapd\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 28 f5[ ]*vmovapd %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 29 ee[ ]*vmovapd\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 28 f5[ ]*vmovapd %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 29 ee[ ]*vmovapd\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 28 f5[ ]*vmovaps %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 29 ee[ ]*vmovaps\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 28 f5[ ]*vmovaps %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 29 ee[ ]*vmovaps\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 28 f5[ ]*vmovaps %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 29 ee[ ]*vmovaps\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 28 f5[ ]*vmovaps %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 29 ee[ ]*vmovaps\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 28 f5[ ]*vmovaps %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 29 ee[ ]*vmovaps\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 28 f5[ ]*vmovaps %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 29 ee[ ]*vmovaps\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 28 f5[ ]*vmovaps %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 29 ee[ ]*vmovaps\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 28 f5[ ]*vmovaps %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 29 ee[ ]*vmovaps\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 6f f5[ ]*vmovdqa32 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 7f ee[ ]*vmovdqa32\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 6f f5[ ]*vmovdqa32 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 7f ee[ ]*vmovdqa32\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 6f f5[ ]*vmovdqa32 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 0f 7f ee[ ]*vmovdqa32\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 6f f5[ ]*vmovdqa32 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 8f 7f ee[ ]*vmovdqa32\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 6f f5[ ]*vmovdqa32 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 7f ee[ ]*vmovdqa32\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 6f f5[ ]*vmovdqa32 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 7f ee[ ]*vmovdqa32\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 6f f5[ ]*vmovdqa32 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d 2f 7f ee[ ]*vmovdqa32\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 6f f5[ ]*vmovdqa32 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7d af 7f ee[ ]*vmovdqa32\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 6f f5[ ]*vmovdqa64 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 7f ee[ ]*vmovdqa64\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 6f f5[ ]*vmovdqa64 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 7f ee[ ]*vmovdqa64\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 6f f5[ ]*vmovdqa64 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 7f ee[ ]*vmovdqa64\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 6f f5[ ]*vmovdqa64 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 7f ee[ ]*vmovdqa64\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 6f f5[ ]*vmovdqa64 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 7f ee[ ]*vmovdqa64\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 6f f5[ ]*vmovdqa64 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 7f ee[ ]*vmovdqa64\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 6f f5[ ]*vmovdqa64 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 7f ee[ ]*vmovdqa64\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 6f f5[ ]*vmovdqa64 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 7f ee[ ]*vmovdqa64\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 6f f5[ ]*vmovdqu32 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 7f ee[ ]*vmovdqu32\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 6f f5[ ]*vmovdqu32 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 7f ee[ ]*vmovdqu32\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 6f f5[ ]*vmovdqu32 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 0f 7f ee[ ]*vmovdqu32\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 6f f5[ ]*vmovdqu32 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 8f 7f ee[ ]*vmovdqu32\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 6f f5[ ]*vmovdqu32 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 7f ee[ ]*vmovdqu32\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 6f f5[ ]*vmovdqu32 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 7f ee[ ]*vmovdqu32\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 6f f5[ ]*vmovdqu32 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e 2f 7f ee[ ]*vmovdqu32\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 6f f5[ ]*vmovdqu32 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7e af 7f ee[ ]*vmovdqu32\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 6f f5[ ]*vmovdqu64 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 7f ee[ ]*vmovdqu64\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 6f f5[ ]*vmovdqu64 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 7f ee[ ]*vmovdqu64\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 6f f5[ ]*vmovdqu64 %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 0f 7f ee[ ]*vmovdqu64\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 6f f5[ ]*vmovdqu64 %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 8f 7f ee[ ]*vmovdqu64\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 6f f5[ ]*vmovdqu64 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 7f ee[ ]*vmovdqu64\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 6f f5[ ]*vmovdqu64 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 7f ee[ ]*vmovdqu64\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 6f f5[ ]*vmovdqu64 %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe 2f 7f ee[ ]*vmovdqu64\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 6f f5[ ]*vmovdqu64 %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fe af 7f ee[ ]*vmovdqu64\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 10 f5[ ]*vmovupd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 11 ee[ ]*vmovupd\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 10 f5[ ]*vmovupd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 11 ee[ ]*vmovupd\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 10 f5[ ]*vmovupd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 0f 11 ee[ ]*vmovupd\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 10 f5[ ]*vmovupd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 8f 11 ee[ ]*vmovupd\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 10 f5[ ]*vmovupd %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 11 ee[ ]*vmovupd\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 10 f5[ ]*vmovupd %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 11 ee[ ]*vmovupd\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 10 f5[ ]*vmovupd %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd 2f 11 ee[ ]*vmovupd\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 10 f5[ ]*vmovupd %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 fd af 11 ee[ ]*vmovupd\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 10 f5[ ]*vmovups %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 11 ee[ ]*vmovups\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 10 f5[ ]*vmovups %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 11 ee[ ]*vmovups\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 10 f5[ ]*vmovups %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 0f 11 ee[ ]*vmovups\.s %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 10 f5[ ]*vmovups %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 8f 11 ee[ ]*vmovups\.s %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 10 f5[ ]*vmovups %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 11 ee[ ]*vmovups\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 10 f5[ ]*vmovups %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 11 ee[ ]*vmovups\.s %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 10 f5[ ]*vmovups %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c 2f 11 ee[ ]*vmovups\.s %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 10 f5[ ]*vmovups %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f1 7c af 11 ee[ ]*vmovups\.s %ymm5,%ymm6\{%k7\}\{z\}
#pass

263
gas/testsuite/gas/i386/avx512f_vl-opts.s Normal file
View file

@ -0,0 +1,263 @@
# Check 32bit AVX512{F,VL} swap instructions
.allow_index_reg
.text
_start:
vmovapd %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovapd.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovapd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovapd.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovapd %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovapd.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovapd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovapd.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovapd %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovapd.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovapd %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovapd.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovapd %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovapd.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovapd %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovapd.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovaps %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovaps.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovaps %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovaps.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovaps %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovaps.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovaps %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovaps.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovaps %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovaps.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovaps %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovaps.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovaps %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovaps.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovaps %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovaps.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqa32 %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqa32.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqa32 %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqa32.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqa32 %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqa32.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqa32 %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqa32.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqa32 %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqa32.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqa32 %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqa32.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqa32 %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqa32.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqa32 %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqa32.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqa64 %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqa64.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqa64 %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqa64.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqa64 %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqa64.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqa64 %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqa64.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqa64 %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqa64.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqa64 %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqa64.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqa64 %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqa64.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqa64 %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqa64.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqu32 %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqu32.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqu32 %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqu32.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqu32 %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqu32.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqu32 %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqu32.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqu32 %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqu32.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqu32 %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqu32.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqu32 %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqu32.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqu32 %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqu32.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqu64 %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqu64.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqu64 %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqu64.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqu64 %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqu64.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovdqu64 %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqu64.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovdqu64 %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqu64.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqu64 %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqu64.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqu64 %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqu64.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovdqu64 %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovdqu64.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovupd %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovupd.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovupd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovupd.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovupd %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovupd.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovupd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovupd.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovupd %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovupd.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovupd %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovupd.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovupd %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovupd.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovupd %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovupd.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovups %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovups.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovups %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovups.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovups %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovups.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
vmovups %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovups.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vmovups %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovups.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovups %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovups.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovups %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovups.s %ymm5, %ymm6{%k7} # AVX512{F,VL}
vmovups %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
vmovups.s %ymm5, %ymm6{%k7}{z} # AVX512{F,VL}
.intel_syntax noprefix
vmovapd xmm6{k7}, xmm5 # AVX512{F,VL}
vmovapd.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovapd xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovapd.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovapd xmm6{k7}, xmm5 # AVX512{F,VL}
vmovapd.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovapd xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovapd.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovapd ymm6{k7}, ymm5 # AVX512{F,VL}
vmovapd.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovapd ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovapd.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovapd ymm6{k7}, ymm5 # AVX512{F,VL}
vmovapd.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovapd ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovapd.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovaps xmm6{k7}, xmm5 # AVX512{F,VL}
vmovaps.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovaps xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovaps.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovaps xmm6{k7}, xmm5 # AVX512{F,VL}
vmovaps.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovaps xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovaps.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovaps ymm6{k7}, ymm5 # AVX512{F,VL}
vmovaps.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovaps ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovaps.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovaps ymm6{k7}, ymm5 # AVX512{F,VL}
vmovaps.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovaps ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovaps.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqa32 xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqa32.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqa32 xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqa32.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqa32 xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqa32.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqa32 xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqa32.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqa32 ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqa32.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqa32 ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqa32.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqa32 ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqa32.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqa32 ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqa32.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqa64 xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqa64.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqa64 xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqa64.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqa64 xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqa64.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqa64 xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqa64.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqa64 ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqa64.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqa64 ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqa64.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqa64 ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqa64.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqa64 ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqa64.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqu32 xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqu32.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqu32 xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqu32.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqu32 xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqu32.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqu32 xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqu32.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqu32 ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqu32.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqu32 ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqu32.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqu32 ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqu32.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqu32 ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqu32.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqu64 xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqu64.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqu64 xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqu64.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqu64 xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqu64.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovdqu64 xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqu64.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovdqu64 ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqu64.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqu64 ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqu64.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqu64 ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqu64.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovdqu64 ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovdqu64.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovupd xmm6{k7}, xmm5 # AVX512{F,VL}
vmovupd.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovupd xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovupd.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovupd xmm6{k7}, xmm5 # AVX512{F,VL}
vmovupd.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovupd xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovupd.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovupd ymm6{k7}, ymm5 # AVX512{F,VL}
vmovupd.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovupd ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovupd.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovupd ymm6{k7}, ymm5 # AVX512{F,VL}
vmovupd.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovupd ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovupd.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovups xmm6{k7}, xmm5 # AVX512{F,VL}
vmovups.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovups xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovups.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovups xmm6{k7}, xmm5 # AVX512{F,VL}
vmovups.s xmm6{k7}, xmm5 # AVX512{F,VL}
vmovups xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovups.s xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vmovups ymm6{k7}, ymm5 # AVX512{F,VL}
vmovups.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovups ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovups.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovups ymm6{k7}, ymm5 # AVX512{F,VL}
vmovups.s ymm6{k7}, ymm5 # AVX512{F,VL}
vmovups ymm6{k7}{z}, ymm5 # AVX512{F,VL}
vmovups.s ymm6{k7}{z}, ymm5 # AVX512{F,VL}

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gas/testsuite/gas/i386/avx512f_vl-wig.s Normal file
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# Check 32bit AVX512{F,VL} WIG instructions
.allow_index_reg
.text
_start:
vpmovsxbd %xmm5, %xmm6{%k7} # AVX512{F,VL}
vpmovsxbd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vpmovsxbd (%ecx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxbd -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
vpmovsxbd 508(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovsxbd 512(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxbd -512(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovsxbd -516(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxbd %xmm5, %ymm6{%k7} # AVX512{F,VL}
vpmovsxbd %xmm5, %ymm6{%k7}{z} # AVX512{F,VL}
vpmovsxbd (%ecx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxbd -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{F,VL}
vpmovsxbd 1016(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovsxbd 1024(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxbd -1024(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovsxbd -1032(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxbq %xmm5, %xmm6{%k7} # AVX512{F,VL}
vpmovsxbq %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vpmovsxbq (%ecx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxbq -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
vpmovsxbq 254(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovsxbq 256(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxbq -256(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovsxbq -258(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxbq %xmm5, %ymm6{%k7} # AVX512{F,VL}
vpmovsxbq %xmm5, %ymm6{%k7}{z} # AVX512{F,VL}
vpmovsxbq (%ecx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxbq -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{F,VL}
vpmovsxbq 508(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovsxbq 512(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxbq -512(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovsxbq -516(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxwd %xmm5, %xmm6{%k7} # AVX512{F,VL}
vpmovsxwd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vpmovsxwd (%ecx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxwd -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
vpmovsxwd 1016(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovsxwd 1024(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxwd -1024(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovsxwd -1032(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxwd %xmm5, %ymm6{%k7} # AVX512{F,VL}
vpmovsxwd %xmm5, %ymm6{%k7}{z} # AVX512{F,VL}
vpmovsxwd (%ecx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxwd -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{F,VL}
vpmovsxwd 2032(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovsxwd 2048(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxwd -2048(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovsxwd -2064(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxwq %xmm5, %xmm6{%k7} # AVX512{F,VL}
vpmovsxwq %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vpmovsxwq (%ecx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxwq -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
vpmovsxwq 508(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovsxwq 512(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxwq -512(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovsxwq -516(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovsxwq %xmm5, %ymm6{%k7} # AVX512{F,VL}
vpmovsxwq %xmm5, %ymm6{%k7}{z} # AVX512{F,VL}
vpmovsxwq (%ecx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxwq -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{F,VL}
vpmovsxwq 1016(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovsxwq 1024(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovsxwq -1024(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovsxwq -1032(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxbd %xmm5, %xmm6{%k7} # AVX512{F,VL}
vpmovzxbd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vpmovzxbd (%ecx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxbd -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
vpmovzxbd 508(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovzxbd 512(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxbd -512(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovzxbd -516(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxbd %xmm5, %ymm6{%k7} # AVX512{F,VL}
vpmovzxbd %xmm5, %ymm6{%k7}{z} # AVX512{F,VL}
vpmovzxbd (%ecx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxbd -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{F,VL}
vpmovzxbd 1016(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovzxbd 1024(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxbd -1024(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovzxbd -1032(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxbq %xmm5, %xmm6{%k7} # AVX512{F,VL}
vpmovzxbq %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vpmovzxbq (%ecx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxbq -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
vpmovzxbq 254(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovzxbq 256(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxbq -256(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovzxbq -258(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxbq %xmm5, %ymm6{%k7} # AVX512{F,VL}
vpmovzxbq %xmm5, %ymm6{%k7}{z} # AVX512{F,VL}
vpmovzxbq (%ecx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxbq -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{F,VL}
vpmovzxbq 508(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovzxbq 512(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxbq -512(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovzxbq -516(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxwd %xmm5, %xmm6{%k7} # AVX512{F,VL}
vpmovzxwd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vpmovzxwd (%ecx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxwd -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
vpmovzxwd 1016(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovzxwd 1024(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxwd -1024(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovzxwd -1032(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxwd %xmm5, %ymm6{%k7} # AVX512{F,VL}
vpmovzxwd %xmm5, %ymm6{%k7}{z} # AVX512{F,VL}
vpmovzxwd (%ecx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxwd -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{F,VL}
vpmovzxwd 2032(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovzxwd 2048(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxwd -2048(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovzxwd -2064(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxwq %xmm5, %xmm6{%k7} # AVX512{F,VL}
vpmovzxwq %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vpmovzxwq (%ecx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxwq -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
vpmovzxwq 508(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovzxwq 512(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxwq -512(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vpmovzxwq -516(%edx), %xmm6{%k7} # AVX512{F,VL}
vpmovzxwq %xmm5, %ymm6{%k7} # AVX512{F,VL}
vpmovzxwq %xmm5, %ymm6{%k7}{z} # AVX512{F,VL}
vpmovzxwq (%ecx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxwq -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{F,VL}
vpmovzxwq 1016(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovzxwq 1024(%edx), %ymm6{%k7} # AVX512{F,VL}
vpmovzxwq -1024(%edx), %ymm6{%k7} # AVX512{F,VL} Disp8
vpmovzxwq -1032(%edx), %ymm6{%k7} # AVX512{F,VL}
.intel_syntax noprefix
vpmovsxbd xmm6{k7}, xmm5 # AVX512{F,VL}
vpmovsxbd xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovsxbd xmm6{k7}, DWORD PTR [ecx] # AVX512{F,VL}
vpmovsxbd xmm6{k7}, DWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovsxbd xmm6{k7}, DWORD PTR [edx+508] # AVX512{F,VL} Disp8
vpmovsxbd xmm6{k7}, DWORD PTR [edx+512] # AVX512{F,VL}
vpmovsxbd xmm6{k7}, DWORD PTR [edx-512] # AVX512{F,VL} Disp8
vpmovsxbd xmm6{k7}, DWORD PTR [edx-516] # AVX512{F,VL}
vpmovsxbd ymm6{k7}, xmm5 # AVX512{F,VL}
vpmovsxbd ymm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovsxbd ymm6{k7}, QWORD PTR [ecx] # AVX512{F,VL}
vpmovsxbd ymm6{k7}, QWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovsxbd ymm6{k7}, QWORD PTR [edx+1016] # AVX512{F,VL} Disp8
vpmovsxbd ymm6{k7}, QWORD PTR [edx+1024] # AVX512{F,VL}
vpmovsxbd ymm6{k7}, QWORD PTR [edx-1024] # AVX512{F,VL} Disp8
vpmovsxbd ymm6{k7}, QWORD PTR [edx-1032] # AVX512{F,VL}
vpmovsxbq xmm6{k7}, xmm5 # AVX512{F,VL}
vpmovsxbq xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovsxbq xmm6{k7}, WORD PTR [ecx] # AVX512{F,VL}
vpmovsxbq xmm6{k7}, WORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovsxbq xmm6{k7}, WORD PTR [edx+254] # AVX512{F,VL} Disp8
vpmovsxbq xmm6{k7}, WORD PTR [edx+256] # AVX512{F,VL}
vpmovsxbq xmm6{k7}, WORD PTR [edx-256] # AVX512{F,VL} Disp8
vpmovsxbq xmm6{k7}, WORD PTR [edx-258] # AVX512{F,VL}
vpmovsxbq ymm6{k7}, xmm5 # AVX512{F,VL}
vpmovsxbq ymm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovsxbq ymm6{k7}, DWORD PTR [ecx] # AVX512{F,VL}
vpmovsxbq ymm6{k7}, DWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovsxbq ymm6{k7}, DWORD PTR [edx+508] # AVX512{F,VL} Disp8
vpmovsxbq ymm6{k7}, DWORD PTR [edx+512] # AVX512{F,VL}
vpmovsxbq ymm6{k7}, DWORD PTR [edx-512] # AVX512{F,VL} Disp8
vpmovsxbq ymm6{k7}, DWORD PTR [edx-516] # AVX512{F,VL}
vpmovsxwd xmm6{k7}, xmm5 # AVX512{F,VL}
vpmovsxwd xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovsxwd xmm6{k7}, QWORD PTR [ecx] # AVX512{F,VL}
vpmovsxwd xmm6{k7}, QWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovsxwd xmm6{k7}, QWORD PTR [edx+1016] # AVX512{F,VL} Disp8
vpmovsxwd xmm6{k7}, QWORD PTR [edx+1024] # AVX512{F,VL}
vpmovsxwd xmm6{k7}, QWORD PTR [edx-1024] # AVX512{F,VL} Disp8
vpmovsxwd xmm6{k7}, QWORD PTR [edx-1032] # AVX512{F,VL}
vpmovsxwd ymm6{k7}, xmm5 # AVX512{F,VL}
vpmovsxwd ymm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovsxwd ymm6{k7}, XMMWORD PTR [ecx] # AVX512{F,VL}
vpmovsxwd ymm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovsxwd ymm6{k7}, XMMWORD PTR [edx+2032] # AVX512{F,VL} Disp8
vpmovsxwd ymm6{k7}, XMMWORD PTR [edx+2048] # AVX512{F,VL}
vpmovsxwd ymm6{k7}, XMMWORD PTR [edx-2048] # AVX512{F,VL} Disp8
vpmovsxwd ymm6{k7}, XMMWORD PTR [edx-2064] # AVX512{F,VL}
vpmovsxwq xmm6{k7}, xmm5 # AVX512{F,VL}
vpmovsxwq xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovsxwq xmm6{k7}, DWORD PTR [ecx] # AVX512{F,VL}
vpmovsxwq xmm6{k7}, DWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovsxwq xmm6{k7}, DWORD PTR [edx+508] # AVX512{F,VL} Disp8
vpmovsxwq xmm6{k7}, DWORD PTR [edx+512] # AVX512{F,VL}
vpmovsxwq xmm6{k7}, DWORD PTR [edx-512] # AVX512{F,VL} Disp8
vpmovsxwq xmm6{k7}, DWORD PTR [edx-516] # AVX512{F,VL}
vpmovsxwq ymm6{k7}, xmm5 # AVX512{F,VL}
vpmovsxwq ymm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovsxwq ymm6{k7}, QWORD PTR [ecx] # AVX512{F,VL}
vpmovsxwq ymm6{k7}, QWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovsxwq ymm6{k7}, QWORD PTR [edx+1016] # AVX512{F,VL} Disp8
vpmovsxwq ymm6{k7}, QWORD PTR [edx+1024] # AVX512{F,VL}
vpmovsxwq ymm6{k7}, QWORD PTR [edx-1024] # AVX512{F,VL} Disp8
vpmovsxwq ymm6{k7}, QWORD PTR [edx-1032] # AVX512{F,VL}
vpmovzxbd xmm6{k7}, xmm5 # AVX512{F,VL}
vpmovzxbd xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovzxbd xmm6{k7}, DWORD PTR [ecx] # AVX512{F,VL}
vpmovzxbd xmm6{k7}, DWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovzxbd xmm6{k7}, DWORD PTR [edx+508] # AVX512{F,VL} Disp8
vpmovzxbd xmm6{k7}, DWORD PTR [edx+512] # AVX512{F,VL}
vpmovzxbd xmm6{k7}, DWORD PTR [edx-512] # AVX512{F,VL} Disp8
vpmovzxbd xmm6{k7}, DWORD PTR [edx-516] # AVX512{F,VL}
vpmovzxbd ymm6{k7}, xmm5 # AVX512{F,VL}
vpmovzxbd ymm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovzxbd ymm6{k7}, QWORD PTR [ecx] # AVX512{F,VL}
vpmovzxbd ymm6{k7}, QWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovzxbd ymm6{k7}, QWORD PTR [edx+1016] # AVX512{F,VL} Disp8
vpmovzxbd ymm6{k7}, QWORD PTR [edx+1024] # AVX512{F,VL}
vpmovzxbd ymm6{k7}, QWORD PTR [edx-1024] # AVX512{F,VL} Disp8
vpmovzxbd ymm6{k7}, QWORD PTR [edx-1032] # AVX512{F,VL}
vpmovzxbq xmm6{k7}, xmm5 # AVX512{F,VL}
vpmovzxbq xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovzxbq xmm6{k7}, WORD PTR [ecx] # AVX512{F,VL}
vpmovzxbq xmm6{k7}, WORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovzxbq xmm6{k7}, WORD PTR [edx+254] # AVX512{F,VL} Disp8
vpmovzxbq xmm6{k7}, WORD PTR [edx+256] # AVX512{F,VL}
vpmovzxbq xmm6{k7}, WORD PTR [edx-256] # AVX512{F,VL} Disp8
vpmovzxbq xmm6{k7}, WORD PTR [edx-258] # AVX512{F,VL}
vpmovzxbq ymm6{k7}, xmm5 # AVX512{F,VL}
vpmovzxbq ymm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovzxbq ymm6{k7}, DWORD PTR [ecx] # AVX512{F,VL}
vpmovzxbq ymm6{k7}, DWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovzxbq ymm6{k7}, DWORD PTR [edx+508] # AVX512{F,VL} Disp8
vpmovzxbq ymm6{k7}, DWORD PTR [edx+512] # AVX512{F,VL}
vpmovzxbq ymm6{k7}, DWORD PTR [edx-512] # AVX512{F,VL} Disp8
vpmovzxbq ymm6{k7}, DWORD PTR [edx-516] # AVX512{F,VL}
vpmovzxwd xmm6{k7}, xmm5 # AVX512{F,VL}
vpmovzxwd xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovzxwd xmm6{k7}, QWORD PTR [ecx] # AVX512{F,VL}
vpmovzxwd xmm6{k7}, QWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovzxwd xmm6{k7}, QWORD PTR [edx+1016] # AVX512{F,VL} Disp8
vpmovzxwd xmm6{k7}, QWORD PTR [edx+1024] # AVX512{F,VL}
vpmovzxwd xmm6{k7}, QWORD PTR [edx-1024] # AVX512{F,VL} Disp8
vpmovzxwd xmm6{k7}, QWORD PTR [edx-1032] # AVX512{F,VL}
vpmovzxwd ymm6{k7}, xmm5 # AVX512{F,VL}
vpmovzxwd ymm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovzxwd ymm6{k7}, XMMWORD PTR [ecx] # AVX512{F,VL}
vpmovzxwd ymm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovzxwd ymm6{k7}, XMMWORD PTR [edx+2032] # AVX512{F,VL} Disp8
vpmovzxwd ymm6{k7}, XMMWORD PTR [edx+2048] # AVX512{F,VL}
vpmovzxwd ymm6{k7}, XMMWORD PTR [edx-2048] # AVX512{F,VL} Disp8
vpmovzxwd ymm6{k7}, XMMWORD PTR [edx-2064] # AVX512{F,VL}
vpmovzxwq xmm6{k7}, xmm5 # AVX512{F,VL}
vpmovzxwq xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovzxwq xmm6{k7}, DWORD PTR [ecx] # AVX512{F,VL}
vpmovzxwq xmm6{k7}, DWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovzxwq xmm6{k7}, DWORD PTR [edx+508] # AVX512{F,VL} Disp8
vpmovzxwq xmm6{k7}, DWORD PTR [edx+512] # AVX512{F,VL}
vpmovzxwq xmm6{k7}, DWORD PTR [edx-512] # AVX512{F,VL} Disp8
vpmovzxwq xmm6{k7}, DWORD PTR [edx-516] # AVX512{F,VL}
vpmovzxwq ymm6{k7}, xmm5 # AVX512{F,VL}
vpmovzxwq ymm6{k7}{z}, xmm5 # AVX512{F,VL}
vpmovzxwq ymm6{k7}, QWORD PTR [ecx] # AVX512{F,VL}
vpmovzxwq ymm6{k7}, QWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
vpmovzxwq ymm6{k7}, QWORD PTR [edx+1016] # AVX512{F,VL} Disp8
vpmovzxwq ymm6{k7}, QWORD PTR [edx+1024] # AVX512{F,VL}
vpmovzxwq ymm6{k7}, QWORD PTR [edx-1024] # AVX512{F,VL} Disp8
vpmovzxwq ymm6{k7}, QWORD PTR [edx-1032] # AVX512{F,VL}

268
gas/testsuite/gas/i386/avx512f_vl-wig1-intel.d Normal file
View file

@ -0,0 +1,268 @@
#as: -mevexwig=1
#objdump: -dw -Mintel
#name: i386 AVX512F/VL wig insns (Intel disassembly)
#source: avx512f_vl-wig.s
.*: +file format .*
Disassembly of section \.text:
00000000 <_start>:
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 f5[ ]*vpmovsxbd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 21 f5[ ]*vpmovsxbd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 31[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 7f[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 00 02 00 00[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 80[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 fc fd ff ff[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 f5[ ]*vpmovsxbd ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 21 f5[ ]*vpmovsxbd ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 31[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 72 7f[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b2 00 04 00 00[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 72 80[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b2 f8 fb ff ff[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 f5[ ]*vpmovsxbq xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 22 f5[ ]*vpmovsxbq xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 31[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b4 f4 c0 1d fe ff[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 72 7f[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[edx\+0xfe\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b2 00 01 00 00[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[edx\+0x100\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 72 80[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[edx-0x100\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b2 fe fe ff ff[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[edx-0x102\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 f5[ ]*vpmovsxbq ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 22 f5[ ]*vpmovsxbq ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 31[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b4 f4 c0 1d fe ff[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 72 7f[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b2 00 02 00 00[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 72 80[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b2 fc fd ff ff[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 f5[ ]*vpmovsxwd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 23 f5[ ]*vpmovsxwd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 31[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b4 f4 c0 1d fe ff[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 72 7f[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b2 00 04 00 00[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 72 80[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b2 f8 fb ff ff[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 f5[ ]*vpmovsxwd ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 23 f5[ ]*vpmovsxwd ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 31[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b4 f4 c0 1d fe ff[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 72 7f[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b2 00 08 00 00[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[edx\+0x800\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 72 80[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[edx-0x800\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b2 f0 f7 ff ff[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[edx-0x810\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 f5[ ]*vpmovsxwq xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 24 f5[ ]*vpmovsxwq xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 31[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b4 f4 c0 1d fe ff[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 72 7f[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b2 00 02 00 00[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 72 80[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b2 fc fd ff ff[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 f5[ ]*vpmovsxwq ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 24 f5[ ]*vpmovsxwq ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 31[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b4 f4 c0 1d fe ff[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 72 7f[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b2 00 04 00 00[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 72 80[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b2 f8 fb ff ff[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 f5[ ]*vpmovzxbd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 31 f5[ ]*vpmovzxbd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 31[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b4 f4 c0 1d fe ff[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 72 7f[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b2 00 02 00 00[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 72 80[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b2 fc fd ff ff[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 f5[ ]*vpmovzxbd ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 31 f5[ ]*vpmovzxbd ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 31[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b4 f4 c0 1d fe ff[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 72 7f[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b2 00 04 00 00[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 72 80[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b2 f8 fb ff ff[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 f5[ ]*vpmovzxbq xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 32 f5[ ]*vpmovzxbq xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 31[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b4 f4 c0 1d fe ff[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 72 7f[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[edx\+0xfe\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b2 00 01 00 00[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[edx\+0x100\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 72 80[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[edx-0x100\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b2 fe fe ff ff[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[edx-0x102\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 f5[ ]*vpmovzxbq ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 32 f5[ ]*vpmovzxbq ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 31[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b4 f4 c0 1d fe ff[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 72 7f[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b2 00 02 00 00[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 72 80[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b2 fc fd ff ff[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 f5[ ]*vpmovzxwd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 33 f5[ ]*vpmovzxwd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 31[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b4 f4 c0 1d fe ff[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 72 7f[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b2 00 04 00 00[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 72 80[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b2 f8 fb ff ff[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 f5[ ]*vpmovzxwd ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 33 f5[ ]*vpmovzxwd ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 31[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b4 f4 c0 1d fe ff[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 72 7f[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b2 00 08 00 00[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[edx\+0x800\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 72 80[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[edx-0x800\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b2 f0 f7 ff ff[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[edx-0x810\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 f5[ ]*vpmovzxwq xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 34 f5[ ]*vpmovzxwq xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 31[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b4 f4 c0 1d fe ff[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 72 7f[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b2 00 02 00 00[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 72 80[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b2 fc fd ff ff[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 f5[ ]*vpmovzxwq ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 34 f5[ ]*vpmovzxwq ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 31[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b4 f4 c0 1d fe ff[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 72 7f[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b2 00 04 00 00[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 72 80[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b2 f8 fb ff ff[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 f5[ ]*vpmovsxbd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 21 f5[ ]*vpmovsxbd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 31[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 7f[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 00 02 00 00[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 80[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 fc fd ff ff[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 f5[ ]*vpmovsxbd ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 21 f5[ ]*vpmovsxbd ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 31[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 72 7f[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b2 00 04 00 00[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 72 80[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b2 f8 fb ff ff[ ]*vpmovsxbd ymm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 f5[ ]*vpmovsxbq xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 22 f5[ ]*vpmovsxbq xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 31[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b4 f4 c0 1d fe ff[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 72 7f[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[edx\+0xfe\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b2 00 01 00 00[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[edx\+0x100\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 72 80[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[edx-0x100\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b2 fe fe ff ff[ ]*vpmovsxbq xmm6\{k7\},WORD PTR \[edx-0x102\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 f5[ ]*vpmovsxbq ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 22 f5[ ]*vpmovsxbq ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 31[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b4 f4 c0 1d fe ff[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 72 7f[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b2 00 02 00 00[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 72 80[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b2 fc fd ff ff[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 f5[ ]*vpmovsxwd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 23 f5[ ]*vpmovsxwd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 31[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b4 f4 c0 1d fe ff[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 72 7f[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b2 00 04 00 00[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 72 80[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b2 f8 fb ff ff[ ]*vpmovsxwd xmm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 f5[ ]*vpmovsxwd ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 23 f5[ ]*vpmovsxwd ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 31[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b4 f4 c0 1d fe ff[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 72 7f[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b2 00 08 00 00[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[edx\+0x800\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 72 80[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[edx-0x800\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b2 f0 f7 ff ff[ ]*vpmovsxwd ymm6\{k7\},XMMWORD PTR \[edx-0x810\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 f5[ ]*vpmovsxwq xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 24 f5[ ]*vpmovsxwq xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 31[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b4 f4 c0 1d fe ff[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 72 7f[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b2 00 02 00 00[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 72 80[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b2 fc fd ff ff[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 f5[ ]*vpmovsxwq ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 24 f5[ ]*vpmovsxwq ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 31[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b4 f4 c0 1d fe ff[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 72 7f[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b2 00 04 00 00[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 72 80[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b2 f8 fb ff ff[ ]*vpmovsxwq ymm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 f5[ ]*vpmovzxbd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 31 f5[ ]*vpmovzxbd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 31[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b4 f4 c0 1d fe ff[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 72 7f[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b2 00 02 00 00[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 72 80[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b2 fc fd ff ff[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 f5[ ]*vpmovzxbd ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 31 f5[ ]*vpmovzxbd ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 31[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b4 f4 c0 1d fe ff[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 72 7f[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b2 00 04 00 00[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 72 80[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b2 f8 fb ff ff[ ]*vpmovzxbd ymm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 f5[ ]*vpmovzxbq xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 32 f5[ ]*vpmovzxbq xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 31[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b4 f4 c0 1d fe ff[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 72 7f[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[edx\+0xfe\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b2 00 01 00 00[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[edx\+0x100\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 72 80[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[edx-0x100\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b2 fe fe ff ff[ ]*vpmovzxbq xmm6\{k7\},WORD PTR \[edx-0x102\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 f5[ ]*vpmovzxbq ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 32 f5[ ]*vpmovzxbq ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 31[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b4 f4 c0 1d fe ff[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 72 7f[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b2 00 02 00 00[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 72 80[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b2 fc fd ff ff[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 f5[ ]*vpmovzxwd xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 33 f5[ ]*vpmovzxwd xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 31[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b4 f4 c0 1d fe ff[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 72 7f[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b2 00 04 00 00[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 72 80[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b2 f8 fb ff ff[ ]*vpmovzxwd xmm6\{k7\},QWORD PTR \[edx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 f5[ ]*vpmovzxwd ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 33 f5[ ]*vpmovzxwd ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 31[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b4 f4 c0 1d fe ff[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 72 7f[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b2 00 08 00 00[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[edx\+0x800\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 72 80[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[edx-0x800\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b2 f0 f7 ff ff[ ]*vpmovzxwd ymm6\{k7\},XMMWORD PTR \[edx-0x810\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 f5[ ]*vpmovzxwq xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 34 f5[ ]*vpmovzxwq xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 31[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b4 f4 c0 1d fe ff[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 72 7f[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b2 00 02 00 00[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[edx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 72 80[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[edx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b2 fc fd ff ff[ ]*vpmovzxwq xmm6\{k7\},DWORD PTR \[edx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 f5[ ]*vpmovzxwq ymm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 34 f5[ ]*vpmovzxwq ymm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 31[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b4 f4 c0 1d fe ff[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 72 7f[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b2 00 04 00 00[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[edx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 72 80[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[edx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b2 f8 fb ff ff[ ]*vpmovzxwq ymm6\{k7\},QWORD PTR \[edx-0x408\]
#pass

268
gas/testsuite/gas/i386/avx512f_vl-wig1.d Normal file
View file

@ -0,0 +1,268 @@
#as: -mevexwig=1
#objdump: -dw
#name: i386 AVX512F/VL wig insns
#source: avx512f_vl-wig.s
.*: +file format .*
Disassembly of section \.text:
00000000 <_start>:
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 f5[ ]*vpmovsxbd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 21 f5[ ]*vpmovsxbd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 31[ ]*vpmovsxbd \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 7f[ ]*vpmovsxbd 0x1fc\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 00 02 00 00[ ]*vpmovsxbd 0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 80[ ]*vpmovsxbd -0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 fc fd ff ff[ ]*vpmovsxbd -0x204\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 f5[ ]*vpmovsxbd %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 21 f5[ ]*vpmovsxbd %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 31[ ]*vpmovsxbd \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 72 7f[ ]*vpmovsxbd 0x3f8\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b2 00 04 00 00[ ]*vpmovsxbd 0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 72 80[ ]*vpmovsxbd -0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b2 f8 fb ff ff[ ]*vpmovsxbd -0x408\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 f5[ ]*vpmovsxbq %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 22 f5[ ]*vpmovsxbq %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 31[ ]*vpmovsxbq \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b4 f4 c0 1d fe ff[ ]*vpmovsxbq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 72 7f[ ]*vpmovsxbq 0xfe\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b2 00 01 00 00[ ]*vpmovsxbq 0x100\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 72 80[ ]*vpmovsxbq -0x100\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b2 fe fe ff ff[ ]*vpmovsxbq -0x102\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 f5[ ]*vpmovsxbq %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 22 f5[ ]*vpmovsxbq %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 31[ ]*vpmovsxbq \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b4 f4 c0 1d fe ff[ ]*vpmovsxbq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 72 7f[ ]*vpmovsxbq 0x1fc\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b2 00 02 00 00[ ]*vpmovsxbq 0x200\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 72 80[ ]*vpmovsxbq -0x200\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b2 fc fd ff ff[ ]*vpmovsxbq -0x204\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 f5[ ]*vpmovsxwd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 23 f5[ ]*vpmovsxwd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 31[ ]*vpmovsxwd \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b4 f4 c0 1d fe ff[ ]*vpmovsxwd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 72 7f[ ]*vpmovsxwd 0x3f8\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b2 00 04 00 00[ ]*vpmovsxwd 0x400\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 72 80[ ]*vpmovsxwd -0x400\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b2 f8 fb ff ff[ ]*vpmovsxwd -0x408\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 f5[ ]*vpmovsxwd %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 23 f5[ ]*vpmovsxwd %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 31[ ]*vpmovsxwd \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b4 f4 c0 1d fe ff[ ]*vpmovsxwd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 72 7f[ ]*vpmovsxwd 0x7f0\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b2 00 08 00 00[ ]*vpmovsxwd 0x800\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 72 80[ ]*vpmovsxwd -0x800\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b2 f0 f7 ff ff[ ]*vpmovsxwd -0x810\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 f5[ ]*vpmovsxwq %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 24 f5[ ]*vpmovsxwq %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 31[ ]*vpmovsxwq \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b4 f4 c0 1d fe ff[ ]*vpmovsxwq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 72 7f[ ]*vpmovsxwq 0x1fc\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b2 00 02 00 00[ ]*vpmovsxwq 0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 72 80[ ]*vpmovsxwq -0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b2 fc fd ff ff[ ]*vpmovsxwq -0x204\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 f5[ ]*vpmovsxwq %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 24 f5[ ]*vpmovsxwq %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 31[ ]*vpmovsxwq \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b4 f4 c0 1d fe ff[ ]*vpmovsxwq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 72 7f[ ]*vpmovsxwq 0x3f8\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b2 00 04 00 00[ ]*vpmovsxwq 0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 72 80[ ]*vpmovsxwq -0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b2 f8 fb ff ff[ ]*vpmovsxwq -0x408\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 f5[ ]*vpmovzxbd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 31 f5[ ]*vpmovzxbd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 31[ ]*vpmovzxbd \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b4 f4 c0 1d fe ff[ ]*vpmovzxbd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 72 7f[ ]*vpmovzxbd 0x1fc\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b2 00 02 00 00[ ]*vpmovzxbd 0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 72 80[ ]*vpmovzxbd -0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b2 fc fd ff ff[ ]*vpmovzxbd -0x204\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 f5[ ]*vpmovzxbd %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 31 f5[ ]*vpmovzxbd %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 31[ ]*vpmovzxbd \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b4 f4 c0 1d fe ff[ ]*vpmovzxbd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 72 7f[ ]*vpmovzxbd 0x3f8\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b2 00 04 00 00[ ]*vpmovzxbd 0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 72 80[ ]*vpmovzxbd -0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b2 f8 fb ff ff[ ]*vpmovzxbd -0x408\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 f5[ ]*vpmovzxbq %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 32 f5[ ]*vpmovzxbq %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 31[ ]*vpmovzxbq \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b4 f4 c0 1d fe ff[ ]*vpmovzxbq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 72 7f[ ]*vpmovzxbq 0xfe\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b2 00 01 00 00[ ]*vpmovzxbq 0x100\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 72 80[ ]*vpmovzxbq -0x100\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b2 fe fe ff ff[ ]*vpmovzxbq -0x102\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 f5[ ]*vpmovzxbq %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 32 f5[ ]*vpmovzxbq %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 31[ ]*vpmovzxbq \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b4 f4 c0 1d fe ff[ ]*vpmovzxbq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 72 7f[ ]*vpmovzxbq 0x1fc\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b2 00 02 00 00[ ]*vpmovzxbq 0x200\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 72 80[ ]*vpmovzxbq -0x200\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b2 fc fd ff ff[ ]*vpmovzxbq -0x204\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 f5[ ]*vpmovzxwd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 33 f5[ ]*vpmovzxwd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 31[ ]*vpmovzxwd \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b4 f4 c0 1d fe ff[ ]*vpmovzxwd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 72 7f[ ]*vpmovzxwd 0x3f8\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b2 00 04 00 00[ ]*vpmovzxwd 0x400\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 72 80[ ]*vpmovzxwd -0x400\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b2 f8 fb ff ff[ ]*vpmovzxwd -0x408\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 f5[ ]*vpmovzxwd %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 33 f5[ ]*vpmovzxwd %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 31[ ]*vpmovzxwd \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b4 f4 c0 1d fe ff[ ]*vpmovzxwd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 72 7f[ ]*vpmovzxwd 0x7f0\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b2 00 08 00 00[ ]*vpmovzxwd 0x800\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 72 80[ ]*vpmovzxwd -0x800\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b2 f0 f7 ff ff[ ]*vpmovzxwd -0x810\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 f5[ ]*vpmovzxwq %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 34 f5[ ]*vpmovzxwq %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 31[ ]*vpmovzxwq \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b4 f4 c0 1d fe ff[ ]*vpmovzxwq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 72 7f[ ]*vpmovzxwq 0x1fc\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b2 00 02 00 00[ ]*vpmovzxwq 0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 72 80[ ]*vpmovzxwq -0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b2 fc fd ff ff[ ]*vpmovzxwq -0x204\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 f5[ ]*vpmovzxwq %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 34 f5[ ]*vpmovzxwq %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 31[ ]*vpmovzxwq \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b4 f4 c0 1d fe ff[ ]*vpmovzxwq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 72 7f[ ]*vpmovzxwq 0x3f8\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b2 00 04 00 00[ ]*vpmovzxwq 0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 72 80[ ]*vpmovzxwq -0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b2 f8 fb ff ff[ ]*vpmovzxwq -0x408\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 f5[ ]*vpmovsxbd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 21 f5[ ]*vpmovsxbd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 31[ ]*vpmovsxbd \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 7f[ ]*vpmovsxbd 0x1fc\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 00 02 00 00[ ]*vpmovsxbd 0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 80[ ]*vpmovsxbd -0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 fc fd ff ff[ ]*vpmovsxbd -0x204\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 f5[ ]*vpmovsxbd %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 21 f5[ ]*vpmovsxbd %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 31[ ]*vpmovsxbd \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 72 7f[ ]*vpmovsxbd 0x3f8\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b2 00 04 00 00[ ]*vpmovsxbd 0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 72 80[ ]*vpmovsxbd -0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 b2 f8 fb ff ff[ ]*vpmovsxbd -0x408\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 f5[ ]*vpmovsxbq %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 22 f5[ ]*vpmovsxbq %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 31[ ]*vpmovsxbq \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b4 f4 c0 1d fe ff[ ]*vpmovsxbq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 72 7f[ ]*vpmovsxbq 0xfe\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b2 00 01 00 00[ ]*vpmovsxbq 0x100\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 72 80[ ]*vpmovsxbq -0x100\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 22 b2 fe fe ff ff[ ]*vpmovsxbq -0x102\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 f5[ ]*vpmovsxbq %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 22 f5[ ]*vpmovsxbq %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 31[ ]*vpmovsxbq \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b4 f4 c0 1d fe ff[ ]*vpmovsxbq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 72 7f[ ]*vpmovsxbq 0x1fc\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b2 00 02 00 00[ ]*vpmovsxbq 0x200\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 72 80[ ]*vpmovsxbq -0x200\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b2 fc fd ff ff[ ]*vpmovsxbq -0x204\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 f5[ ]*vpmovsxwd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 23 f5[ ]*vpmovsxwd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 31[ ]*vpmovsxwd \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b4 f4 c0 1d fe ff[ ]*vpmovsxwd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 72 7f[ ]*vpmovsxwd 0x3f8\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b2 00 04 00 00[ ]*vpmovsxwd 0x400\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 72 80[ ]*vpmovsxwd -0x400\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 23 b2 f8 fb ff ff[ ]*vpmovsxwd -0x408\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 f5[ ]*vpmovsxwd %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 23 f5[ ]*vpmovsxwd %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 31[ ]*vpmovsxwd \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b4 f4 c0 1d fe ff[ ]*vpmovsxwd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 72 7f[ ]*vpmovsxwd 0x7f0\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b2 00 08 00 00[ ]*vpmovsxwd 0x800\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 72 80[ ]*vpmovsxwd -0x800\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 23 b2 f0 f7 ff ff[ ]*vpmovsxwd -0x810\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 f5[ ]*vpmovsxwq %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 24 f5[ ]*vpmovsxwq %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 31[ ]*vpmovsxwq \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b4 f4 c0 1d fe ff[ ]*vpmovsxwq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 72 7f[ ]*vpmovsxwq 0x1fc\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b2 00 02 00 00[ ]*vpmovsxwq 0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 72 80[ ]*vpmovsxwq -0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b2 fc fd ff ff[ ]*vpmovsxwq -0x204\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 f5[ ]*vpmovsxwq %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 24 f5[ ]*vpmovsxwq %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 31[ ]*vpmovsxwq \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b4 f4 c0 1d fe ff[ ]*vpmovsxwq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 72 7f[ ]*vpmovsxwq 0x3f8\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b2 00 04 00 00[ ]*vpmovsxwq 0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 72 80[ ]*vpmovsxwq -0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 24 b2 f8 fb ff ff[ ]*vpmovsxwq -0x408\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 f5[ ]*vpmovzxbd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 31 f5[ ]*vpmovzxbd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 31[ ]*vpmovzxbd \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b4 f4 c0 1d fe ff[ ]*vpmovzxbd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 72 7f[ ]*vpmovzxbd 0x1fc\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b2 00 02 00 00[ ]*vpmovzxbd 0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 72 80[ ]*vpmovzxbd -0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b2 fc fd ff ff[ ]*vpmovzxbd -0x204\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 f5[ ]*vpmovzxbd %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 31 f5[ ]*vpmovzxbd %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 31[ ]*vpmovzxbd \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b4 f4 c0 1d fe ff[ ]*vpmovzxbd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 72 7f[ ]*vpmovzxbd 0x3f8\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b2 00 04 00 00[ ]*vpmovzxbd 0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 72 80[ ]*vpmovzxbd -0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 31 b2 f8 fb ff ff[ ]*vpmovzxbd -0x408\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 f5[ ]*vpmovzxbq %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 32 f5[ ]*vpmovzxbq %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 31[ ]*vpmovzxbq \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b4 f4 c0 1d fe ff[ ]*vpmovzxbq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 72 7f[ ]*vpmovzxbq 0xfe\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b2 00 01 00 00[ ]*vpmovzxbq 0x100\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 72 80[ ]*vpmovzxbq -0x100\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 32 b2 fe fe ff ff[ ]*vpmovzxbq -0x102\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 f5[ ]*vpmovzxbq %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 32 f5[ ]*vpmovzxbq %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 31[ ]*vpmovzxbq \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b4 f4 c0 1d fe ff[ ]*vpmovzxbq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 72 7f[ ]*vpmovzxbq 0x1fc\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b2 00 02 00 00[ ]*vpmovzxbq 0x200\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 72 80[ ]*vpmovzxbq -0x200\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b2 fc fd ff ff[ ]*vpmovzxbq -0x204\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 f5[ ]*vpmovzxwd %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 33 f5[ ]*vpmovzxwd %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 31[ ]*vpmovzxwd \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b4 f4 c0 1d fe ff[ ]*vpmovzxwd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 72 7f[ ]*vpmovzxwd 0x3f8\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b2 00 04 00 00[ ]*vpmovzxwd 0x400\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 72 80[ ]*vpmovzxwd -0x400\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 33 b2 f8 fb ff ff[ ]*vpmovzxwd -0x408\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 f5[ ]*vpmovzxwd %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 33 f5[ ]*vpmovzxwd %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 31[ ]*vpmovzxwd \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b4 f4 c0 1d fe ff[ ]*vpmovzxwd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 72 7f[ ]*vpmovzxwd 0x7f0\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b2 00 08 00 00[ ]*vpmovzxwd 0x800\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 72 80[ ]*vpmovzxwd -0x800\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 33 b2 f0 f7 ff ff[ ]*vpmovzxwd -0x810\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 f5[ ]*vpmovzxwq %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 34 f5[ ]*vpmovzxwq %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 31[ ]*vpmovzxwq \(%ecx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b4 f4 c0 1d fe ff[ ]*vpmovzxwq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 72 7f[ ]*vpmovzxwq 0x1fc\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b2 00 02 00 00[ ]*vpmovzxwq 0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 72 80[ ]*vpmovzxwq -0x200\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 34 b2 fc fd ff ff[ ]*vpmovzxwq -0x204\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 f5[ ]*vpmovzxwq %xmm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 34 f5[ ]*vpmovzxwq %xmm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 31[ ]*vpmovzxwq \(%ecx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b4 f4 c0 1d fe ff[ ]*vpmovzxwq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 72 7f[ ]*vpmovzxwq 0x3f8\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b2 00 04 00 00[ ]*vpmovzxwq 0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 72 80[ ]*vpmovzxwq -0x400\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 34 b2 f8 fb ff ff[ ]*vpmovzxwq -0x408\(%edx\),%ymm6\{%k7\}
#pass

11402
gas/testsuite/gas/i386/avx512f_vl.d Normal file
View file

File diff suppressed because it is too large Load diff

11397
gas/testsuite/gas/i386/avx512f_vl.s Normal file
View file

File diff suppressed because it is too large Load diff

12
gas/testsuite/gas/i386/i386.exp
View file

@ -277,6 +277,12 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "prefetchwt1"
run_dump_test "prefetchwt1-intel"
run_dump_test "se1"
run_dump_test "avx512f_vl-intel"
run_dump_test "avx512f_vl-opts-intel"
run_dump_test "avx512f_vl-opts"
run_dump_test "avx512f_vl-wig1-intel"
run_dump_test "avx512f_vl-wig1"
run_dump_test "avx512f_vl"
run_dump_test "disassem"
# These tests require support for 8 and 16 bit relocs,
@ -577,6 +583,12 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-prefetchwt1-intel"
run_dump_test "x86-64-se1"
run_dump_test "x86-64-equ"
run_dump_test "x86-64-avx512f_vl-intel"
run_dump_test "x86-64-avx512f_vl-opts-intel"
run_dump_test "x86-64-avx512f_vl-opts"
run_dump_test "x86-64-avx512f_vl-wig1-intel"
run_dump_test "x86-64-avx512f_vl-wig1"
run_dump_test "x86-64-avx512f_vl"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]

12626
gas/testsuite/gas/i386/x86-64-avx512f_vl-intel.d Normal file
View file

File diff suppressed because it is too large Load diff

396
gas/testsuite/gas/i386/x86-64-avx512f_vl-opts-intel.d Normal file
View file

@ -0,0 +1,396 @@
#as:
#objdump: -dw -Mintel -Msuffix
#name: x86_64 AVX512F/VL opts insns (Intel disassembly)
#source: x86-64-avx512f_vl-opts.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 28 f5[ ]*vmovapd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 29 ee[ ]*vmovapd\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 28 f5[ ]*vmovapd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 29 ee[ ]*vmovapd\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 28 f5[ ]*vmovapd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 29 ee[ ]*vmovapd\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 28 f5[ ]*vmovapd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 29 ee[ ]*vmovapd\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 28 f5[ ]*vmovapd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 29 ee[ ]*vmovapd\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 28 f5[ ]*vmovapd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 29 ee[ ]*vmovapd\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 28 f5[ ]*vmovapd ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 29 ee[ ]*vmovapd\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 28 f5[ ]*vmovapd ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 29 ee[ ]*vmovapd\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 28 f5[ ]*vmovapd ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 29 ee[ ]*vmovapd\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 28 f5[ ]*vmovapd ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 29 ee[ ]*vmovapd\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 28 f5[ ]*vmovapd ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 29 ee[ ]*vmovapd\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 28 f5[ ]*vmovapd ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 29 ee[ ]*vmovapd\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 28 f5[ ]*vmovaps xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 29 ee[ ]*vmovaps\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 28 f5[ ]*vmovaps xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 29 ee[ ]*vmovaps\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 28 f5[ ]*vmovaps xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 29 ee[ ]*vmovaps\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 28 f5[ ]*vmovaps xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 29 ee[ ]*vmovaps\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 28 f5[ ]*vmovaps xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 29 ee[ ]*vmovaps\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 28 f5[ ]*vmovaps xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 29 ee[ ]*vmovaps\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 28 f5[ ]*vmovaps ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 29 ee[ ]*vmovaps\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 28 f5[ ]*vmovaps ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 29 ee[ ]*vmovaps\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 28 f5[ ]*vmovaps ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 29 ee[ ]*vmovaps\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 28 f5[ ]*vmovaps ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 29 ee[ ]*vmovaps\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 28 f5[ ]*vmovaps ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 29 ee[ ]*vmovaps\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 28 f5[ ]*vmovaps ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 29 ee[ ]*vmovaps\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 6f f5[ ]*vmovdqa32 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 7f ee[ ]*vmovdqa32\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 6f f5[ ]*vmovdqa32 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 7f ee[ ]*vmovdqa32\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 6f f5[ ]*vmovdqa32 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 7f ee[ ]*vmovdqa32\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 6f f5[ ]*vmovdqa32 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 7f ee[ ]*vmovdqa32\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 6f f5[ ]*vmovdqa32 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 7f ee[ ]*vmovdqa32\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 6f f5[ ]*vmovdqa32 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 7f ee[ ]*vmovdqa32\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 6f f5[ ]*vmovdqa32 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 7f ee[ ]*vmovdqa32\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 6f f5[ ]*vmovdqa32 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 7f ee[ ]*vmovdqa32\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d af 6f f5[ ]*vmovdqa32 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d af 7f ee[ ]*vmovdqa32\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 6f f5[ ]*vmovdqa32 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 7f ee[ ]*vmovdqa32\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 6f f5[ ]*vmovdqa32 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 7f ee[ ]*vmovdqa32\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d af 6f f5[ ]*vmovdqa32 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d af 7f ee[ ]*vmovdqa32\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 6f f5[ ]*vmovdqa64 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 7f ee[ ]*vmovdqa64\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 6f f5[ ]*vmovdqa64 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 7f ee[ ]*vmovdqa64\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 6f f5[ ]*vmovdqa64 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 7f ee[ ]*vmovdqa64\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 6f f5[ ]*vmovdqa64 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 7f ee[ ]*vmovdqa64\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 6f f5[ ]*vmovdqa64 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 7f ee[ ]*vmovdqa64\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 6f f5[ ]*vmovdqa64 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 7f ee[ ]*vmovdqa64\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 6f f5[ ]*vmovdqa64 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 7f ee[ ]*vmovdqa64\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 6f f5[ ]*vmovdqa64 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 7f ee[ ]*vmovdqa64\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 6f f5[ ]*vmovdqa64 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 7f ee[ ]*vmovdqa64\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 6f f5[ ]*vmovdqa64 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 7f ee[ ]*vmovdqa64\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 6f f5[ ]*vmovdqa64 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 7f ee[ ]*vmovdqa64\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 6f f5[ ]*vmovdqa64 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 7f ee[ ]*vmovdqa64\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 6f f5[ ]*vmovdqu32 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 7f ee[ ]*vmovdqu32\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 6f f5[ ]*vmovdqu32 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 7f ee[ ]*vmovdqu32\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 6f f5[ ]*vmovdqu32 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 7f ee[ ]*vmovdqu32\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 6f f5[ ]*vmovdqu32 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 7f ee[ ]*vmovdqu32\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 6f f5[ ]*vmovdqu32 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 7f ee[ ]*vmovdqu32\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 6f f5[ ]*vmovdqu32 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 7f ee[ ]*vmovdqu32\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 6f f5[ ]*vmovdqu32 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 7f ee[ ]*vmovdqu32\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 6f f5[ ]*vmovdqu32 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 7f ee[ ]*vmovdqu32\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e af 6f f5[ ]*vmovdqu32 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e af 7f ee[ ]*vmovdqu32\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 6f f5[ ]*vmovdqu32 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 7f ee[ ]*vmovdqu32\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 6f f5[ ]*vmovdqu32 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 7f ee[ ]*vmovdqu32\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e af 6f f5[ ]*vmovdqu32 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e af 7f ee[ ]*vmovdqu32\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 6f f5[ ]*vmovdqu64 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 7f ee[ ]*vmovdqu64\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 6f f5[ ]*vmovdqu64 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 7f ee[ ]*vmovdqu64\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 6f f5[ ]*vmovdqu64 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 7f ee[ ]*vmovdqu64\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 6f f5[ ]*vmovdqu64 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 7f ee[ ]*vmovdqu64\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 6f f5[ ]*vmovdqu64 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 7f ee[ ]*vmovdqu64\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 6f f5[ ]*vmovdqu64 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 7f ee[ ]*vmovdqu64\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 6f f5[ ]*vmovdqu64 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 7f ee[ ]*vmovdqu64\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 6f f5[ ]*vmovdqu64 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 7f ee[ ]*vmovdqu64\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe af 6f f5[ ]*vmovdqu64 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe af 7f ee[ ]*vmovdqu64\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 6f f5[ ]*vmovdqu64 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 7f ee[ ]*vmovdqu64\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 6f f5[ ]*vmovdqu64 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 7f ee[ ]*vmovdqu64\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe af 6f f5[ ]*vmovdqu64 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe af 7f ee[ ]*vmovdqu64\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 10 f5[ ]*vmovupd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 11 ee[ ]*vmovupd\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 10 f5[ ]*vmovupd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 11 ee[ ]*vmovupd\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 10 f5[ ]*vmovupd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 11 ee[ ]*vmovupd\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 10 f5[ ]*vmovupd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 11 ee[ ]*vmovupd\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 10 f5[ ]*vmovupd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 11 ee[ ]*vmovupd\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 10 f5[ ]*vmovupd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 11 ee[ ]*vmovupd\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 10 f5[ ]*vmovupd ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 11 ee[ ]*vmovupd\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 10 f5[ ]*vmovupd ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 11 ee[ ]*vmovupd\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 10 f5[ ]*vmovupd ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 11 ee[ ]*vmovupd\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 10 f5[ ]*vmovupd ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 11 ee[ ]*vmovupd\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 10 f5[ ]*vmovupd ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 11 ee[ ]*vmovupd\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 10 f5[ ]*vmovupd ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 11 ee[ ]*vmovupd\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 10 f5[ ]*vmovups xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 11 ee[ ]*vmovups\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 10 f5[ ]*vmovups xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 11 ee[ ]*vmovups\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 10 f5[ ]*vmovups xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 11 ee[ ]*vmovups\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 10 f5[ ]*vmovups xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 11 ee[ ]*vmovups\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 10 f5[ ]*vmovups xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 11 ee[ ]*vmovups\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 10 f5[ ]*vmovups xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 11 ee[ ]*vmovups\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 10 f5[ ]*vmovups ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 11 ee[ ]*vmovups\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 10 f5[ ]*vmovups ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 11 ee[ ]*vmovups\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 10 f5[ ]*vmovups ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 11 ee[ ]*vmovups\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 10 f5[ ]*vmovups ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 11 ee[ ]*vmovups\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 10 f5[ ]*vmovups ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 11 ee[ ]*vmovups\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 10 f5[ ]*vmovups ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 11 ee[ ]*vmovups\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 28 f5[ ]*vmovapd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 29 ee[ ]*vmovapd\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 28 f5[ ]*vmovapd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 29 ee[ ]*vmovapd\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 28 f5[ ]*vmovapd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 29 ee[ ]*vmovapd\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 28 f5[ ]*vmovapd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 29 ee[ ]*vmovapd\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 28 f5[ ]*vmovapd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 29 ee[ ]*vmovapd\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 28 f5[ ]*vmovapd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 29 ee[ ]*vmovapd\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 28 f5[ ]*vmovapd ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 29 ee[ ]*vmovapd\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 28 f5[ ]*vmovapd ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 29 ee[ ]*vmovapd\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 28 f5[ ]*vmovapd ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 29 ee[ ]*vmovapd\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 28 f5[ ]*vmovapd ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 29 ee[ ]*vmovapd\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 28 f5[ ]*vmovapd ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 29 ee[ ]*vmovapd\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 28 f5[ ]*vmovapd ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 29 ee[ ]*vmovapd\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 28 f5[ ]*vmovaps xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 29 ee[ ]*vmovaps\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 28 f5[ ]*vmovaps xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 29 ee[ ]*vmovaps\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 28 f5[ ]*vmovaps xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 29 ee[ ]*vmovaps\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 28 f5[ ]*vmovaps xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 29 ee[ ]*vmovaps\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 28 f5[ ]*vmovaps xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 29 ee[ ]*vmovaps\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 28 f5[ ]*vmovaps xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 29 ee[ ]*vmovaps\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 28 f5[ ]*vmovaps ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 29 ee[ ]*vmovaps\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 28 f5[ ]*vmovaps ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 29 ee[ ]*vmovaps\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 28 f5[ ]*vmovaps ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 29 ee[ ]*vmovaps\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 28 f5[ ]*vmovaps ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 29 ee[ ]*vmovaps\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 28 f5[ ]*vmovaps ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 29 ee[ ]*vmovaps\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 28 f5[ ]*vmovaps ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 29 ee[ ]*vmovaps\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 6f f5[ ]*vmovdqa32 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 7f ee[ ]*vmovdqa32\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 6f f5[ ]*vmovdqa32 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 7f ee[ ]*vmovdqa32\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 6f f5[ ]*vmovdqa32 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 7f ee[ ]*vmovdqa32\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 6f f5[ ]*vmovdqa32 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 7f ee[ ]*vmovdqa32\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 6f f5[ ]*vmovdqa32 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 7f ee[ ]*vmovdqa32\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 6f f5[ ]*vmovdqa32 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 7f ee[ ]*vmovdqa32\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 6f f5[ ]*vmovdqa32 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 7f ee[ ]*vmovdqa32\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 6f f5[ ]*vmovdqa32 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 7f ee[ ]*vmovdqa32\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d af 6f f5[ ]*vmovdqa32 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d af 7f ee[ ]*vmovdqa32\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 6f f5[ ]*vmovdqa32 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 7f ee[ ]*vmovdqa32\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 6f f5[ ]*vmovdqa32 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 7f ee[ ]*vmovdqa32\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d af 6f f5[ ]*vmovdqa32 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7d af 7f ee[ ]*vmovdqa32\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 6f f5[ ]*vmovdqa64 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 7f ee[ ]*vmovdqa64\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 6f f5[ ]*vmovdqa64 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 7f ee[ ]*vmovdqa64\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 6f f5[ ]*vmovdqa64 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 7f ee[ ]*vmovdqa64\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 6f f5[ ]*vmovdqa64 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 7f ee[ ]*vmovdqa64\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 6f f5[ ]*vmovdqa64 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 7f ee[ ]*vmovdqa64\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 6f f5[ ]*vmovdqa64 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 7f ee[ ]*vmovdqa64\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 6f f5[ ]*vmovdqa64 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 7f ee[ ]*vmovdqa64\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 6f f5[ ]*vmovdqa64 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 7f ee[ ]*vmovdqa64\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 6f f5[ ]*vmovdqa64 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 7f ee[ ]*vmovdqa64\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 6f f5[ ]*vmovdqa64 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 7f ee[ ]*vmovdqa64\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 6f f5[ ]*vmovdqa64 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 7f ee[ ]*vmovdqa64\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 6f f5[ ]*vmovdqa64 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 7f ee[ ]*vmovdqa64\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 6f f5[ ]*vmovdqu32 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 7f ee[ ]*vmovdqu32\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 6f f5[ ]*vmovdqu32 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 7f ee[ ]*vmovdqu32\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 6f f5[ ]*vmovdqu32 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 7f ee[ ]*vmovdqu32\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 6f f5[ ]*vmovdqu32 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 7f ee[ ]*vmovdqu32\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 6f f5[ ]*vmovdqu32 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 7f ee[ ]*vmovdqu32\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 6f f5[ ]*vmovdqu32 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 7f ee[ ]*vmovdqu32\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 6f f5[ ]*vmovdqu32 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 7f ee[ ]*vmovdqu32\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 6f f5[ ]*vmovdqu32 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 7f ee[ ]*vmovdqu32\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e af 6f f5[ ]*vmovdqu32 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e af 7f ee[ ]*vmovdqu32\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 6f f5[ ]*vmovdqu32 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 7f ee[ ]*vmovdqu32\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 6f f5[ ]*vmovdqu32 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 7f ee[ ]*vmovdqu32\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e af 6f f5[ ]*vmovdqu32 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7e af 7f ee[ ]*vmovdqu32\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 6f f5[ ]*vmovdqu64 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 7f ee[ ]*vmovdqu64\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 6f f5[ ]*vmovdqu64 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 7f ee[ ]*vmovdqu64\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 6f f5[ ]*vmovdqu64 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 7f ee[ ]*vmovdqu64\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 6f f5[ ]*vmovdqu64 xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 7f ee[ ]*vmovdqu64\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 6f f5[ ]*vmovdqu64 xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 7f ee[ ]*vmovdqu64\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 6f f5[ ]*vmovdqu64 xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 7f ee[ ]*vmovdqu64\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 6f f5[ ]*vmovdqu64 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 7f ee[ ]*vmovdqu64\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 6f f5[ ]*vmovdqu64 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 7f ee[ ]*vmovdqu64\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe af 6f f5[ ]*vmovdqu64 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe af 7f ee[ ]*vmovdqu64\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 6f f5[ ]*vmovdqu64 ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 7f ee[ ]*vmovdqu64\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 6f f5[ ]*vmovdqu64 ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 7f ee[ ]*vmovdqu64\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe af 6f f5[ ]*vmovdqu64 ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fe af 7f ee[ ]*vmovdqu64\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 10 f5[ ]*vmovupd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 11 ee[ ]*vmovupd\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 10 f5[ ]*vmovupd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 11 ee[ ]*vmovupd\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 10 f5[ ]*vmovupd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 11 ee[ ]*vmovupd\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 10 f5[ ]*vmovupd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 11 ee[ ]*vmovupd\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 10 f5[ ]*vmovupd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 11 ee[ ]*vmovupd\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 10 f5[ ]*vmovupd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 11 ee[ ]*vmovupd\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 10 f5[ ]*vmovupd ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 11 ee[ ]*vmovupd\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 10 f5[ ]*vmovupd ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 11 ee[ ]*vmovupd\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 10 f5[ ]*vmovupd ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 11 ee[ ]*vmovupd\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 10 f5[ ]*vmovupd ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 11 ee[ ]*vmovupd\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 10 f5[ ]*vmovupd ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 11 ee[ ]*vmovupd\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 10 f5[ ]*vmovupd ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 fd af 11 ee[ ]*vmovupd\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 10 f5[ ]*vmovups xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 11 ee[ ]*vmovups\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 10 f5[ ]*vmovups xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 11 ee[ ]*vmovups\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 10 f5[ ]*vmovups xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 11 ee[ ]*vmovups\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 10 f5[ ]*vmovups xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 11 ee[ ]*vmovups\.s xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 10 f5[ ]*vmovups xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 11 ee[ ]*vmovups\.s xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 10 f5[ ]*vmovups xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 11 ee[ ]*vmovups\.s xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 10 f5[ ]*vmovups ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 11 ee[ ]*vmovups\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 10 f5[ ]*vmovups ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 11 ee[ ]*vmovups\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 10 f5[ ]*vmovups ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 11 ee[ ]*vmovups\.s ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 10 f5[ ]*vmovups ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 11 ee[ ]*vmovups\.s ymm30,ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 10 f5[ ]*vmovups ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 11 ee[ ]*vmovups\.s ymm30\{k7\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 10 f5[ ]*vmovups ymm30\{k7\}\{z\},ymm29
[ ]*[a-f0-9]+:[ ]*62 01 7c af 11 ee[ ]*vmovups\.s ymm30\{k7\}\{z\},ymm29
#pass

396
gas/testsuite/gas/i386/x86-64-avx512f_vl-opts.d Normal file
View file

@ -0,0 +1,396 @@
#as:
#objdump: -dw -Msuffix
#name: x86_64 AVX512F/VL opts insns
#source: x86-64-avx512f_vl-opts.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 28 f5[ ]*vmovapd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 29 ee[ ]*vmovapd\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 28 f5[ ]*vmovapd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 29 ee[ ]*vmovapd\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 28 f5[ ]*vmovapd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 29 ee[ ]*vmovapd\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 28 f5[ ]*vmovapd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 29 ee[ ]*vmovapd\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 28 f5[ ]*vmovapd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 29 ee[ ]*vmovapd\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 28 f5[ ]*vmovapd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 29 ee[ ]*vmovapd\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 28 f5[ ]*vmovapd %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 29 ee[ ]*vmovapd\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 28 f5[ ]*vmovapd %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 29 ee[ ]*vmovapd\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 28 f5[ ]*vmovapd %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 29 ee[ ]*vmovapd\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 28 f5[ ]*vmovapd %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 29 ee[ ]*vmovapd\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 28 f5[ ]*vmovapd %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 29 ee[ ]*vmovapd\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 28 f5[ ]*vmovapd %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 29 ee[ ]*vmovapd\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 28 f5[ ]*vmovaps %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 29 ee[ ]*vmovaps\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 28 f5[ ]*vmovaps %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 29 ee[ ]*vmovaps\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 28 f5[ ]*vmovaps %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 29 ee[ ]*vmovaps\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 28 f5[ ]*vmovaps %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 29 ee[ ]*vmovaps\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 28 f5[ ]*vmovaps %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 29 ee[ ]*vmovaps\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 28 f5[ ]*vmovaps %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 29 ee[ ]*vmovaps\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 28 f5[ ]*vmovaps %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 29 ee[ ]*vmovaps\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 28 f5[ ]*vmovaps %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 29 ee[ ]*vmovaps\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 28 f5[ ]*vmovaps %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 29 ee[ ]*vmovaps\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 28 f5[ ]*vmovaps %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 29 ee[ ]*vmovaps\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 28 f5[ ]*vmovaps %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 29 ee[ ]*vmovaps\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 28 f5[ ]*vmovaps %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 29 ee[ ]*vmovaps\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 6f f5[ ]*vmovdqa32 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 6f f5[ ]*vmovdqa32 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 6f f5[ ]*vmovdqa32 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 6f f5[ ]*vmovdqa32 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 6f f5[ ]*vmovdqa32 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 6f f5[ ]*vmovdqa32 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 6f f5[ ]*vmovdqa32 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 6f f5[ ]*vmovdqa32 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d af 6f f5[ ]*vmovdqa32 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d af 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 6f f5[ ]*vmovdqa32 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 6f f5[ ]*vmovdqa32 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d af 6f f5[ ]*vmovdqa32 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d af 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 6f f5[ ]*vmovdqa64 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 6f f5[ ]*vmovdqa64 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 6f f5[ ]*vmovdqa64 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 6f f5[ ]*vmovdqa64 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 6f f5[ ]*vmovdqa64 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 6f f5[ ]*vmovdqa64 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 6f f5[ ]*vmovdqa64 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 6f f5[ ]*vmovdqa64 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 6f f5[ ]*vmovdqa64 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 6f f5[ ]*vmovdqa64 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 6f f5[ ]*vmovdqa64 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 6f f5[ ]*vmovdqa64 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 6f f5[ ]*vmovdqu32 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 6f f5[ ]*vmovdqu32 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 6f f5[ ]*vmovdqu32 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 6f f5[ ]*vmovdqu32 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 6f f5[ ]*vmovdqu32 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 6f f5[ ]*vmovdqu32 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 6f f5[ ]*vmovdqu32 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 6f f5[ ]*vmovdqu32 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e af 6f f5[ ]*vmovdqu32 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e af 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 6f f5[ ]*vmovdqu32 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 6f f5[ ]*vmovdqu32 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e af 6f f5[ ]*vmovdqu32 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e af 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 6f f5[ ]*vmovdqu64 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 6f f5[ ]*vmovdqu64 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 6f f5[ ]*vmovdqu64 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 6f f5[ ]*vmovdqu64 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 6f f5[ ]*vmovdqu64 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 6f f5[ ]*vmovdqu64 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 6f f5[ ]*vmovdqu64 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 6f f5[ ]*vmovdqu64 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe af 6f f5[ ]*vmovdqu64 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe af 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 6f f5[ ]*vmovdqu64 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 6f f5[ ]*vmovdqu64 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe af 6f f5[ ]*vmovdqu64 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe af 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 10 f5[ ]*vmovupd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 11 ee[ ]*vmovupd\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 10 f5[ ]*vmovupd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 11 ee[ ]*vmovupd\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 10 f5[ ]*vmovupd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 11 ee[ ]*vmovupd\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 10 f5[ ]*vmovupd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 11 ee[ ]*vmovupd\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 10 f5[ ]*vmovupd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 11 ee[ ]*vmovupd\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 10 f5[ ]*vmovupd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 11 ee[ ]*vmovupd\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 10 f5[ ]*vmovupd %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 11 ee[ ]*vmovupd\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 10 f5[ ]*vmovupd %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 11 ee[ ]*vmovupd\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 10 f5[ ]*vmovupd %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 11 ee[ ]*vmovupd\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 10 f5[ ]*vmovupd %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 11 ee[ ]*vmovupd\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 10 f5[ ]*vmovupd %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 11 ee[ ]*vmovupd\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 10 f5[ ]*vmovupd %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 11 ee[ ]*vmovupd\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 10 f5[ ]*vmovups %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 11 ee[ ]*vmovups\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 10 f5[ ]*vmovups %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 11 ee[ ]*vmovups\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 10 f5[ ]*vmovups %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 11 ee[ ]*vmovups\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 10 f5[ ]*vmovups %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 11 ee[ ]*vmovups\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 10 f5[ ]*vmovups %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 11 ee[ ]*vmovups\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 10 f5[ ]*vmovups %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 11 ee[ ]*vmovups\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 10 f5[ ]*vmovups %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 11 ee[ ]*vmovups\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 10 f5[ ]*vmovups %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 11 ee[ ]*vmovups\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 10 f5[ ]*vmovups %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 11 ee[ ]*vmovups\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 10 f5[ ]*vmovups %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 11 ee[ ]*vmovups\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 10 f5[ ]*vmovups %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 11 ee[ ]*vmovups\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 10 f5[ ]*vmovups %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 11 ee[ ]*vmovups\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 28 f5[ ]*vmovapd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 29 ee[ ]*vmovapd\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 28 f5[ ]*vmovapd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 29 ee[ ]*vmovapd\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 28 f5[ ]*vmovapd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 29 ee[ ]*vmovapd\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 28 f5[ ]*vmovapd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 29 ee[ ]*vmovapd\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 28 f5[ ]*vmovapd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 29 ee[ ]*vmovapd\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 28 f5[ ]*vmovapd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 29 ee[ ]*vmovapd\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 28 f5[ ]*vmovapd %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 29 ee[ ]*vmovapd\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 28 f5[ ]*vmovapd %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 29 ee[ ]*vmovapd\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 28 f5[ ]*vmovapd %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 29 ee[ ]*vmovapd\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 28 f5[ ]*vmovapd %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 29 ee[ ]*vmovapd\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 28 f5[ ]*vmovapd %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 29 ee[ ]*vmovapd\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 28 f5[ ]*vmovapd %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 29 ee[ ]*vmovapd\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 28 f5[ ]*vmovaps %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 29 ee[ ]*vmovaps\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 28 f5[ ]*vmovaps %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 29 ee[ ]*vmovaps\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 28 f5[ ]*vmovaps %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 29 ee[ ]*vmovaps\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 28 f5[ ]*vmovaps %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 29 ee[ ]*vmovaps\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 28 f5[ ]*vmovaps %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 29 ee[ ]*vmovaps\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 28 f5[ ]*vmovaps %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 29 ee[ ]*vmovaps\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 28 f5[ ]*vmovaps %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 29 ee[ ]*vmovaps\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 28 f5[ ]*vmovaps %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 29 ee[ ]*vmovaps\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 28 f5[ ]*vmovaps %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 29 ee[ ]*vmovaps\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 28 f5[ ]*vmovaps %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 29 ee[ ]*vmovaps\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 28 f5[ ]*vmovaps %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 29 ee[ ]*vmovaps\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 28 f5[ ]*vmovaps %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 29 ee[ ]*vmovaps\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 6f f5[ ]*vmovdqa32 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 6f f5[ ]*vmovdqa32 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 6f f5[ ]*vmovdqa32 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 6f f5[ ]*vmovdqa32 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 08 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 6f f5[ ]*vmovdqa32 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 0f 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 6f f5[ ]*vmovdqa32 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 8f 7f ee[ ]*vmovdqa32\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 6f f5[ ]*vmovdqa32 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 6f f5[ ]*vmovdqa32 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d af 6f f5[ ]*vmovdqa32 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d af 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 6f f5[ ]*vmovdqa32 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 28 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 6f f5[ ]*vmovdqa32 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d 2f 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7d af 6f f5[ ]*vmovdqa32 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7d af 7f ee[ ]*vmovdqa32\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 6f f5[ ]*vmovdqa64 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 6f f5[ ]*vmovdqa64 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 6f f5[ ]*vmovdqa64 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 6f f5[ ]*vmovdqa64 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 6f f5[ ]*vmovdqa64 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 6f f5[ ]*vmovdqa64 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 7f ee[ ]*vmovdqa64\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 6f f5[ ]*vmovdqa64 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 6f f5[ ]*vmovdqa64 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 6f f5[ ]*vmovdqa64 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 6f f5[ ]*vmovdqa64 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 6f f5[ ]*vmovdqa64 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 6f f5[ ]*vmovdqa64 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 7f ee[ ]*vmovdqa64\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 6f f5[ ]*vmovdqu32 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 6f f5[ ]*vmovdqu32 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 6f f5[ ]*vmovdqu32 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 6f f5[ ]*vmovdqu32 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 08 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 6f f5[ ]*vmovdqu32 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 0f 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 6f f5[ ]*vmovdqu32 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 8f 7f ee[ ]*vmovdqu32\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 6f f5[ ]*vmovdqu32 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 6f f5[ ]*vmovdqu32 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e af 6f f5[ ]*vmovdqu32 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e af 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 6f f5[ ]*vmovdqu32 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 28 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 6f f5[ ]*vmovdqu32 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e 2f 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7e af 6f f5[ ]*vmovdqu32 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7e af 7f ee[ ]*vmovdqu32\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 6f f5[ ]*vmovdqu64 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 6f f5[ ]*vmovdqu64 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 6f f5[ ]*vmovdqu64 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 6f f5[ ]*vmovdqu64 %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 08 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 6f f5[ ]*vmovdqu64 %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 0f 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 6f f5[ ]*vmovdqu64 %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 8f 7f ee[ ]*vmovdqu64\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 6f f5[ ]*vmovdqu64 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 6f f5[ ]*vmovdqu64 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe af 6f f5[ ]*vmovdqu64 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe af 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 6f f5[ ]*vmovdqu64 %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 28 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 6f f5[ ]*vmovdqu64 %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe 2f 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fe af 6f f5[ ]*vmovdqu64 %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fe af 7f ee[ ]*vmovdqu64\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 10 f5[ ]*vmovupd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 11 ee[ ]*vmovupd\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 10 f5[ ]*vmovupd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 11 ee[ ]*vmovupd\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 10 f5[ ]*vmovupd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 11 ee[ ]*vmovupd\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 10 f5[ ]*vmovupd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 08 11 ee[ ]*vmovupd\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 10 f5[ ]*vmovupd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 0f 11 ee[ ]*vmovupd\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 10 f5[ ]*vmovupd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 8f 11 ee[ ]*vmovupd\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 10 f5[ ]*vmovupd %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 11 ee[ ]*vmovupd\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 10 f5[ ]*vmovupd %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 11 ee[ ]*vmovupd\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 10 f5[ ]*vmovupd %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 11 ee[ ]*vmovupd\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 10 f5[ ]*vmovupd %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 28 11 ee[ ]*vmovupd\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 10 f5[ ]*vmovupd %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd 2f 11 ee[ ]*vmovupd\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 10 f5[ ]*vmovupd %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 fd af 11 ee[ ]*vmovupd\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 10 f5[ ]*vmovups %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 11 ee[ ]*vmovups\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 10 f5[ ]*vmovups %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 11 ee[ ]*vmovups\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 10 f5[ ]*vmovups %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 11 ee[ ]*vmovups\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 10 f5[ ]*vmovups %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 08 11 ee[ ]*vmovups\.s %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 10 f5[ ]*vmovups %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 0f 11 ee[ ]*vmovups\.s %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 10 f5[ ]*vmovups %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 8f 11 ee[ ]*vmovups\.s %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 10 f5[ ]*vmovups %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 11 ee[ ]*vmovups\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 10 f5[ ]*vmovups %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 11 ee[ ]*vmovups\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 10 f5[ ]*vmovups %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 11 ee[ ]*vmovups\.s %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 10 f5[ ]*vmovups %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 28 11 ee[ ]*vmovups\.s %ymm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 10 f5[ ]*vmovups %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c 2f 11 ee[ ]*vmovups\.s %ymm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 10 f5[ ]*vmovups %ymm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 01 7c af 11 ee[ ]*vmovups\.s %ymm29,%ymm30\{%k7\}\{z\}
#pass

391
gas/testsuite/gas/i386/x86-64-avx512f_vl-opts.s Normal file
View file

@ -0,0 +1,391 @@
# Check 64bit AVX512{F,VL} swap instructions
.allow_index_reg
.text
_start:
vmovapd %xmm29, %xmm30 # AVX512{F,VL}
vmovapd.s %xmm29, %xmm30 # AVX512{F,VL}
vmovapd %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovapd.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovapd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovapd.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovapd %xmm29, %xmm30 # AVX512{F,VL}
vmovapd.s %xmm29, %xmm30 # AVX512{F,VL}
vmovapd %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovapd.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovapd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovapd.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovapd %ymm29, %ymm30 # AVX512{F,VL}
vmovapd.s %ymm29, %ymm30 # AVX512{F,VL}
vmovapd %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovapd.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovapd %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovapd.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovapd %ymm29, %ymm30 # AVX512{F,VL}
vmovapd.s %ymm29, %ymm30 # AVX512{F,VL}
vmovapd %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovapd.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovapd %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovapd.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovaps %xmm29, %xmm30 # AVX512{F,VL}
vmovaps.s %xmm29, %xmm30 # AVX512{F,VL}
vmovaps %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovaps.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovaps %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovaps.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovaps %xmm29, %xmm30 # AVX512{F,VL}
vmovaps.s %xmm29, %xmm30 # AVX512{F,VL}
vmovaps %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovaps.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovaps %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovaps.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovaps %ymm29, %ymm30 # AVX512{F,VL}
vmovaps.s %ymm29, %ymm30 # AVX512{F,VL}
vmovaps %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovaps.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovaps %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovaps.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovaps %ymm29, %ymm30 # AVX512{F,VL}
vmovaps.s %ymm29, %ymm30 # AVX512{F,VL}
vmovaps %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovaps.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovaps %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovaps.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqa32 %xmm29, %xmm30 # AVX512{F,VL}
vmovdqa32.s %xmm29, %xmm30 # AVX512{F,VL}
vmovdqa32 %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqa32.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqa32 %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqa32.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqa32 %xmm29, %xmm30 # AVX512{F,VL}
vmovdqa32.s %xmm29, %xmm30 # AVX512{F,VL}
vmovdqa32 %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqa32.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqa32 %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqa32.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqa32 %ymm29, %ymm30 # AVX512{F,VL}
vmovdqa32.s %ymm29, %ymm30 # AVX512{F,VL}
vmovdqa32 %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqa32.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqa32 %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqa32.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqa32 %ymm29, %ymm30 # AVX512{F,VL}
vmovdqa32.s %ymm29, %ymm30 # AVX512{F,VL}
vmovdqa32 %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqa32.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqa32 %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqa32.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqa64 %xmm29, %xmm30 # AVX512{F,VL}
vmovdqa64.s %xmm29, %xmm30 # AVX512{F,VL}
vmovdqa64 %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqa64.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqa64 %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqa64.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqa64 %xmm29, %xmm30 # AVX512{F,VL}
vmovdqa64.s %xmm29, %xmm30 # AVX512{F,VL}
vmovdqa64 %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqa64.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqa64 %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqa64.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqa64 %ymm29, %ymm30 # AVX512{F,VL}
vmovdqa64.s %ymm29, %ymm30 # AVX512{F,VL}
vmovdqa64 %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqa64.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqa64 %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqa64.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqa64 %ymm29, %ymm30 # AVX512{F,VL}
vmovdqa64.s %ymm29, %ymm30 # AVX512{F,VL}
vmovdqa64 %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqa64.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqa64 %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqa64.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqu32 %xmm29, %xmm30 # AVX512{F,VL}
vmovdqu32.s %xmm29, %xmm30 # AVX512{F,VL}
vmovdqu32 %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqu32.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqu32 %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqu32.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqu32 %xmm29, %xmm30 # AVX512{F,VL}
vmovdqu32.s %xmm29, %xmm30 # AVX512{F,VL}
vmovdqu32 %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqu32.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqu32 %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqu32.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqu32 %ymm29, %ymm30 # AVX512{F,VL}
vmovdqu32.s %ymm29, %ymm30 # AVX512{F,VL}
vmovdqu32 %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqu32.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqu32 %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqu32.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqu32 %ymm29, %ymm30 # AVX512{F,VL}
vmovdqu32.s %ymm29, %ymm30 # AVX512{F,VL}
vmovdqu32 %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqu32.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqu32 %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqu32.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqu64 %xmm29, %xmm30 # AVX512{F,VL}
vmovdqu64.s %xmm29, %xmm30 # AVX512{F,VL}
vmovdqu64 %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqu64.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqu64 %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqu64.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqu64 %xmm29, %xmm30 # AVX512{F,VL}
vmovdqu64.s %xmm29, %xmm30 # AVX512{F,VL}
vmovdqu64 %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqu64.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovdqu64 %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqu64.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovdqu64 %ymm29, %ymm30 # AVX512{F,VL}
vmovdqu64.s %ymm29, %ymm30 # AVX512{F,VL}
vmovdqu64 %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqu64.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqu64 %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqu64.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqu64 %ymm29, %ymm30 # AVX512{F,VL}
vmovdqu64.s %ymm29, %ymm30 # AVX512{F,VL}
vmovdqu64 %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqu64.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovdqu64 %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovdqu64.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovupd %xmm29, %xmm30 # AVX512{F,VL}
vmovupd.s %xmm29, %xmm30 # AVX512{F,VL}
vmovupd %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovupd.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovupd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovupd.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovupd %xmm29, %xmm30 # AVX512{F,VL}
vmovupd.s %xmm29, %xmm30 # AVX512{F,VL}
vmovupd %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovupd.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovupd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovupd.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovupd %ymm29, %ymm30 # AVX512{F,VL}
vmovupd.s %ymm29, %ymm30 # AVX512{F,VL}
vmovupd %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovupd.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovupd %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovupd.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovupd %ymm29, %ymm30 # AVX512{F,VL}
vmovupd.s %ymm29, %ymm30 # AVX512{F,VL}
vmovupd %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovupd.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovupd %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovupd.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovups %xmm29, %xmm30 # AVX512{F,VL}
vmovups.s %xmm29, %xmm30 # AVX512{F,VL}
vmovups %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovups.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovups %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovups.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovups %xmm29, %xmm30 # AVX512{F,VL}
vmovups.s %xmm29, %xmm30 # AVX512{F,VL}
vmovups %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovups.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
vmovups %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovups.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vmovups %ymm29, %ymm30 # AVX512{F,VL}
vmovups.s %ymm29, %ymm30 # AVX512{F,VL}
vmovups %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovups.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovups %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovups.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovups %ymm29, %ymm30 # AVX512{F,VL}
vmovups.s %ymm29, %ymm30 # AVX512{F,VL}
vmovups %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovups.s %ymm29, %ymm30{%k7} # AVX512{F,VL}
vmovups %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
vmovups.s %ymm29, %ymm30{%k7}{z} # AVX512{F,VL}
.intel_syntax noprefix
vmovapd xmm30, xmm29 # AVX512{F,VL}
vmovapd.s xmm30, xmm29 # AVX512{F,VL}
vmovapd xmm30{k7}, xmm29 # AVX512{F,VL}
vmovapd.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovapd xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovapd.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovapd xmm30, xmm29 # AVX512{F,VL}
vmovapd.s xmm30, xmm29 # AVX512{F,VL}
vmovapd xmm30{k7}, xmm29 # AVX512{F,VL}
vmovapd.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovapd xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovapd.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovapd ymm30, ymm29 # AVX512{F,VL}
vmovapd.s ymm30, ymm29 # AVX512{F,VL}
vmovapd ymm30{k7}, ymm29 # AVX512{F,VL}
vmovapd.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovapd ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovapd.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovapd ymm30, ymm29 # AVX512{F,VL}
vmovapd.s ymm30, ymm29 # AVX512{F,VL}
vmovapd ymm30{k7}, ymm29 # AVX512{F,VL}
vmovapd.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovapd ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovapd.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovaps xmm30, xmm29 # AVX512{F,VL}
vmovaps.s xmm30, xmm29 # AVX512{F,VL}
vmovaps xmm30{k7}, xmm29 # AVX512{F,VL}
vmovaps.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovaps xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovaps.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovaps xmm30, xmm29 # AVX512{F,VL}
vmovaps.s xmm30, xmm29 # AVX512{F,VL}
vmovaps xmm30{k7}, xmm29 # AVX512{F,VL}
vmovaps.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovaps xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovaps.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovaps ymm30, ymm29 # AVX512{F,VL}
vmovaps.s ymm30, ymm29 # AVX512{F,VL}
vmovaps ymm30{k7}, ymm29 # AVX512{F,VL}
vmovaps.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovaps ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovaps.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovaps ymm30, ymm29 # AVX512{F,VL}
vmovaps.s ymm30, ymm29 # AVX512{F,VL}
vmovaps ymm30{k7}, ymm29 # AVX512{F,VL}
vmovaps.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovaps ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovaps.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqa32 xmm30, xmm29 # AVX512{F,VL}
vmovdqa32.s xmm30, xmm29 # AVX512{F,VL}
vmovdqa32 xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqa32.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqa32 xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqa32.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqa32 xmm30, xmm29 # AVX512{F,VL}
vmovdqa32.s xmm30, xmm29 # AVX512{F,VL}
vmovdqa32 xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqa32.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqa32 xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqa32.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqa32 ymm30, ymm29 # AVX512{F,VL}
vmovdqa32.s ymm30, ymm29 # AVX512{F,VL}
vmovdqa32 ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqa32.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqa32 ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqa32.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqa32 ymm30, ymm29 # AVX512{F,VL}
vmovdqa32.s ymm30, ymm29 # AVX512{F,VL}
vmovdqa32 ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqa32.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqa32 ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqa32.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqa64 xmm30, xmm29 # AVX512{F,VL}
vmovdqa64.s xmm30, xmm29 # AVX512{F,VL}
vmovdqa64 xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqa64.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqa64 xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqa64.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqa64 xmm30, xmm29 # AVX512{F,VL}
vmovdqa64.s xmm30, xmm29 # AVX512{F,VL}
vmovdqa64 xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqa64.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqa64 xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqa64.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqa64 ymm30, ymm29 # AVX512{F,VL}
vmovdqa64.s ymm30, ymm29 # AVX512{F,VL}
vmovdqa64 ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqa64.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqa64 ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqa64.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqa64 ymm30, ymm29 # AVX512{F,VL}
vmovdqa64.s ymm30, ymm29 # AVX512{F,VL}
vmovdqa64 ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqa64.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqa64 ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqa64.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqu32 xmm30, xmm29 # AVX512{F,VL}
vmovdqu32.s xmm30, xmm29 # AVX512{F,VL}
vmovdqu32 xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqu32.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqu32 xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqu32.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqu32 xmm30, xmm29 # AVX512{F,VL}
vmovdqu32.s xmm30, xmm29 # AVX512{F,VL}
vmovdqu32 xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqu32.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqu32 xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqu32.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqu32 ymm30, ymm29 # AVX512{F,VL}
vmovdqu32.s ymm30, ymm29 # AVX512{F,VL}
vmovdqu32 ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqu32.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqu32 ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqu32.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqu32 ymm30, ymm29 # AVX512{F,VL}
vmovdqu32.s ymm30, ymm29 # AVX512{F,VL}
vmovdqu32 ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqu32.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqu32 ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqu32.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqu64 xmm30, xmm29 # AVX512{F,VL}
vmovdqu64.s xmm30, xmm29 # AVX512{F,VL}
vmovdqu64 xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqu64.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqu64 xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqu64.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqu64 xmm30, xmm29 # AVX512{F,VL}
vmovdqu64.s xmm30, xmm29 # AVX512{F,VL}
vmovdqu64 xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqu64.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovdqu64 xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqu64.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovdqu64 ymm30, ymm29 # AVX512{F,VL}
vmovdqu64.s ymm30, ymm29 # AVX512{F,VL}
vmovdqu64 ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqu64.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqu64 ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqu64.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqu64 ymm30, ymm29 # AVX512{F,VL}
vmovdqu64.s ymm30, ymm29 # AVX512{F,VL}
vmovdqu64 ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqu64.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovdqu64 ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovdqu64.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovupd xmm30, xmm29 # AVX512{F,VL}
vmovupd.s xmm30, xmm29 # AVX512{F,VL}
vmovupd xmm30{k7}, xmm29 # AVX512{F,VL}
vmovupd.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovupd xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovupd.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovupd xmm30, xmm29 # AVX512{F,VL}
vmovupd.s xmm30, xmm29 # AVX512{F,VL}
vmovupd xmm30{k7}, xmm29 # AVX512{F,VL}
vmovupd.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovupd xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovupd.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovupd ymm30, ymm29 # AVX512{F,VL}
vmovupd.s ymm30, ymm29 # AVX512{F,VL}
vmovupd ymm30{k7}, ymm29 # AVX512{F,VL}
vmovupd.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovupd ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovupd.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovupd ymm30, ymm29 # AVX512{F,VL}
vmovupd.s ymm30, ymm29 # AVX512{F,VL}
vmovupd ymm30{k7}, ymm29 # AVX512{F,VL}
vmovupd.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovupd ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovupd.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovups xmm30, xmm29 # AVX512{F,VL}
vmovups.s xmm30, xmm29 # AVX512{F,VL}
vmovups xmm30{k7}, xmm29 # AVX512{F,VL}
vmovups.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovups xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovups.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovups xmm30, xmm29 # AVX512{F,VL}
vmovups.s xmm30, xmm29 # AVX512{F,VL}
vmovups xmm30{k7}, xmm29 # AVX512{F,VL}
vmovups.s xmm30{k7}, xmm29 # AVX512{F,VL}
vmovups xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovups.s xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vmovups ymm30, ymm29 # AVX512{F,VL}
vmovups.s ymm30, ymm29 # AVX512{F,VL}
vmovups ymm30{k7}, ymm29 # AVX512{F,VL}
vmovups.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovups ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovups.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovups ymm30, ymm29 # AVX512{F,VL}
vmovups.s ymm30, ymm29 # AVX512{F,VL}
vmovups ymm30{k7}, ymm29 # AVX512{F,VL}
vmovups.s ymm30{k7}, ymm29 # AVX512{F,VL}
vmovups ymm30{k7}{z}, ymm29 # AVX512{F,VL}
vmovups.s ymm30{k7}{z}, ymm29 # AVX512{F,VL}

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gas/testsuite/gas/i386/x86-64-avx512f_vl-wig.s Normal file
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@ -0,0 +1,295 @@
# Check 64bit AVX512{F,VL} WIG instructions
.allow_index_reg
.text
_start:
vpmovsxbd %xmm29, %xmm30 # AVX512{F,VL}
vpmovsxbd %xmm29, %xmm30{%k7} # AVX512{F,VL}
vpmovsxbd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vpmovsxbd (%rcx), %xmm30 # AVX512{F,VL}
vpmovsxbd 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
vpmovsxbd 508(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovsxbd 512(%rdx), %xmm30 # AVX512{F,VL}
vpmovsxbd -512(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovsxbd -516(%rdx), %xmm30 # AVX512{F,VL}
vpmovsxbd %xmm29, %ymm30 # AVX512{F,VL}
vpmovsxbd %xmm29, %ymm30{%k7} # AVX512{F,VL}
vpmovsxbd %xmm29, %ymm30{%k7}{z} # AVX512{F,VL}
vpmovsxbd (%rcx), %ymm30 # AVX512{F,VL}
vpmovsxbd 0x123(%rax,%r14,8), %ymm30 # AVX512{F,VL}
vpmovsxbd 1016(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovsxbd 1024(%rdx), %ymm30 # AVX512{F,VL}
vpmovsxbd -1024(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovsxbd -1032(%rdx), %ymm30 # AVX512{F,VL}
vpmovsxbq %xmm29, %xmm30 # AVX512{F,VL}
vpmovsxbq %xmm29, %xmm30{%k7} # AVX512{F,VL}
vpmovsxbq %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vpmovsxbq (%rcx), %xmm30 # AVX512{F,VL}
vpmovsxbq 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
vpmovsxbq 254(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovsxbq 256(%rdx), %xmm30 # AVX512{F,VL}
vpmovsxbq -256(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovsxbq -258(%rdx), %xmm30 # AVX512{F,VL}
vpmovsxbq %xmm29, %ymm30 # AVX512{F,VL}
vpmovsxbq %xmm29, %ymm30{%k7} # AVX512{F,VL}
vpmovsxbq %xmm29, %ymm30{%k7}{z} # AVX512{F,VL}
vpmovsxbq (%rcx), %ymm30 # AVX512{F,VL}
vpmovsxbq 0x123(%rax,%r14,8), %ymm30 # AVX512{F,VL}
vpmovsxbq 508(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovsxbq 512(%rdx), %ymm30 # AVX512{F,VL}
vpmovsxbq -512(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovsxbq -516(%rdx), %ymm30 # AVX512{F,VL}
vpmovsxwd %xmm29, %xmm30 # AVX512{F,VL}
vpmovsxwd %xmm29, %xmm30{%k7} # AVX512{F,VL}
vpmovsxwd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vpmovsxwd (%rcx), %xmm30 # AVX512{F,VL}
vpmovsxwd 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
vpmovsxwd 1016(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovsxwd 1024(%rdx), %xmm30 # AVX512{F,VL}
vpmovsxwd -1024(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovsxwd -1032(%rdx), %xmm30 # AVX512{F,VL}
vpmovsxwd %xmm29, %ymm30 # AVX512{F,VL}
vpmovsxwd %xmm29, %ymm30{%k7} # AVX512{F,VL}
vpmovsxwd %xmm29, %ymm30{%k7}{z} # AVX512{F,VL}
vpmovsxwd (%rcx), %ymm30 # AVX512{F,VL}
vpmovsxwd 0x123(%rax,%r14,8), %ymm30 # AVX512{F,VL}
vpmovsxwd 2032(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovsxwd 2048(%rdx), %ymm30 # AVX512{F,VL}
vpmovsxwd -2048(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovsxwd -2064(%rdx), %ymm30 # AVX512{F,VL}
vpmovsxwq %xmm29, %xmm30 # AVX512{F,VL}
vpmovsxwq %xmm29, %xmm30{%k7} # AVX512{F,VL}
vpmovsxwq %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vpmovsxwq (%rcx), %xmm30 # AVX512{F,VL}
vpmovsxwq 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
vpmovsxwq 508(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovsxwq 512(%rdx), %xmm30 # AVX512{F,VL}
vpmovsxwq -512(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovsxwq -516(%rdx), %xmm30 # AVX512{F,VL}
vpmovsxwq %xmm29, %ymm30 # AVX512{F,VL}
vpmovsxwq %xmm29, %ymm30{%k7} # AVX512{F,VL}
vpmovsxwq %xmm29, %ymm30{%k7}{z} # AVX512{F,VL}
vpmovsxwq (%rcx), %ymm30 # AVX512{F,VL}
vpmovsxwq 0x123(%rax,%r14,8), %ymm30 # AVX512{F,VL}
vpmovsxwq 1016(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovsxwq 1024(%rdx), %ymm30 # AVX512{F,VL}
vpmovsxwq -1024(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovsxwq -1032(%rdx), %ymm30 # AVX512{F,VL}
vpmovzxbd %xmm29, %xmm30 # AVX512{F,VL}
vpmovzxbd %xmm29, %xmm30{%k7} # AVX512{F,VL}
vpmovzxbd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vpmovzxbd (%rcx), %xmm30 # AVX512{F,VL}
vpmovzxbd 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
vpmovzxbd 508(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovzxbd 512(%rdx), %xmm30 # AVX512{F,VL}
vpmovzxbd -512(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovzxbd -516(%rdx), %xmm30 # AVX512{F,VL}
vpmovzxbd %xmm29, %ymm30 # AVX512{F,VL}
vpmovzxbd %xmm29, %ymm30{%k7} # AVX512{F,VL}
vpmovzxbd %xmm29, %ymm30{%k7}{z} # AVX512{F,VL}
vpmovzxbd (%rcx), %ymm30 # AVX512{F,VL}
vpmovzxbd 0x123(%rax,%r14,8), %ymm30 # AVX512{F,VL}
vpmovzxbd 1016(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovzxbd 1024(%rdx), %ymm30 # AVX512{F,VL}
vpmovzxbd -1024(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovzxbd -1032(%rdx), %ymm30 # AVX512{F,VL}
vpmovzxbq %xmm29, %xmm30 # AVX512{F,VL}
vpmovzxbq %xmm29, %xmm30{%k7} # AVX512{F,VL}
vpmovzxbq %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vpmovzxbq (%rcx), %xmm30 # AVX512{F,VL}
vpmovzxbq 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
vpmovzxbq 254(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovzxbq 256(%rdx), %xmm30 # AVX512{F,VL}
vpmovzxbq -256(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovzxbq -258(%rdx), %xmm30 # AVX512{F,VL}
vpmovzxbq %xmm29, %ymm30 # AVX512{F,VL}
vpmovzxbq %xmm29, %ymm30{%k7} # AVX512{F,VL}
vpmovzxbq %xmm29, %ymm30{%k7}{z} # AVX512{F,VL}
vpmovzxbq (%rcx), %ymm30 # AVX512{F,VL}
vpmovzxbq 0x123(%rax,%r14,8), %ymm30 # AVX512{F,VL}
vpmovzxbq 508(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovzxbq 512(%rdx), %ymm30 # AVX512{F,VL}
vpmovzxbq -512(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovzxbq -516(%rdx), %ymm30 # AVX512{F,VL}
vpmovzxwd %xmm29, %xmm30 # AVX512{F,VL}
vpmovzxwd %xmm29, %xmm30{%k7} # AVX512{F,VL}
vpmovzxwd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vpmovzxwd (%rcx), %xmm30 # AVX512{F,VL}
vpmovzxwd 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
vpmovzxwd 1016(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovzxwd 1024(%rdx), %xmm30 # AVX512{F,VL}
vpmovzxwd -1024(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovzxwd -1032(%rdx), %xmm30 # AVX512{F,VL}
vpmovzxwd %xmm29, %ymm30 # AVX512{F,VL}
vpmovzxwd %xmm29, %ymm30{%k7} # AVX512{F,VL}
vpmovzxwd %xmm29, %ymm30{%k7}{z} # AVX512{F,VL}
vpmovzxwd (%rcx), %ymm30 # AVX512{F,VL}
vpmovzxwd 0x123(%rax,%r14,8), %ymm30 # AVX512{F,VL}
vpmovzxwd 2032(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovzxwd 2048(%rdx), %ymm30 # AVX512{F,VL}
vpmovzxwd -2048(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovzxwd -2064(%rdx), %ymm30 # AVX512{F,VL}
vpmovzxwq %xmm29, %xmm30 # AVX512{F,VL}
vpmovzxwq %xmm29, %xmm30{%k7} # AVX512{F,VL}
vpmovzxwq %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vpmovzxwq (%rcx), %xmm30 # AVX512{F,VL}
vpmovzxwq 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
vpmovzxwq 508(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovzxwq 512(%rdx), %xmm30 # AVX512{F,VL}
vpmovzxwq -512(%rdx), %xmm30 # AVX512{F,VL} Disp8
vpmovzxwq -516(%rdx), %xmm30 # AVX512{F,VL}
vpmovzxwq %xmm29, %ymm30 # AVX512{F,VL}
vpmovzxwq %xmm29, %ymm30{%k7} # AVX512{F,VL}
vpmovzxwq %xmm29, %ymm30{%k7}{z} # AVX512{F,VL}
vpmovzxwq (%rcx), %ymm30 # AVX512{F,VL}
vpmovzxwq 0x123(%rax,%r14,8), %ymm30 # AVX512{F,VL}
vpmovzxwq 1016(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovzxwq 1024(%rdx), %ymm30 # AVX512{F,VL}
vpmovzxwq -1024(%rdx), %ymm30 # AVX512{F,VL} Disp8
vpmovzxwq -1032(%rdx), %ymm30 # AVX512{F,VL}
.intel_syntax noprefix
vpmovsxbd xmm30, xmm29 # AVX512{F,VL}
vpmovsxbd xmm30{k7}, xmm29 # AVX512{F,VL}
vpmovsxbd xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovsxbd xmm30, DWORD PTR [rcx] # AVX512{F,VL}
vpmovsxbd xmm30, DWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovsxbd xmm30, DWORD PTR [rdx+508] # AVX512{F,VL} Disp8
vpmovsxbd xmm30, DWORD PTR [rdx+512] # AVX512{F,VL}
vpmovsxbd xmm30, DWORD PTR [rdx-512] # AVX512{F,VL} Disp8
vpmovsxbd xmm30, DWORD PTR [rdx-516] # AVX512{F,VL}
vpmovsxbd ymm30, xmm29 # AVX512{F,VL}
vpmovsxbd ymm30{k7}, xmm29 # AVX512{F,VL}
vpmovsxbd ymm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovsxbd ymm30, QWORD PTR [rcx] # AVX512{F,VL}
vpmovsxbd ymm30, QWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovsxbd ymm30, QWORD PTR [rdx+1016] # AVX512{F,VL} Disp8
vpmovsxbd ymm30, QWORD PTR [rdx+1024] # AVX512{F,VL}
vpmovsxbd ymm30, QWORD PTR [rdx-1024] # AVX512{F,VL} Disp8
vpmovsxbd ymm30, QWORD PTR [rdx-1032] # AVX512{F,VL}
vpmovsxbq xmm30, xmm29 # AVX512{F,VL}
vpmovsxbq xmm30{k7}, xmm29 # AVX512{F,VL}
vpmovsxbq xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovsxbq xmm30, WORD PTR [rcx] # AVX512{F,VL}
vpmovsxbq xmm30, WORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovsxbq xmm30, WORD PTR [rdx+254] # AVX512{F,VL} Disp8
vpmovsxbq xmm30, WORD PTR [rdx+256] # AVX512{F,VL}
vpmovsxbq xmm30, WORD PTR [rdx-256] # AVX512{F,VL} Disp8
vpmovsxbq xmm30, WORD PTR [rdx-258] # AVX512{F,VL}
vpmovsxbq ymm30, xmm29 # AVX512{F,VL}
vpmovsxbq ymm30{k7}, xmm29 # AVX512{F,VL}
vpmovsxbq ymm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovsxbq ymm30, DWORD PTR [rcx] # AVX512{F,VL}
vpmovsxbq ymm30, DWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovsxbq ymm30, DWORD PTR [rdx+508] # AVX512{F,VL} Disp8
vpmovsxbq ymm30, DWORD PTR [rdx+512] # AVX512{F,VL}
vpmovsxbq ymm30, DWORD PTR [rdx-512] # AVX512{F,VL} Disp8
vpmovsxbq ymm30, DWORD PTR [rdx-516] # AVX512{F,VL}
vpmovsxwd xmm30, xmm29 # AVX512{F,VL}
vpmovsxwd xmm30{k7}, xmm29 # AVX512{F,VL}
vpmovsxwd xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovsxwd xmm30, QWORD PTR [rcx] # AVX512{F,VL}
vpmovsxwd xmm30, QWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovsxwd xmm30, QWORD PTR [rdx+1016] # AVX512{F,VL} Disp8
vpmovsxwd xmm30, QWORD PTR [rdx+1024] # AVX512{F,VL}
vpmovsxwd xmm30, QWORD PTR [rdx-1024] # AVX512{F,VL} Disp8
vpmovsxwd xmm30, QWORD PTR [rdx-1032] # AVX512{F,VL}
vpmovsxwd ymm30, xmm29 # AVX512{F,VL}
vpmovsxwd ymm30{k7}, xmm29 # AVX512{F,VL}
vpmovsxwd ymm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovsxwd ymm30, XMMWORD PTR [rcx] # AVX512{F,VL}
vpmovsxwd ymm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovsxwd ymm30, XMMWORD PTR [rdx+2032] # AVX512{F,VL} Disp8
vpmovsxwd ymm30, XMMWORD PTR [rdx+2048] # AVX512{F,VL}
vpmovsxwd ymm30, XMMWORD PTR [rdx-2048] # AVX512{F,VL} Disp8
vpmovsxwd ymm30, XMMWORD PTR [rdx-2064] # AVX512{F,VL}
vpmovsxwq xmm30, xmm29 # AVX512{F,VL}
vpmovsxwq xmm30{k7}, xmm29 # AVX512{F,VL}
vpmovsxwq xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovsxwq xmm30, DWORD PTR [rcx] # AVX512{F,VL}
vpmovsxwq xmm30, DWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovsxwq xmm30, DWORD PTR [rdx+508] # AVX512{F,VL} Disp8
vpmovsxwq xmm30, DWORD PTR [rdx+512] # AVX512{F,VL}
vpmovsxwq xmm30, DWORD PTR [rdx-512] # AVX512{F,VL} Disp8
vpmovsxwq xmm30, DWORD PTR [rdx-516] # AVX512{F,VL}
vpmovsxwq ymm30, xmm29 # AVX512{F,VL}
vpmovsxwq ymm30{k7}, xmm29 # AVX512{F,VL}
vpmovsxwq ymm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovsxwq ymm30, QWORD PTR [rcx] # AVX512{F,VL}
vpmovsxwq ymm30, QWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovsxwq ymm30, QWORD PTR [rdx+1016] # AVX512{F,VL} Disp8
vpmovsxwq ymm30, QWORD PTR [rdx+1024] # AVX512{F,VL}
vpmovsxwq ymm30, QWORD PTR [rdx-1024] # AVX512{F,VL} Disp8
vpmovsxwq ymm30, QWORD PTR [rdx-1032] # AVX512{F,VL}
vpmovzxbd xmm30, xmm29 # AVX512{F,VL}
vpmovzxbd xmm30{k7}, xmm29 # AVX512{F,VL}
vpmovzxbd xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovzxbd xmm30, DWORD PTR [rcx] # AVX512{F,VL}
vpmovzxbd xmm30, DWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovzxbd xmm30, DWORD PTR [rdx+508] # AVX512{F,VL} Disp8
vpmovzxbd xmm30, DWORD PTR [rdx+512] # AVX512{F,VL}
vpmovzxbd xmm30, DWORD PTR [rdx-512] # AVX512{F,VL} Disp8
vpmovzxbd xmm30, DWORD PTR [rdx-516] # AVX512{F,VL}
vpmovzxbd ymm30, xmm29 # AVX512{F,VL}
vpmovzxbd ymm30{k7}, xmm29 # AVX512{F,VL}
vpmovzxbd ymm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovzxbd ymm30, QWORD PTR [rcx] # AVX512{F,VL}
vpmovzxbd ymm30, QWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovzxbd ymm30, QWORD PTR [rdx+1016] # AVX512{F,VL} Disp8
vpmovzxbd ymm30, QWORD PTR [rdx+1024] # AVX512{F,VL}
vpmovzxbd ymm30, QWORD PTR [rdx-1024] # AVX512{F,VL} Disp8
vpmovzxbd ymm30, QWORD PTR [rdx-1032] # AVX512{F,VL}
vpmovzxbq xmm30, xmm29 # AVX512{F,VL}
vpmovzxbq xmm30{k7}, xmm29 # AVX512{F,VL}
vpmovzxbq xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovzxbq xmm30, WORD PTR [rcx] # AVX512{F,VL}
vpmovzxbq xmm30, WORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovzxbq xmm30, WORD PTR [rdx+254] # AVX512{F,VL} Disp8
vpmovzxbq xmm30, WORD PTR [rdx+256] # AVX512{F,VL}
vpmovzxbq xmm30, WORD PTR [rdx-256] # AVX512{F,VL} Disp8
vpmovzxbq xmm30, WORD PTR [rdx-258] # AVX512{F,VL}
vpmovzxbq ymm30, xmm29 # AVX512{F,VL}
vpmovzxbq ymm30{k7}, xmm29 # AVX512{F,VL}
vpmovzxbq ymm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovzxbq ymm30, DWORD PTR [rcx] # AVX512{F,VL}
vpmovzxbq ymm30, DWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovzxbq ymm30, DWORD PTR [rdx+508] # AVX512{F,VL} Disp8
vpmovzxbq ymm30, DWORD PTR [rdx+512] # AVX512{F,VL}
vpmovzxbq ymm30, DWORD PTR [rdx-512] # AVX512{F,VL} Disp8
vpmovzxbq ymm30, DWORD PTR [rdx-516] # AVX512{F,VL}
vpmovzxwd xmm30, xmm29 # AVX512{F,VL}
vpmovzxwd xmm30{k7}, xmm29 # AVX512{F,VL}
vpmovzxwd xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovzxwd xmm30, QWORD PTR [rcx] # AVX512{F,VL}
vpmovzxwd xmm30, QWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovzxwd xmm30, QWORD PTR [rdx+1016] # AVX512{F,VL} Disp8
vpmovzxwd xmm30, QWORD PTR [rdx+1024] # AVX512{F,VL}
vpmovzxwd xmm30, QWORD PTR [rdx-1024] # AVX512{F,VL} Disp8
vpmovzxwd xmm30, QWORD PTR [rdx-1032] # AVX512{F,VL}
vpmovzxwd ymm30, xmm29 # AVX512{F,VL}
vpmovzxwd ymm30{k7}, xmm29 # AVX512{F,VL}
vpmovzxwd ymm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovzxwd ymm30, XMMWORD PTR [rcx] # AVX512{F,VL}
vpmovzxwd ymm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovzxwd ymm30, XMMWORD PTR [rdx+2032] # AVX512{F,VL} Disp8
vpmovzxwd ymm30, XMMWORD PTR [rdx+2048] # AVX512{F,VL}
vpmovzxwd ymm30, XMMWORD PTR [rdx-2048] # AVX512{F,VL} Disp8
vpmovzxwd ymm30, XMMWORD PTR [rdx-2064] # AVX512{F,VL}
vpmovzxwq xmm30, xmm29 # AVX512{F,VL}
vpmovzxwq xmm30{k7}, xmm29 # AVX512{F,VL}
vpmovzxwq xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovzxwq xmm30, DWORD PTR [rcx] # AVX512{F,VL}
vpmovzxwq xmm30, DWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovzxwq xmm30, DWORD PTR [rdx+508] # AVX512{F,VL} Disp8
vpmovzxwq xmm30, DWORD PTR [rdx+512] # AVX512{F,VL}
vpmovzxwq xmm30, DWORD PTR [rdx-512] # AVX512{F,VL} Disp8
vpmovzxwq xmm30, DWORD PTR [rdx-516] # AVX512{F,VL}
vpmovzxwq ymm30, xmm29 # AVX512{F,VL}
vpmovzxwq ymm30{k7}, xmm29 # AVX512{F,VL}
vpmovzxwq ymm30{k7}{z}, xmm29 # AVX512{F,VL}
vpmovzxwq ymm30, QWORD PTR [rcx] # AVX512{F,VL}
vpmovzxwq ymm30, QWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
vpmovzxwq ymm30, QWORD PTR [rdx+1016] # AVX512{F,VL} Disp8
vpmovzxwq ymm30, QWORD PTR [rdx+1024] # AVX512{F,VL}
vpmovzxwq ymm30, QWORD PTR [rdx-1024] # AVX512{F,VL} Disp8
vpmovzxwq ymm30, QWORD PTR [rdx-1032] # AVX512{F,VL}

300
gas/testsuite/gas/i386/x86-64-avx512f_vl-wig1-intel.d Normal file
View file

@ -0,0 +1,300 @@
#as: -mevexwig=1
#objdump: -dw -Mintel
#name: x86_64 AVX512F/VL wig insns (Intel disassembly)
#source: x86-64-avx512f_vl-wig.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 21 f5[ ]*vpmovsxbd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 21 f5[ ]*vpmovsxbd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 21 f5[ ]*vpmovsxbd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 31[ ]*vpmovsxbd xmm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 21 b4 f0 23 01 00 00[ ]*vpmovsxbd xmm30,DWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 7f[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 00 02 00 00[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 80[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 fc fd ff ff[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 21 f5[ ]*vpmovsxbd ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 21 f5[ ]*vpmovsxbd ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 21 f5[ ]*vpmovsxbd ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 31[ ]*vpmovsxbd ymm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 21 b4 f0 23 01 00 00[ ]*vpmovsxbd ymm30,QWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 72 7f[ ]*vpmovsxbd ymm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 b2 00 04 00 00[ ]*vpmovsxbd ymm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 72 80[ ]*vpmovsxbd ymm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 b2 f8 fb ff ff[ ]*vpmovsxbd ymm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 22 f5[ ]*vpmovsxbq xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 22 f5[ ]*vpmovsxbq xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 22 f5[ ]*vpmovsxbq xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 31[ ]*vpmovsxbq xmm30,WORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 22 b4 f0 23 01 00 00[ ]*vpmovsxbq xmm30,WORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 72 7f[ ]*vpmovsxbq xmm30,WORD PTR \[rdx\+0xfe\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 b2 00 01 00 00[ ]*vpmovsxbq xmm30,WORD PTR \[rdx\+0x100\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 72 80[ ]*vpmovsxbq xmm30,WORD PTR \[rdx-0x100\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 b2 fe fe ff ff[ ]*vpmovsxbq xmm30,WORD PTR \[rdx-0x102\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 22 f5[ ]*vpmovsxbq ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 22 f5[ ]*vpmovsxbq ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 22 f5[ ]*vpmovsxbq ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 31[ ]*vpmovsxbq ymm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 22 b4 f0 23 01 00 00[ ]*vpmovsxbq ymm30,DWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 72 7f[ ]*vpmovsxbq ymm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 b2 00 02 00 00[ ]*vpmovsxbq ymm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 72 80[ ]*vpmovsxbq ymm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 b2 fc fd ff ff[ ]*vpmovsxbq ymm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 23 f5[ ]*vpmovsxwd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 23 f5[ ]*vpmovsxwd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 23 f5[ ]*vpmovsxwd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 31[ ]*vpmovsxwd xmm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 23 b4 f0 23 01 00 00[ ]*vpmovsxwd xmm30,QWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 72 7f[ ]*vpmovsxwd xmm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 b2 00 04 00 00[ ]*vpmovsxwd xmm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 72 80[ ]*vpmovsxwd xmm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 b2 f8 fb ff ff[ ]*vpmovsxwd xmm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 23 f5[ ]*vpmovsxwd ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 23 f5[ ]*vpmovsxwd ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 23 f5[ ]*vpmovsxwd ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 31[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 23 b4 f0 23 01 00 00[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 72 7f[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rdx\+0x7f0\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 b2 00 08 00 00[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rdx\+0x800\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 72 80[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rdx-0x800\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 b2 f0 f7 ff ff[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rdx-0x810\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 24 f5[ ]*vpmovsxwq xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 24 f5[ ]*vpmovsxwq xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 24 f5[ ]*vpmovsxwq xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 31[ ]*vpmovsxwq xmm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 24 b4 f0 23 01 00 00[ ]*vpmovsxwq xmm30,DWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 72 7f[ ]*vpmovsxwq xmm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 b2 00 02 00 00[ ]*vpmovsxwq xmm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 72 80[ ]*vpmovsxwq xmm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 b2 fc fd ff ff[ ]*vpmovsxwq xmm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 24 f5[ ]*vpmovsxwq ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 24 f5[ ]*vpmovsxwq ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 24 f5[ ]*vpmovsxwq ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 31[ ]*vpmovsxwq ymm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 24 b4 f0 23 01 00 00[ ]*vpmovsxwq ymm30,QWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 72 7f[ ]*vpmovsxwq ymm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 b2 00 04 00 00[ ]*vpmovsxwq ymm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 72 80[ ]*vpmovsxwq ymm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 b2 f8 fb ff ff[ ]*vpmovsxwq ymm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 31 f5[ ]*vpmovzxbd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 31 f5[ ]*vpmovzxbd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 31 f5[ ]*vpmovzxbd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 31[ ]*vpmovzxbd xmm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 31 b4 f0 23 01 00 00[ ]*vpmovzxbd xmm30,DWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 72 7f[ ]*vpmovzxbd xmm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 b2 00 02 00 00[ ]*vpmovzxbd xmm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 72 80[ ]*vpmovzxbd xmm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 b2 fc fd ff ff[ ]*vpmovzxbd xmm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 31 f5[ ]*vpmovzxbd ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 31 f5[ ]*vpmovzxbd ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 31 f5[ ]*vpmovzxbd ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 31[ ]*vpmovzxbd ymm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 31 b4 f0 23 01 00 00[ ]*vpmovzxbd ymm30,QWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 72 7f[ ]*vpmovzxbd ymm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 b2 00 04 00 00[ ]*vpmovzxbd ymm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 72 80[ ]*vpmovzxbd ymm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 b2 f8 fb ff ff[ ]*vpmovzxbd ymm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 32 f5[ ]*vpmovzxbq xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 32 f5[ ]*vpmovzxbq xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 32 f5[ ]*vpmovzxbq xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 31[ ]*vpmovzxbq xmm30,WORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 32 b4 f0 23 01 00 00[ ]*vpmovzxbq xmm30,WORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 72 7f[ ]*vpmovzxbq xmm30,WORD PTR \[rdx\+0xfe\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 b2 00 01 00 00[ ]*vpmovzxbq xmm30,WORD PTR \[rdx\+0x100\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 72 80[ ]*vpmovzxbq xmm30,WORD PTR \[rdx-0x100\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 b2 fe fe ff ff[ ]*vpmovzxbq xmm30,WORD PTR \[rdx-0x102\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 32 f5[ ]*vpmovzxbq ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 32 f5[ ]*vpmovzxbq ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 32 f5[ ]*vpmovzxbq ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 31[ ]*vpmovzxbq ymm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 32 b4 f0 23 01 00 00[ ]*vpmovzxbq ymm30,DWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 72 7f[ ]*vpmovzxbq ymm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 b2 00 02 00 00[ ]*vpmovzxbq ymm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 72 80[ ]*vpmovzxbq ymm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 b2 fc fd ff ff[ ]*vpmovzxbq ymm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 33 f5[ ]*vpmovzxwd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 33 f5[ ]*vpmovzxwd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 33 f5[ ]*vpmovzxwd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 31[ ]*vpmovzxwd xmm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 33 b4 f0 23 01 00 00[ ]*vpmovzxwd xmm30,QWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 72 7f[ ]*vpmovzxwd xmm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 b2 00 04 00 00[ ]*vpmovzxwd xmm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 72 80[ ]*vpmovzxwd xmm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 b2 f8 fb ff ff[ ]*vpmovzxwd xmm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 33 f5[ ]*vpmovzxwd ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 33 f5[ ]*vpmovzxwd ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 33 f5[ ]*vpmovzxwd ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 31[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 33 b4 f0 23 01 00 00[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 72 7f[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rdx\+0x7f0\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 b2 00 08 00 00[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rdx\+0x800\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 72 80[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rdx-0x800\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 b2 f0 f7 ff ff[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rdx-0x810\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 34 f5[ ]*vpmovzxwq xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 34 f5[ ]*vpmovzxwq xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 34 f5[ ]*vpmovzxwq xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 31[ ]*vpmovzxwq xmm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 34 b4 f0 23 01 00 00[ ]*vpmovzxwq xmm30,DWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 72 7f[ ]*vpmovzxwq xmm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 b2 00 02 00 00[ ]*vpmovzxwq xmm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 72 80[ ]*vpmovzxwq xmm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 b2 fc fd ff ff[ ]*vpmovzxwq xmm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 34 f5[ ]*vpmovzxwq ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 34 f5[ ]*vpmovzxwq ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 34 f5[ ]*vpmovzxwq ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 31[ ]*vpmovzxwq ymm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 34 b4 f0 23 01 00 00[ ]*vpmovzxwq ymm30,QWORD PTR \[rax\+r14\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 72 7f[ ]*vpmovzxwq ymm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 b2 00 04 00 00[ ]*vpmovzxwq ymm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 72 80[ ]*vpmovzxwq ymm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 b2 f8 fb ff ff[ ]*vpmovzxwq ymm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 21 f5[ ]*vpmovsxbd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 21 f5[ ]*vpmovsxbd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 21 f5[ ]*vpmovsxbd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 31[ ]*vpmovsxbd xmm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 21 b4 f0 34 12 00 00[ ]*vpmovsxbd xmm30,DWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 7f[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 00 02 00 00[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 80[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 fc fd ff ff[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 21 f5[ ]*vpmovsxbd ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 21 f5[ ]*vpmovsxbd ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 21 f5[ ]*vpmovsxbd ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 31[ ]*vpmovsxbd ymm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 21 b4 f0 34 12 00 00[ ]*vpmovsxbd ymm30,QWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 72 7f[ ]*vpmovsxbd ymm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 b2 00 04 00 00[ ]*vpmovsxbd ymm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 72 80[ ]*vpmovsxbd ymm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 b2 f8 fb ff ff[ ]*vpmovsxbd ymm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 22 f5[ ]*vpmovsxbq xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 22 f5[ ]*vpmovsxbq xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 22 f5[ ]*vpmovsxbq xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 31[ ]*vpmovsxbq xmm30,WORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 22 b4 f0 34 12 00 00[ ]*vpmovsxbq xmm30,WORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 72 7f[ ]*vpmovsxbq xmm30,WORD PTR \[rdx\+0xfe\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 b2 00 01 00 00[ ]*vpmovsxbq xmm30,WORD PTR \[rdx\+0x100\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 72 80[ ]*vpmovsxbq xmm30,WORD PTR \[rdx-0x100\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 b2 fe fe ff ff[ ]*vpmovsxbq xmm30,WORD PTR \[rdx-0x102\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 22 f5[ ]*vpmovsxbq ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 22 f5[ ]*vpmovsxbq ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 22 f5[ ]*vpmovsxbq ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 31[ ]*vpmovsxbq ymm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 22 b4 f0 34 12 00 00[ ]*vpmovsxbq ymm30,DWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 72 7f[ ]*vpmovsxbq ymm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 b2 00 02 00 00[ ]*vpmovsxbq ymm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 72 80[ ]*vpmovsxbq ymm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 b2 fc fd ff ff[ ]*vpmovsxbq ymm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 23 f5[ ]*vpmovsxwd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 23 f5[ ]*vpmovsxwd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 23 f5[ ]*vpmovsxwd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 31[ ]*vpmovsxwd xmm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 23 b4 f0 34 12 00 00[ ]*vpmovsxwd xmm30,QWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 72 7f[ ]*vpmovsxwd xmm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 b2 00 04 00 00[ ]*vpmovsxwd xmm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 72 80[ ]*vpmovsxwd xmm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 b2 f8 fb ff ff[ ]*vpmovsxwd xmm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 23 f5[ ]*vpmovsxwd ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 23 f5[ ]*vpmovsxwd ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 23 f5[ ]*vpmovsxwd ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 31[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 23 b4 f0 34 12 00 00[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 72 7f[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rdx\+0x7f0\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 b2 00 08 00 00[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rdx\+0x800\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 72 80[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rdx-0x800\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 b2 f0 f7 ff ff[ ]*vpmovsxwd ymm30,XMMWORD PTR \[rdx-0x810\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 24 f5[ ]*vpmovsxwq xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 24 f5[ ]*vpmovsxwq xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 24 f5[ ]*vpmovsxwq xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 31[ ]*vpmovsxwq xmm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 24 b4 f0 34 12 00 00[ ]*vpmovsxwq xmm30,DWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 72 7f[ ]*vpmovsxwq xmm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 b2 00 02 00 00[ ]*vpmovsxwq xmm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 72 80[ ]*vpmovsxwq xmm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 b2 fc fd ff ff[ ]*vpmovsxwq xmm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 24 f5[ ]*vpmovsxwq ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 24 f5[ ]*vpmovsxwq ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 24 f5[ ]*vpmovsxwq ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 31[ ]*vpmovsxwq ymm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 24 b4 f0 34 12 00 00[ ]*vpmovsxwq ymm30,QWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 72 7f[ ]*vpmovsxwq ymm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 b2 00 04 00 00[ ]*vpmovsxwq ymm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 72 80[ ]*vpmovsxwq ymm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 b2 f8 fb ff ff[ ]*vpmovsxwq ymm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 31 f5[ ]*vpmovzxbd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 31 f5[ ]*vpmovzxbd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 31 f5[ ]*vpmovzxbd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 31[ ]*vpmovzxbd xmm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 31 b4 f0 34 12 00 00[ ]*vpmovzxbd xmm30,DWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 72 7f[ ]*vpmovzxbd xmm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 b2 00 02 00 00[ ]*vpmovzxbd xmm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 72 80[ ]*vpmovzxbd xmm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 b2 fc fd ff ff[ ]*vpmovzxbd xmm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 31 f5[ ]*vpmovzxbd ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 31 f5[ ]*vpmovzxbd ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 31 f5[ ]*vpmovzxbd ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 31[ ]*vpmovzxbd ymm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 31 b4 f0 34 12 00 00[ ]*vpmovzxbd ymm30,QWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 72 7f[ ]*vpmovzxbd ymm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 b2 00 04 00 00[ ]*vpmovzxbd ymm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 72 80[ ]*vpmovzxbd ymm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 b2 f8 fb ff ff[ ]*vpmovzxbd ymm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 32 f5[ ]*vpmovzxbq xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 32 f5[ ]*vpmovzxbq xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 32 f5[ ]*vpmovzxbq xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 31[ ]*vpmovzxbq xmm30,WORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 32 b4 f0 34 12 00 00[ ]*vpmovzxbq xmm30,WORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 72 7f[ ]*vpmovzxbq xmm30,WORD PTR \[rdx\+0xfe\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 b2 00 01 00 00[ ]*vpmovzxbq xmm30,WORD PTR \[rdx\+0x100\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 72 80[ ]*vpmovzxbq xmm30,WORD PTR \[rdx-0x100\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 b2 fe fe ff ff[ ]*vpmovzxbq xmm30,WORD PTR \[rdx-0x102\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 32 f5[ ]*vpmovzxbq ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 32 f5[ ]*vpmovzxbq ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 32 f5[ ]*vpmovzxbq ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 31[ ]*vpmovzxbq ymm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 32 b4 f0 34 12 00 00[ ]*vpmovzxbq ymm30,DWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 72 7f[ ]*vpmovzxbq ymm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 b2 00 02 00 00[ ]*vpmovzxbq ymm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 72 80[ ]*vpmovzxbq ymm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 b2 fc fd ff ff[ ]*vpmovzxbq ymm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 33 f5[ ]*vpmovzxwd xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 33 f5[ ]*vpmovzxwd xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 33 f5[ ]*vpmovzxwd xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 31[ ]*vpmovzxwd xmm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 33 b4 f0 34 12 00 00[ ]*vpmovzxwd xmm30,QWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 72 7f[ ]*vpmovzxwd xmm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 b2 00 04 00 00[ ]*vpmovzxwd xmm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 72 80[ ]*vpmovzxwd xmm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 b2 f8 fb ff ff[ ]*vpmovzxwd xmm30,QWORD PTR \[rdx-0x408\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 33 f5[ ]*vpmovzxwd ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 33 f5[ ]*vpmovzxwd ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 33 f5[ ]*vpmovzxwd ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 31[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 33 b4 f0 34 12 00 00[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 72 7f[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rdx\+0x7f0\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 b2 00 08 00 00[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rdx\+0x800\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 72 80[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rdx-0x800\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 b2 f0 f7 ff ff[ ]*vpmovzxwd ymm30,XMMWORD PTR \[rdx-0x810\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 34 f5[ ]*vpmovzxwq xmm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 34 f5[ ]*vpmovzxwq xmm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 34 f5[ ]*vpmovzxwq xmm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 31[ ]*vpmovzxwq xmm30,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 34 b4 f0 34 12 00 00[ ]*vpmovzxwq xmm30,DWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 72 7f[ ]*vpmovzxwq xmm30,DWORD PTR \[rdx\+0x1fc\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 b2 00 02 00 00[ ]*vpmovzxwq xmm30,DWORD PTR \[rdx\+0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 72 80[ ]*vpmovzxwq xmm30,DWORD PTR \[rdx-0x200\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 b2 fc fd ff ff[ ]*vpmovzxwq xmm30,DWORD PTR \[rdx-0x204\]
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 34 f5[ ]*vpmovzxwq ymm30,xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 34 f5[ ]*vpmovzxwq ymm30\{k7\},xmm29
[ ]*[a-f0-9]+:[ ]*62 02 fd af 34 f5[ ]*vpmovzxwq ymm30\{k7\}\{z\},xmm29
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 31[ ]*vpmovzxwq ymm30,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 34 b4 f0 34 12 00 00[ ]*vpmovzxwq ymm30,QWORD PTR \[rax\+r14\*8\+0x1234\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 72 7f[ ]*vpmovzxwq ymm30,QWORD PTR \[rdx\+0x3f8\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 b2 00 04 00 00[ ]*vpmovzxwq ymm30,QWORD PTR \[rdx\+0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 72 80[ ]*vpmovzxwq ymm30,QWORD PTR \[rdx-0x400\]
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 b2 f8 fb ff ff[ ]*vpmovzxwq ymm30,QWORD PTR \[rdx-0x408\]
#pass

300
gas/testsuite/gas/i386/x86-64-avx512f_vl-wig1.d Normal file
View file

@ -0,0 +1,300 @@
#as: -mevexwig=1
#objdump: -dw
#name: x86_64 AVX512F/VL wig insns
#source: x86-64-avx512f_vl-wig.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 21 f5[ ]*vpmovsxbd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 21 f5[ ]*vpmovsxbd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 21 f5[ ]*vpmovsxbd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 31[ ]*vpmovsxbd \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 21 b4 f0 23 01 00 00[ ]*vpmovsxbd 0x123\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 7f[ ]*vpmovsxbd 0x1fc\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 00 02 00 00[ ]*vpmovsxbd 0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 80[ ]*vpmovsxbd -0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 fc fd ff ff[ ]*vpmovsxbd -0x204\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 21 f5[ ]*vpmovsxbd %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 21 f5[ ]*vpmovsxbd %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 21 f5[ ]*vpmovsxbd %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 31[ ]*vpmovsxbd \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 21 b4 f0 23 01 00 00[ ]*vpmovsxbd 0x123\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 72 7f[ ]*vpmovsxbd 0x3f8\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 b2 00 04 00 00[ ]*vpmovsxbd 0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 72 80[ ]*vpmovsxbd -0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 b2 f8 fb ff ff[ ]*vpmovsxbd -0x408\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 22 f5[ ]*vpmovsxbq %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 22 f5[ ]*vpmovsxbq %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 22 f5[ ]*vpmovsxbq %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 31[ ]*vpmovsxbq \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 22 b4 f0 23 01 00 00[ ]*vpmovsxbq 0x123\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 72 7f[ ]*vpmovsxbq 0xfe\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 b2 00 01 00 00[ ]*vpmovsxbq 0x100\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 72 80[ ]*vpmovsxbq -0x100\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 b2 fe fe ff ff[ ]*vpmovsxbq -0x102\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 22 f5[ ]*vpmovsxbq %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 22 f5[ ]*vpmovsxbq %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 22 f5[ ]*vpmovsxbq %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 31[ ]*vpmovsxbq \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 22 b4 f0 23 01 00 00[ ]*vpmovsxbq 0x123\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 72 7f[ ]*vpmovsxbq 0x1fc\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 b2 00 02 00 00[ ]*vpmovsxbq 0x200\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 72 80[ ]*vpmovsxbq -0x200\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 b2 fc fd ff ff[ ]*vpmovsxbq -0x204\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 23 f5[ ]*vpmovsxwd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 23 f5[ ]*vpmovsxwd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 23 f5[ ]*vpmovsxwd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 31[ ]*vpmovsxwd \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 23 b4 f0 23 01 00 00[ ]*vpmovsxwd 0x123\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 72 7f[ ]*vpmovsxwd 0x3f8\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 b2 00 04 00 00[ ]*vpmovsxwd 0x400\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 72 80[ ]*vpmovsxwd -0x400\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 b2 f8 fb ff ff[ ]*vpmovsxwd -0x408\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 23 f5[ ]*vpmovsxwd %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 23 f5[ ]*vpmovsxwd %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 23 f5[ ]*vpmovsxwd %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 31[ ]*vpmovsxwd \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 23 b4 f0 23 01 00 00[ ]*vpmovsxwd 0x123\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 72 7f[ ]*vpmovsxwd 0x7f0\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 b2 00 08 00 00[ ]*vpmovsxwd 0x800\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 72 80[ ]*vpmovsxwd -0x800\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 b2 f0 f7 ff ff[ ]*vpmovsxwd -0x810\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 24 f5[ ]*vpmovsxwq %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 24 f5[ ]*vpmovsxwq %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 24 f5[ ]*vpmovsxwq %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 31[ ]*vpmovsxwq \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 24 b4 f0 23 01 00 00[ ]*vpmovsxwq 0x123\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 72 7f[ ]*vpmovsxwq 0x1fc\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 b2 00 02 00 00[ ]*vpmovsxwq 0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 72 80[ ]*vpmovsxwq -0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 b2 fc fd ff ff[ ]*vpmovsxwq -0x204\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 24 f5[ ]*vpmovsxwq %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 24 f5[ ]*vpmovsxwq %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 24 f5[ ]*vpmovsxwq %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 31[ ]*vpmovsxwq \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 24 b4 f0 23 01 00 00[ ]*vpmovsxwq 0x123\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 72 7f[ ]*vpmovsxwq 0x3f8\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 b2 00 04 00 00[ ]*vpmovsxwq 0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 72 80[ ]*vpmovsxwq -0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 b2 f8 fb ff ff[ ]*vpmovsxwq -0x408\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 31 f5[ ]*vpmovzxbd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 31 f5[ ]*vpmovzxbd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 31 f5[ ]*vpmovzxbd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 31[ ]*vpmovzxbd \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 31 b4 f0 23 01 00 00[ ]*vpmovzxbd 0x123\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 72 7f[ ]*vpmovzxbd 0x1fc\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 b2 00 02 00 00[ ]*vpmovzxbd 0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 72 80[ ]*vpmovzxbd -0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 b2 fc fd ff ff[ ]*vpmovzxbd -0x204\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 31 f5[ ]*vpmovzxbd %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 31 f5[ ]*vpmovzxbd %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 31 f5[ ]*vpmovzxbd %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 31[ ]*vpmovzxbd \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 31 b4 f0 23 01 00 00[ ]*vpmovzxbd 0x123\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 72 7f[ ]*vpmovzxbd 0x3f8\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 b2 00 04 00 00[ ]*vpmovzxbd 0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 72 80[ ]*vpmovzxbd -0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 b2 f8 fb ff ff[ ]*vpmovzxbd -0x408\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 32 f5[ ]*vpmovzxbq %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 32 f5[ ]*vpmovzxbq %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 32 f5[ ]*vpmovzxbq %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 31[ ]*vpmovzxbq \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 32 b4 f0 23 01 00 00[ ]*vpmovzxbq 0x123\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 72 7f[ ]*vpmovzxbq 0xfe\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 b2 00 01 00 00[ ]*vpmovzxbq 0x100\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 72 80[ ]*vpmovzxbq -0x100\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 b2 fe fe ff ff[ ]*vpmovzxbq -0x102\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 32 f5[ ]*vpmovzxbq %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 32 f5[ ]*vpmovzxbq %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 32 f5[ ]*vpmovzxbq %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 31[ ]*vpmovzxbq \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 32 b4 f0 23 01 00 00[ ]*vpmovzxbq 0x123\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 72 7f[ ]*vpmovzxbq 0x1fc\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 b2 00 02 00 00[ ]*vpmovzxbq 0x200\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 72 80[ ]*vpmovzxbq -0x200\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 b2 fc fd ff ff[ ]*vpmovzxbq -0x204\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 33 f5[ ]*vpmovzxwd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 33 f5[ ]*vpmovzxwd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 33 f5[ ]*vpmovzxwd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 31[ ]*vpmovzxwd \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 33 b4 f0 23 01 00 00[ ]*vpmovzxwd 0x123\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 72 7f[ ]*vpmovzxwd 0x3f8\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 b2 00 04 00 00[ ]*vpmovzxwd 0x400\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 72 80[ ]*vpmovzxwd -0x400\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 b2 f8 fb ff ff[ ]*vpmovzxwd -0x408\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 33 f5[ ]*vpmovzxwd %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 33 f5[ ]*vpmovzxwd %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 33 f5[ ]*vpmovzxwd %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 31[ ]*vpmovzxwd \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 33 b4 f0 23 01 00 00[ ]*vpmovzxwd 0x123\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 72 7f[ ]*vpmovzxwd 0x7f0\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 b2 00 08 00 00[ ]*vpmovzxwd 0x800\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 72 80[ ]*vpmovzxwd -0x800\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 b2 f0 f7 ff ff[ ]*vpmovzxwd -0x810\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 34 f5[ ]*vpmovzxwq %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 34 f5[ ]*vpmovzxwq %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 34 f5[ ]*vpmovzxwq %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 31[ ]*vpmovzxwq \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 34 b4 f0 23 01 00 00[ ]*vpmovzxwq 0x123\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 72 7f[ ]*vpmovzxwq 0x1fc\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 b2 00 02 00 00[ ]*vpmovzxwq 0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 72 80[ ]*vpmovzxwq -0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 b2 fc fd ff ff[ ]*vpmovzxwq -0x204\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 34 f5[ ]*vpmovzxwq %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 34 f5[ ]*vpmovzxwq %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 34 f5[ ]*vpmovzxwq %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 31[ ]*vpmovzxwq \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 34 b4 f0 23 01 00 00[ ]*vpmovzxwq 0x123\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 72 7f[ ]*vpmovzxwq 0x3f8\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 b2 00 04 00 00[ ]*vpmovzxwq 0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 72 80[ ]*vpmovzxwq -0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 b2 f8 fb ff ff[ ]*vpmovzxwq -0x408\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 21 f5[ ]*vpmovsxbd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 21 f5[ ]*vpmovsxbd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 21 f5[ ]*vpmovsxbd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 31[ ]*vpmovsxbd \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 21 b4 f0 34 12 00 00[ ]*vpmovsxbd 0x1234\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 7f[ ]*vpmovsxbd 0x1fc\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 00 02 00 00[ ]*vpmovsxbd 0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 80[ ]*vpmovsxbd -0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 fc fd ff ff[ ]*vpmovsxbd -0x204\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 21 f5[ ]*vpmovsxbd %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 21 f5[ ]*vpmovsxbd %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 21 f5[ ]*vpmovsxbd %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 31[ ]*vpmovsxbd \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 21 b4 f0 34 12 00 00[ ]*vpmovsxbd 0x1234\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 72 7f[ ]*vpmovsxbd 0x3f8\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 b2 00 04 00 00[ ]*vpmovsxbd 0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 72 80[ ]*vpmovsxbd -0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 21 b2 f8 fb ff ff[ ]*vpmovsxbd -0x408\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 22 f5[ ]*vpmovsxbq %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 22 f5[ ]*vpmovsxbq %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 22 f5[ ]*vpmovsxbq %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 31[ ]*vpmovsxbq \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 22 b4 f0 34 12 00 00[ ]*vpmovsxbq 0x1234\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 72 7f[ ]*vpmovsxbq 0xfe\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 b2 00 01 00 00[ ]*vpmovsxbq 0x100\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 72 80[ ]*vpmovsxbq -0x100\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 22 b2 fe fe ff ff[ ]*vpmovsxbq -0x102\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 22 f5[ ]*vpmovsxbq %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 22 f5[ ]*vpmovsxbq %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 22 f5[ ]*vpmovsxbq %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 31[ ]*vpmovsxbq \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 22 b4 f0 34 12 00 00[ ]*vpmovsxbq 0x1234\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 72 7f[ ]*vpmovsxbq 0x1fc\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 b2 00 02 00 00[ ]*vpmovsxbq 0x200\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 72 80[ ]*vpmovsxbq -0x200\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 b2 fc fd ff ff[ ]*vpmovsxbq -0x204\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 23 f5[ ]*vpmovsxwd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 23 f5[ ]*vpmovsxwd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 23 f5[ ]*vpmovsxwd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 31[ ]*vpmovsxwd \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 23 b4 f0 34 12 00 00[ ]*vpmovsxwd 0x1234\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 72 7f[ ]*vpmovsxwd 0x3f8\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 b2 00 04 00 00[ ]*vpmovsxwd 0x400\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 72 80[ ]*vpmovsxwd -0x400\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 23 b2 f8 fb ff ff[ ]*vpmovsxwd -0x408\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 23 f5[ ]*vpmovsxwd %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 23 f5[ ]*vpmovsxwd %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 23 f5[ ]*vpmovsxwd %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 31[ ]*vpmovsxwd \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 23 b4 f0 34 12 00 00[ ]*vpmovsxwd 0x1234\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 72 7f[ ]*vpmovsxwd 0x7f0\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 b2 00 08 00 00[ ]*vpmovsxwd 0x800\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 72 80[ ]*vpmovsxwd -0x800\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 23 b2 f0 f7 ff ff[ ]*vpmovsxwd -0x810\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 24 f5[ ]*vpmovsxwq %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 24 f5[ ]*vpmovsxwq %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 24 f5[ ]*vpmovsxwq %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 31[ ]*vpmovsxwq \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 24 b4 f0 34 12 00 00[ ]*vpmovsxwq 0x1234\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 72 7f[ ]*vpmovsxwq 0x1fc\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 b2 00 02 00 00[ ]*vpmovsxwq 0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 72 80[ ]*vpmovsxwq -0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 b2 fc fd ff ff[ ]*vpmovsxwq -0x204\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 24 f5[ ]*vpmovsxwq %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 24 f5[ ]*vpmovsxwq %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 24 f5[ ]*vpmovsxwq %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 31[ ]*vpmovsxwq \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 24 b4 f0 34 12 00 00[ ]*vpmovsxwq 0x1234\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 72 7f[ ]*vpmovsxwq 0x3f8\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 b2 00 04 00 00[ ]*vpmovsxwq 0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 72 80[ ]*vpmovsxwq -0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 24 b2 f8 fb ff ff[ ]*vpmovsxwq -0x408\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 31 f5[ ]*vpmovzxbd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 31 f5[ ]*vpmovzxbd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 31 f5[ ]*vpmovzxbd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 31[ ]*vpmovzxbd \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 31 b4 f0 34 12 00 00[ ]*vpmovzxbd 0x1234\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 72 7f[ ]*vpmovzxbd 0x1fc\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 b2 00 02 00 00[ ]*vpmovzxbd 0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 72 80[ ]*vpmovzxbd -0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 b2 fc fd ff ff[ ]*vpmovzxbd -0x204\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 31 f5[ ]*vpmovzxbd %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 31 f5[ ]*vpmovzxbd %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 31 f5[ ]*vpmovzxbd %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 31[ ]*vpmovzxbd \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 31 b4 f0 34 12 00 00[ ]*vpmovzxbd 0x1234\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 72 7f[ ]*vpmovzxbd 0x3f8\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 b2 00 04 00 00[ ]*vpmovzxbd 0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 72 80[ ]*vpmovzxbd -0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 31 b2 f8 fb ff ff[ ]*vpmovzxbd -0x408\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 32 f5[ ]*vpmovzxbq %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 32 f5[ ]*vpmovzxbq %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 32 f5[ ]*vpmovzxbq %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 31[ ]*vpmovzxbq \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 32 b4 f0 34 12 00 00[ ]*vpmovzxbq 0x1234\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 72 7f[ ]*vpmovzxbq 0xfe\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 b2 00 01 00 00[ ]*vpmovzxbq 0x100\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 72 80[ ]*vpmovzxbq -0x100\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 32 b2 fe fe ff ff[ ]*vpmovzxbq -0x102\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 32 f5[ ]*vpmovzxbq %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 32 f5[ ]*vpmovzxbq %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 32 f5[ ]*vpmovzxbq %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 31[ ]*vpmovzxbq \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 32 b4 f0 34 12 00 00[ ]*vpmovzxbq 0x1234\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 72 7f[ ]*vpmovzxbq 0x1fc\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 b2 00 02 00 00[ ]*vpmovzxbq 0x200\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 72 80[ ]*vpmovzxbq -0x200\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 b2 fc fd ff ff[ ]*vpmovzxbq -0x204\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 33 f5[ ]*vpmovzxwd %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 33 f5[ ]*vpmovzxwd %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 33 f5[ ]*vpmovzxwd %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 31[ ]*vpmovzxwd \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 33 b4 f0 34 12 00 00[ ]*vpmovzxwd 0x1234\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 72 7f[ ]*vpmovzxwd 0x3f8\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 b2 00 04 00 00[ ]*vpmovzxwd 0x400\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 72 80[ ]*vpmovzxwd -0x400\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 33 b2 f8 fb ff ff[ ]*vpmovzxwd -0x408\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 33 f5[ ]*vpmovzxwd %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 33 f5[ ]*vpmovzxwd %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 33 f5[ ]*vpmovzxwd %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 31[ ]*vpmovzxwd \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 33 b4 f0 34 12 00 00[ ]*vpmovzxwd 0x1234\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 72 7f[ ]*vpmovzxwd 0x7f0\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 b2 00 08 00 00[ ]*vpmovzxwd 0x800\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 72 80[ ]*vpmovzxwd -0x800\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 33 b2 f0 f7 ff ff[ ]*vpmovzxwd -0x810\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 08 34 f5[ ]*vpmovzxwq %xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 34 f5[ ]*vpmovzxwq %xmm29,%xmm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 34 f5[ ]*vpmovzxwq %xmm29,%xmm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 31[ ]*vpmovzxwq \(%rcx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 08 34 b4 f0 34 12 00 00[ ]*vpmovzxwq 0x1234\(%rax,%r14,8\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 72 7f[ ]*vpmovzxwq 0x1fc\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 b2 00 02 00 00[ ]*vpmovzxwq 0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 72 80[ ]*vpmovzxwq -0x200\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 08 34 b2 fc fd ff ff[ ]*vpmovzxwq -0x204\(%rdx\),%xmm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 28 34 f5[ ]*vpmovzxwq %xmm29,%ymm30
[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 34 f5[ ]*vpmovzxwq %xmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 02 fd af 34 f5[ ]*vpmovzxwq %xmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 31[ ]*vpmovzxwq \(%rcx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 22 fd 28 34 b4 f0 34 12 00 00[ ]*vpmovzxwq 0x1234\(%rax,%r14,8\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 72 7f[ ]*vpmovzxwq 0x3f8\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 b2 00 04 00 00[ ]*vpmovzxwq 0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 72 80[ ]*vpmovzxwq -0x400\(%rdx\),%ymm30
[ ]*[a-f0-9]+:[ ]*62 62 fd 28 34 b2 f8 fb ff ff[ ]*vpmovzxwq -0x408\(%rdx\),%ymm30
#pass

12626
gas/testsuite/gas/i386/x86-64-avx512f_vl.d Normal file
View file

File diff suppressed because it is too large Load diff

12621
gas/testsuite/gas/i386/x86-64-avx512f_vl.s Normal file
View file

File diff suppressed because it is too large Load diff

23
opcodes/ChangeLog
View file

@ -1,3 +1,26 @@
2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis.c (intel_operand_size): Support 128/256 length in
vex_vsib_q_w_dq_mode.
(OP_E_memory): Add ymmq_mode handling, handle new broadcast.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
(cpu_flags): Add CpuAVX512VL.
* i386-init.h: Regenerated.
* i386-opc.h (CpuAVX512VL): New.
(i386_cpu_flags): Add cpuavx512vl.
(BROADCAST_1TO4, BROADCAST_1TO2): Define.
* i386-opc.tbl: Add AVX512VL instructions.
* i386-tbl.h: Regenerate.
2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,

70
opcodes/i386-dis.c
View file

@ -14114,17 +14114,41 @@ intel_operand_size (int bytemode, int sizeflag)
}
else
{
if (vex.length != 512)
abort ();
oappend ("ZMMWORD PTR ");
switch (vex.length)
{
case 128:
oappend ("XMMWORD PTR ");
break;
case 256:
oappend ("YMMWORD PTR ");
break;
case 512:
oappend ("ZMMWORD PTR ");
break;
default:
abort ();
}
}
break;
case vex_vsib_q_w_d_mode:
case vex_vsib_d_w_d_mode:
if (!need_vex || !vex.evex || vex.length != 512)
if (!need_vex || !vex.evex)
abort ();
oappend ("YMMWORD PTR ");
switch (vex.length)
{
case 128:
oappend ("QWORD PTR ");
break;
case 256:
oappend ("XMMWORD PTR ");
break;
case 512:
oappend ("YMMWORD PTR ");
break;
default:
abort ();
}
break;
case mask_mode:
@ -14324,6 +14348,8 @@ OP_E_memory (int bytemode, int sizeflag)
shift -= 2;
else if (bytemode == xmmdw_mode)
shift -= 3;
else if (bytemode == ymmq_mode && vex.length == 128)
shift -= 1;
}
else
shift = 0;
@ -14621,9 +14647,39 @@ OP_E_memory (int bytemode, int sizeflag)
|| bytemode == evex_half_bcst_xmmq_mode))
{
if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
oappend ("{1to8}");
{
switch (vex.length)
{
case 128:
oappend ("{1to2}");
break;
case 256:
oappend ("{1to4}");
break;
case 512:
oappend ("{1to8}");
break;
default:
abort ();
}
}
else
oappend ("{1to16}");
{
switch (vex.length)
{
case 128:
oappend ("{1to4}");
break;
case 256:
oappend ("{1to8}");
break;
case 512:
oappend ("{1to16}");
break;
default:
abort ();
}
}
}
}

3
opcodes/i386-gen.c
View file

@ -231,6 +231,8 @@ static initializer cpu_flag_init[] =
"CpuPREFETCHWT1" },
{ "CPU_SE1_FLAGS",
"CpuSE1" },
{ "CPU_AVX512VL_FLAGS",
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512VL" },
};
static initializer operand_type_init[] =
@ -379,6 +381,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX512CD),
BITFIELD (CpuAVX512ER),
BITFIELD (CpuAVX512PF),
BITFIELD (CpuAVX512VL),
BITFIELD (CpuL1OM),
BITFIELD (CpuK1OM),
BITFIELD (CpuSSE4a),

280
opcodes/i386-init.h
View file

@ -20,573 +20,579 @@
#define CPU_UNKNOWN_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
#define CPU_GENERIC32_FLAGS \
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_GENERIC64_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_NONE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I186_FLAGS \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I286_FLAGS \
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I386_FLAGS \
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I486_FLAGS \
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I586_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I686_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PENTIUMPRO_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P3_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P4_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_NOCONA_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CORE_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CORE2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_COREI7_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_K6_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_K6_2_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ATHLON_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_K8_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AMDFAM10_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BDVER1_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, \
1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BDVER2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, \
1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, \
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, \
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BDVER3_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, \
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, \
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BDVER4_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, \
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BTVER1_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BTVER2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, \
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
1, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, \
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_8087_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_287_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_387_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY87_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CLFLUSH_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_NOP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SYSCALL_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_MMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE3_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSSE3_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4_1_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4_2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_SSE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_VMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_XSAVE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_XSAVEOPT_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AES_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PCLMUL_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_FMA_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_FMA4_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_XOP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_LWP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BMI_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_TBM_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_MOVBE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CX16_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_RDTSCP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_EPT_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_FSGSBASE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_RDRND_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_F16C_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BMI2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_LZCNT_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_HLE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_RTM_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_INVPCID_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_VMFUNC_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_3DNOW_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_3DNOWA_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PADLOCK_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SVME_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4A_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ABM_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512F_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512CD_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512ER_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512PF_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_AVX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_L1OM_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
#define CPU_K1OM_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
#define CPU_ADX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_RDSEED_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PRFCHW_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SMAP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_MPX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SHA_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CLFLUSHOPT_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_XSAVES_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
#define CPU_XSAVEC_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
#define CPU_PREFETCHWT1_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
#define CPU_SE1_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
#define CPU_AVX512VL_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_NONE \

5
opcodes/i386-opc.h
View file

@ -102,6 +102,8 @@ enum
CpuAVX512ER,
/* Intel AVX-512 Prefetch Instructions support required */
CpuAVX512PF,
/* Intel AVX-512 VL Instructions support required. */
CpuAVX512VL,
/* Intel L1OM support required */
CpuL1OM,
/* Intel K1OM support required */
@ -236,6 +238,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx512cd:1;
unsigned int cpuavx512er:1;
unsigned int cpuavx512pf:1;
unsigned int cpuavx512vl:1;
unsigned int cpul1om:1;
unsigned int cpuk1om:1;
unsigned int cpuxsave:1;
@ -492,6 +495,8 @@ enum
#define NO_BROADCAST 0
#define BROADCAST_1TO16 1
#define BROADCAST_1TO8 2
#define BROADCAST_1TO4 3
#define BROADCAST_1TO2 4
Broadcast,
/* Static rounding control is supported. */

944
opcodes/i386-opc.tbl
View file

@ -4321,3 +4321,947 @@ encls, 0, 0xf01cf, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l
enclu, 0, 0xf01d7, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
// SGX instructions end.
// AVX512VL instructions.
vaddpd, 3, 0x6658, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vaddpd, 3, 0x6658, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vdivpd, 3, 0x665E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vdivpd, 3, 0x665E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vmulpd, 3, 0x6659, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vmulpd, 3, 0x6659, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vsqrtpd, 2, 0x6651, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vsqrtpd, 2, 0x6651, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vsubpd, 3, 0x665C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vsubpd, 3, 0x665C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vaddps, 3, 0x58, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vaddps, 3, 0x58, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vcvtdq2ps, 2, 0x5B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtdq2ps, 2, 0x5B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vcvtps2udq, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtps2udq, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vdivps, 3, 0x5E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vdivps, 3, 0x5E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vmulps, 3, 0x59, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vmulps, 3, 0x59, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vsqrtps, 2, 0x51, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vsqrtps, 2, 0x51, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vsubps, 3, 0x5C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vsubps, 3, 0x5C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
valignd, 4, 0x6603, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
valignd, 4, 0x6603, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermilps, 3, 0x6604, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpermilps, 3, 0x6604, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpternlogd, 4, 0x6625, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpternlogd, 4, 0x6625, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vshuff32x4, 4, 0x6623, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vshufi32x4, 4, 0x6643, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
valignq, 4, 0x6603, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
valignq, 4, 0x6603, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermilpd, 3, 0x6605, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpermilpd, 3, 0x6605, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpermpd, 3, 0x6601, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpermq, 3, 0x6600, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpternlogq, 4, 0x6625, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpternlogq, 4, 0x6625, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vshuff64x2, 4, 0x6623, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vshufi64x2, 4, 0x6643, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vblendmpd, 3, 0x6665, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vblendmpd, 3, 0x6665, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpabsq, 2, 0x661F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpabsq, 2, 0x661F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpblendmq, 3, 0x6664, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpblendmq, 3, 0x6664, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermi2pd, 3, 0x6677, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpermi2pd, 3, 0x6677, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermi2q, 3, 0x6676, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpermi2q, 3, 0x6676, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermilpd, 3, 0x660D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpermilpd, 3, 0x660D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermpd, 3, 0x6616, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermq, 3, 0x6636, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermt2pd, 3, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpermt2pd, 3, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermt2q, 3, 0x667E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpermt2q, 3, 0x667E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpmaxsq, 3, 0x663D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpmaxsq, 3, 0x663D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpmaxuq, 3, 0x663F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpmaxuq, 3, 0x663F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpminsq, 3, 0x6639, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpminsq, 3, 0x6639, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpminuq, 3, 0x663B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpminuq, 3, 0x663B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpmuldq, 3, 0x6628, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpmuldq, 3, 0x6628, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vprolvq, 3, 0x6615, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vprolvq, 3, 0x6615, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vprorvq, 3, 0x6614, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vprorvq, 3, 0x6614, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpsllvq, 3, 0x6647, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsllvq, 3, 0x6647, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpsravq, 3, 0x6646, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsravq, 3, 0x6646, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpsrlvq, 3, 0x6645, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsrlvq, 3, 0x6645, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vrcp14pd, 2, 0x664C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vrcp14pd, 2, 0x664C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vrsqrt14pd, 2, 0x664E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vrsqrt14pd, 2, 0x664E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vblendmps, 3, 0x6665, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vblendmps, 3, 0x6665, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpabsd, 2, 0x661E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpabsd, 2, 0x661E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpblendmd, 3, 0x6664, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpblendmd, 3, 0x6664, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermd, 3, 0x6636, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermi2d, 3, 0x6676, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpermi2d, 3, 0x6676, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermi2ps, 3, 0x6677, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpermi2ps, 3, 0x6677, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermilps, 3, 0x660C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpermilps, 3, 0x660C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermps, 3, 0x6616, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermt2d, 3, 0x667E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpermt2d, 3, 0x667E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpermt2ps, 3, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpermt2ps, 3, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpmaxsd, 3, 0x663D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpmaxsd, 3, 0x663D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpmaxud, 3, 0x663F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpmaxud, 3, 0x663F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpminsd, 3, 0x6639, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpminsd, 3, 0x6639, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpminud, 3, 0x663B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpminud, 3, 0x663B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpmulld, 3, 0x6640, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpmulld, 3, 0x6640, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vprolvd, 3, 0x6615, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vprolvd, 3, 0x6615, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vprorvd, 3, 0x6614, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vprorvd, 3, 0x6614, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpsllvd, 3, 0x6647, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsllvd, 3, 0x6647, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpsravd, 3, 0x6646, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsravd, 3, 0x6646, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpsrlvd, 3, 0x6645, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsrlvd, 3, 0x6645, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vrcp14ps, 2, 0x664C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vrcp14ps, 2, 0x664C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vrsqrt14ps, 2, 0x664E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vrsqrt14ps, 2, 0x664E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vbroadcastf32x4, 2, 0x661A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vbroadcasti32x4, 2, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vbroadcastss, 2, 0x6618, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vbroadcastss, 2, 0x6618, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vcompressps, 2, 0x668A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vcompressps, 2, 0x668A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vexpandps, 2, 0x6688, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vexpandps, 2, 0x6688, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpbroadcastd, 2, 0x6658, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpbroadcastd, 2, 0x6658, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, RegXMM }
vpbroadcastd, 2, 0x6658, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpbroadcastd, 2, 0x6658, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, RegYMM }
vpbroadcastd, 2, 0x667C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegXMM }
vpbroadcastd, 2, 0x667C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegYMM }
vpcompressd, 2, 0x668B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpcompressd, 2, 0x668B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vpexpandd, 2, 0x6689, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpexpandd, 2, 0x6689, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vbroadcastsd, 2, 0x6619, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vcompresspd, 2, 0x668A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vcompresspd, 2, 0x668A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vexpandpd, 2, 0x6688, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vexpandpd, 2, 0x6688, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpbroadcastq, 2, 0x6659, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpbroadcastq, 2, 0x6659, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, RegXMM }
vpbroadcastq, 2, 0x6659, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpbroadcastq, 2, 0x6659, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, RegYMM }
vpbroadcastq, 2, 0x667C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64, RegXMM }
vpbroadcastq, 2, 0x667C, None, 1, CpuAVX512F|CpuAVX512VL|Cpu64, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64, RegYMM }
vpcompressq, 2, 0x668B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpcompressq, 2, 0x668B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vpexpandq, 2, 0x6689, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpexpandq, 2, 0x6689, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vcmpeq_oqpd, 3, 0x66C2, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpeq_oqpd, 3, 0x66C2, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpeq_ospd, 3, 0x66C2, 16, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpeq_ospd, 3, 0x66C2, 16, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpeq_uqpd, 3, 0x66C2, 8, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpeq_uqpd, 3, 0x66C2, 8, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpeq_uspd, 3, 0x66C2, 24, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpeq_uspd, 3, 0x66C2, 24, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpeqpd, 3, 0x66C2, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpeqpd, 3, 0x66C2, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpfalse_oqpd, 3, 0x66C2, 11, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpfalse_oqpd, 3, 0x66C2, 11, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpfalse_ospd, 3, 0x66C2, 27, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpfalse_ospd, 3, 0x66C2, 27, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpfalsepd, 3, 0x66C2, 11, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpfalsepd, 3, 0x66C2, 11, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpge_oqpd, 3, 0x66C2, 29, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpge_oqpd, 3, 0x66C2, 29, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpge_ospd, 3, 0x66C2, 13, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpge_ospd, 3, 0x66C2, 13, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpgepd, 3, 0x66C2, 13, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpgepd, 3, 0x66C2, 13, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpgt_oqpd, 3, 0x66C2, 30, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpgt_oqpd, 3, 0x66C2, 30, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpgt_ospd, 3, 0x66C2, 14, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpgt_ospd, 3, 0x66C2, 14, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpgtpd, 3, 0x66C2, 14, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpgtpd, 3, 0x66C2, 14, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmple_oqpd, 3, 0x66C2, 18, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmple_oqpd, 3, 0x66C2, 18, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmple_ospd, 3, 0x66C2, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmple_ospd, 3, 0x66C2, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmplepd, 3, 0x66C2, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmplepd, 3, 0x66C2, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmplt_oqpd, 3, 0x66C2, 17, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmplt_oqpd, 3, 0x66C2, 17, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmplt_ospd, 3, 0x66C2, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmplt_ospd, 3, 0x66C2, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpltpd, 3, 0x66C2, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpltpd, 3, 0x66C2, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpneq_oqpd, 3, 0x66C2, 12, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpneq_oqpd, 3, 0x66C2, 12, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpneq_ospd, 3, 0x66C2, 28, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpneq_ospd, 3, 0x66C2, 28, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpneq_uqpd, 3, 0x66C2, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpneq_uqpd, 3, 0x66C2, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpneq_uspd, 3, 0x66C2, 20, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpneq_uspd, 3, 0x66C2, 20, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpneqpd, 3, 0x66C2, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpneqpd, 3, 0x66C2, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnge_uqpd, 3, 0x66C2, 25, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnge_uqpd, 3, 0x66C2, 25, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnge_uspd, 3, 0x66C2, 9, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnge_uspd, 3, 0x66C2, 9, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpngepd, 3, 0x66C2, 9, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpngepd, 3, 0x66C2, 9, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpngt_uqpd, 3, 0x66C2, 26, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpngt_uqpd, 3, 0x66C2, 26, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpngt_uspd, 3, 0x66C2, 10, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpngt_uspd, 3, 0x66C2, 10, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpngtpd, 3, 0x66C2, 10, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpngtpd, 3, 0x66C2, 10, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnle_uqpd, 3, 0x66C2, 22, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnle_uqpd, 3, 0x66C2, 22, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnle_uspd, 3, 0x66C2, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnle_uspd, 3, 0x66C2, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnlepd, 3, 0x66C2, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnlepd, 3, 0x66C2, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnlt_uqpd, 3, 0x66C2, 21, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnlt_uqpd, 3, 0x66C2, 21, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnlt_uspd, 3, 0x66C2, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnlt_uspd, 3, 0x66C2, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnltpd, 3, 0x66C2, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnltpd, 3, 0x66C2, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpord_qpd, 3, 0x66C2, 7, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpord_qpd, 3, 0x66C2, 7, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpord_spd, 3, 0x66C2, 23, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpord_spd, 3, 0x66C2, 23, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpordpd, 3, 0x66C2, 7, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpordpd, 3, 0x66C2, 7, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmppd, 4, 0x66C2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmppd, 4, 0x66C2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmptrue_uqpd, 3, 0x66C2, 15, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmptrue_uqpd, 3, 0x66C2, 15, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmptrue_uspd, 3, 0x66C2, 31, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmptrue_uspd, 3, 0x66C2, 31, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmptruepd, 3, 0x66C2, 15, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmptruepd, 3, 0x66C2, 15, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpunord_qpd, 3, 0x66C2, 3, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpunord_qpd, 3, 0x66C2, 3, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpunord_spd, 3, 0x66C2, 19, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpunord_spd, 3, 0x66C2, 19, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpunordpd, 3, 0x66C2, 3, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpunordpd, 3, 0x66C2, 3, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpeq_oqps, 3, 0xC2, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpeq_oqps, 3, 0xC2, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpeq_osps, 3, 0xC2, 16, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpeq_osps, 3, 0xC2, 16, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpeq_uqps, 3, 0xC2, 8, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpeq_uqps, 3, 0xC2, 8, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpeq_usps, 3, 0xC2, 24, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpeq_usps, 3, 0xC2, 24, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpeqps, 3, 0xC2, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpeqps, 3, 0xC2, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpfalse_oqps, 3, 0xC2, 11, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpfalse_oqps, 3, 0xC2, 11, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpfalse_osps, 3, 0xC2, 27, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpfalse_osps, 3, 0xC2, 27, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpfalseps, 3, 0xC2, 11, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpfalseps, 3, 0xC2, 11, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpge_oqps, 3, 0xC2, 29, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpge_oqps, 3, 0xC2, 29, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpge_osps, 3, 0xC2, 13, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpge_osps, 3, 0xC2, 13, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpgeps, 3, 0xC2, 13, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpgeps, 3, 0xC2, 13, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpgt_oqps, 3, 0xC2, 30, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpgt_oqps, 3, 0xC2, 30, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpgt_osps, 3, 0xC2, 14, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpgt_osps, 3, 0xC2, 14, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpgtps, 3, 0xC2, 14, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpgtps, 3, 0xC2, 14, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmple_oqps, 3, 0xC2, 18, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmple_oqps, 3, 0xC2, 18, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmple_osps, 3, 0xC2, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmple_osps, 3, 0xC2, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpleps, 3, 0xC2, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpleps, 3, 0xC2, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmplt_oqps, 3, 0xC2, 17, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmplt_oqps, 3, 0xC2, 17, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmplt_osps, 3, 0xC2, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmplt_osps, 3, 0xC2, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpltps, 3, 0xC2, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpltps, 3, 0xC2, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpneq_oqps, 3, 0xC2, 12, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpneq_oqps, 3, 0xC2, 12, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpneq_osps, 3, 0xC2, 28, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpneq_osps, 3, 0xC2, 28, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpneq_uqps, 3, 0xC2, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpneq_uqps, 3, 0xC2, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpneq_usps, 3, 0xC2, 20, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpneq_usps, 3, 0xC2, 20, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpneqps, 3, 0xC2, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpneqps, 3, 0xC2, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnge_uqps, 3, 0xC2, 25, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnge_uqps, 3, 0xC2, 25, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnge_usps, 3, 0xC2, 9, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnge_usps, 3, 0xC2, 9, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpngeps, 3, 0xC2, 9, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpngeps, 3, 0xC2, 9, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpngt_uqps, 3, 0xC2, 26, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpngt_uqps, 3, 0xC2, 26, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpngt_usps, 3, 0xC2, 10, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpngt_usps, 3, 0xC2, 10, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpngtps, 3, 0xC2, 10, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpngtps, 3, 0xC2, 10, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnle_uqps, 3, 0xC2, 22, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnle_uqps, 3, 0xC2, 22, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnle_usps, 3, 0xC2, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnle_usps, 3, 0xC2, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnleps, 3, 0xC2, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnleps, 3, 0xC2, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnlt_uqps, 3, 0xC2, 21, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnlt_uqps, 3, 0xC2, 21, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnlt_usps, 3, 0xC2, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnlt_usps, 3, 0xC2, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpnltps, 3, 0xC2, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpnltps, 3, 0xC2, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpord_qps, 3, 0xC2, 7, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpord_qps, 3, 0xC2, 7, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpord_sps, 3, 0xC2, 23, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpord_sps, 3, 0xC2, 23, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpordps, 3, 0xC2, 7, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpordps, 3, 0xC2, 7, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpps, 4, 0xC2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpps, 4, 0xC2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmptrue_uqps, 3, 0xC2, 15, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmptrue_uqps, 3, 0xC2, 15, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmptrue_usps, 3, 0xC2, 31, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmptrue_usps, 3, 0xC2, 31, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmptrueps, 3, 0xC2, 15, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmptrueps, 3, 0xC2, 15, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpunord_qps, 3, 0xC2, 3, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpunord_qps, 3, 0xC2, 3, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpunord_sps, 3, 0xC2, 19, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpunord_sps, 3, 0xC2, 19, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcmpunordps, 3, 0xC2, 3, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vcmpunordps, 3, 0xC2, 3, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vcompresspd, 2, 0x668A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vcompresspd, 2, 0x668A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vgatherdpd, 2, 0x6692, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vgatherdpd, 2, 0x6692, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vgatherqpd, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vgatherqpd, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpcompressq, 2, 0x668B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpcompressq, 2, 0x668B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpgatherdq, 2, 0x6690, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpgatherdq, 2, 0x6690, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpgatherqq, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpgatherqq, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpscatterdq, 2, 0x66A0, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpscatterdq, 2, 0x66A0, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpscatterqq, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpscatterqq, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vscatterdpd, 2, 0x66A2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vscatterdpd, 2, 0x66A2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vscatterqpd, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vscatterqpd, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|VecESize=1|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vcompressps, 2, 0x668A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vcompressps, 2, 0x668A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vgatherdps, 2, 0x6692, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vgatherdps, 2, 0x6692, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vgatherqps, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vgatherqps, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovntdqa, 2, 0x662A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovntdqa, 2, 0x662A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpcompressd, 2, 0x668B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpcompressd, 2, 0x668B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpgatherdd, 2, 0x6690, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpgatherdd, 2, 0x6690, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpgatherqd, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpgatherqd, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpscatterdd, 2, 0x66A0, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpscatterdd, 2, 0x66A0, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpscatterqd, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpscatterqd, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vscatterdps, 2, 0x66A2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vscatterdps, 2, 0x66A2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vscatterqps, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vscatterqps, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vcvtdq2pd, 2, 0xF3E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=4|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtdq2pd, 2, 0xF3E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vcvtudq2pd, 2, 0xF37A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=4|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtudq2pd, 2, 0xF37A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vcvtpd2dq, 2, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2dqx, 2, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2dq, 2, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2dqy, 2, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2ps, 2, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2psx, 2, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2ps, 2, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2psy, 2, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2udq, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2udqx, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2udq, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtpd2udqy, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtph2ps, 2, 0x6613, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtph2ps, 2, 0x6613, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vcvtps2dq, 2, 0x665B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtps2dq, 2, 0x665B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vcvtps2pd, 2, 0x5A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=4|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtps2pd, 2, 0x5A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM|RegMem }
vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegXMM|RegMem }
vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vcvttpd2dq, 2, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvttpd2dqx, 2, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvttpd2dq, 2, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvttpd2dqy, 2, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvttpd2udq, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvttpd2udqx, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvttpd2udq, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvttpd2udqy, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvttps2dq, 2, 0xF35B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvttps2dq, 2, 0xF35B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vcvttps2udq, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvttps2udq, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmaxps, 3, 0x5F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vmaxps, 3, 0x5F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vminps, 3, 0x5D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vminps, 3, 0x5D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vcvtudq2ps, 2, 0xF27A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vcvtudq2ps, 2, 0xF27A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vextractf32x4, 3, 0x6619, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vextracti32x4, 3, 0x6639, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vextractf32x4, 3, 0x6619, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegXMM|RegMem }
vextracti32x4, 3, 0x6639, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegXMM|RegMem }
vinsertf32x4, 4, 0x6618, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vinserti32x4, 4, 0x6638, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfixupimmpd, 4, 0x6654, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfixupimmpd, 4, 0x6654, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vgetmantpd, 3, 0x6626, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vgetmantpd, 3, 0x6626, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vrndscalepd, 3, 0x6609, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vrndscalepd, 3, 0x6609, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vfixupimmps, 4, 0x6654, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfixupimmps, 4, 0x6654, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vgetmantps, 3, 0x6626, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vgetmantps, 3, 0x6626, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vrndscaleps, 3, 0x6608, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vrndscaleps, 3, 0x6608, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vfmadd132pd, 3, 0x6698, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmadd132pd, 3, 0x6698, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmadd213pd, 3, 0x66A8, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmadd213pd, 3, 0x66A8, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmadd231pd, 3, 0x66B8, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmadd231pd, 3, 0x66B8, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmaddsub132pd, 3, 0x6696, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmaddsub132pd, 3, 0x6696, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmaddsub213pd, 3, 0x66A6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmaddsub213pd, 3, 0x66A6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmaddsub231pd, 3, 0x66B6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmaddsub231pd, 3, 0x66B6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsub132pd, 3, 0x669A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsub132pd, 3, 0x669A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsub213pd, 3, 0x66AA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsub213pd, 3, 0x66AA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsub231pd, 3, 0x66BA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsub231pd, 3, 0x66BA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsubadd132pd, 3, 0x6697, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsubadd132pd, 3, 0x6697, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsubadd213pd, 3, 0x66A7, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsubadd213pd, 3, 0x66A7, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsubadd231pd, 3, 0x66B7, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsubadd231pd, 3, 0x66B7, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmadd132pd, 3, 0x669C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmadd132pd, 3, 0x669C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmadd213pd, 3, 0x66AC, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmadd213pd, 3, 0x66AC, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmadd231pd, 3, 0x66BC, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmadd231pd, 3, 0x66BC, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmsub132pd, 3, 0x669E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmsub132pd, 3, 0x669E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmsub213pd, 3, 0x66AE, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmsub213pd, 3, 0x66AE, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmsub231pd, 3, 0x66BE, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmsub231pd, 3, 0x66BE, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vscalefpd, 3, 0x662C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vscalefpd, 3, 0x662C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmadd132ps, 3, 0x6698, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmadd132ps, 3, 0x6698, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmadd213ps, 3, 0x66A8, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmadd213ps, 3, 0x66A8, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmadd231ps, 3, 0x66B8, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmadd231ps, 3, 0x66B8, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmaddsub132ps, 3, 0x6696, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmaddsub132ps, 3, 0x6696, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmaddsub213ps, 3, 0x66A6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmaddsub213ps, 3, 0x66A6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmaddsub231ps, 3, 0x66B6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmaddsub231ps, 3, 0x66B6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsub132ps, 3, 0x669A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsub132ps, 3, 0x669A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsub213ps, 3, 0x66AA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsub213ps, 3, 0x66AA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsub231ps, 3, 0x66BA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsub231ps, 3, 0x66BA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsubadd132ps, 3, 0x6697, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsubadd132ps, 3, 0x6697, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsubadd213ps, 3, 0x66A7, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsubadd213ps, 3, 0x66A7, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfmsubadd231ps, 3, 0x66B7, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfmsubadd231ps, 3, 0x66B7, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmadd132ps, 3, 0x669C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmadd132ps, 3, 0x669C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmadd213ps, 3, 0x66AC, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmadd213ps, 3, 0x66AC, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmadd231ps, 3, 0x66BC, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmadd231ps, 3, 0x66BC, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmsub132ps, 3, 0x669E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmsub132ps, 3, 0x669E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmsub213ps, 3, 0x66AE, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmsub213ps, 3, 0x66AE, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vfnmsub231ps, 3, 0x66BE, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vfnmsub231ps, 3, 0x66BE, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vscalefps, 3, 0x662C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vscalefps, 3, 0x662C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vgetexppd, 2, 0x6642, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vgetexppd, 2, 0x6642, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vgetexpps, 2, 0x6642, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vgetexpps, 2, 0x6642, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmaxpd, 3, 0x665F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vmaxpd, 3, 0x665F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vminpd, 3, 0x665D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vminpd, 3, 0x665D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vmovapd, 2, 0x6629, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovapd, 2, 0x6629, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovdqa64, 2, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovdqa64, 2, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovntpd, 2, 0x662B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovntpd, 2, 0x662B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovupd, 2, 0x6611, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovupd, 2, 0x6611, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovapd, 2, 0x6628, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovapd, 2, 0x6628, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovapd, 2, 0x6628, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
vmovapd, 2, 0x6628, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM }
vmovapd, 2, 0x6629, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vmovapd, 2, 0x6629, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vmovdqa64, 2, 0x666F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovdqa64, 2, 0x666F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovdqa64, 2, 0x666F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
vmovdqa64, 2, 0x666F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM }
vmovdqa64, 2, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vmovdqa64, 2, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vmovupd, 2, 0x6610, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovupd, 2, 0x6610, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovupd, 2, 0x6610, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
vmovupd, 2, 0x6610, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM }
vmovupd, 2, 0x6611, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vmovupd, 2, 0x6611, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vpsllq, 3, 0x66F3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsllq, 3, 0x66F3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpsraq, 3, 0x66E2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsraq, 3, 0x66E2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpsrlq, 3, 0x66D3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsrlq, 3, 0x66D3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vmovaps, 2, 0x28, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovaps, 2, 0x28, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovaps, 2, 0x28, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=2|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
vmovaps, 2, 0x28, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=3|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM }
vmovaps, 2, 0x29, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vmovaps, 2, 0x29, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vmovups, 2, 0x10, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovups, 2, 0x10, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovups, 2, 0x10, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=2|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
vmovups, 2, 0x10, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=3|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM }
vmovups, 2, 0x11, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vmovups, 2, 0x11, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vmovaps, 2, 0x29, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovaps, 2, 0x29, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovntps, 2, 0x2B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovntps, 2, 0x2B, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovups, 2, 0x11, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovups, 2, 0x11, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovddup, 2, 0xF212, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovddup, 2, 0xF212, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovdqa32, 2, 0x666F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovdqa32, 2, 0x666F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovdqa32, 2, 0x666F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=2|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
vmovdqa32, 2, 0x666F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=3|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM }
vmovdqa32, 2, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vmovdqa32, 2, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vpslld, 3, 0x66F2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpslld, 3, 0x66F2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpsrad, 3, 0x66E2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsrad, 3, 0x66E2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpsrld, 3, 0x66D2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsrld, 3, 0x66D2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vmovdqa32, 2, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovdqa32, 2, 0x667F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovntdq, 2, 0x66E7, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovntdq, 2, 0x66E7, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovdqu32, 2, 0xF37F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovdqu32, 2, 0xF37F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovdqu32, 2, 0xF36F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovdqu32, 2, 0xF36F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovdqu32, 2, 0xF36F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=2|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
vmovdqu32, 2, 0xF36F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=3|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM }
vmovdqu32, 2, 0xF37F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vmovdqu32, 2, 0xF37F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vmovshdup, 2, 0xF316, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovshdup, 2, 0xF316, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovsldup, 2, 0xF312, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovsldup, 2, 0xF312, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovdqu64, 2, 0xF36F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vmovdqu64, 2, 0xF36F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vmovdqu64, 2, 0xF36F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
vmovdqu64, 2, 0xF36F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|S|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM }
vmovdqu64, 2, 0xF37F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vmovdqu64, 2, 0xF37F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
vmovdqu64, 2, 0xF37F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vmovdqu64, 2, 0xF37F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpaddd, 3, 0x66FE, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpaddd, 3, 0x66FE, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpandd, 3, 0x66DB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpandd, 3, 0x66DB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpandnd, 3, 0x66DF, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpandnd, 3, 0x66DF, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpord, 3, 0x66EB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpord, 3, 0x66EB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vprold, 3, 0x6672, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
vprold, 3, 0x6672, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vprold, 3, 0x6672, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vprold, 3, 0x6672, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vprord, 3, 0x6672, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
vprord, 3, 0x6672, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vprord, 3, 0x6672, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vprord, 3, 0x6672, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpshufd, 3, 0x6670, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpshufd, 3, 0x6670, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpslld, 3, 0x6672, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
vpslld, 3, 0x6672, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpslld, 3, 0x6672, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vpslld, 3, 0x6672, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpsrad, 3, 0x6672, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
vpsrad, 3, 0x6672, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpsrad, 3, 0x6672, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vpsrad, 3, 0x6672, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpsrld, 3, 0x6672, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
vpsrld, 3, 0x6672, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpsrld, 3, 0x6672, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vpsrld, 3, 0x6672, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpsubd, 3, 0x66FA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsubd, 3, 0x66FA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpunpckhdq, 3, 0x666A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpunpckhdq, 3, 0x666A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpunpckldq, 3, 0x6662, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpunpckldq, 3, 0x6662, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpxord, 3, 0x66EF, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpxord, 3, 0x66EF, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpaddq, 3, 0x66D4, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpaddq, 3, 0x66D4, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpandnq, 3, 0x66DF, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpandnq, 3, 0x66DF, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpandq, 3, 0x66DB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpandq, 3, 0x66DB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpmuludq, 3, 0x66F4, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpmuludq, 3, 0x66F4, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vporq, 3, 0x66EB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vporq, 3, 0x66EB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vprolq, 3, 0x6672, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
vprolq, 3, 0x6672, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vprolq, 3, 0x6672, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vprolq, 3, 0x6672, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vprorq, 3, 0x6672, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
vprorq, 3, 0x6672, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vprorq, 3, 0x6672, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vprorq, 3, 0x6672, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpsllq, 3, 0x6673, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
vpsllq, 3, 0x6673, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpsllq, 3, 0x6673, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vpsllq, 3, 0x6673, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpsraq, 3, 0x6672, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
vpsraq, 3, 0x6672, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpsraq, 3, 0x6672, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vpsraq, 3, 0x6672, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpsrlq, 3, 0x6673, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
vpsrlq, 3, 0x6673, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpsrlq, 3, 0x6673, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
vpsrlq, 3, 0x6673, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpsubq, 3, 0x66FB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpsubq, 3, 0x66FB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpunpckhqdq, 3, 0x666D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpunpckhqdq, 3, 0x666D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpunpcklqdq, 3, 0x666C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpunpcklqdq, 3, 0x666C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpxorq, 3, 0x66EF, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vpxorq, 3, 0x66EF, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vshufpd, 4, 0x66C6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vshufpd, 4, 0x66C6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vunpckhpd, 3, 0x6615, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vunpckhpd, 3, 0x6615, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vunpcklpd, 3, 0x6614, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vunpcklpd, 3, 0x6614, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vpcmpeqd, 3, 0x6676, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpeqd, 3, 0x6676, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegMask }
vpcmpeqd, 3, 0x6676, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpeqd, 3, 0x6676, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM, RegMask }
vpcmpd, 4, 0x661F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpd, 4, 0x661F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpeqd, 3, 0x661F, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpeqd, 3, 0x661F, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM, RegXMM, RegMask }
vpcmpeqd, 3, 0x661F, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpeqd, 3, 0x661F, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM, RegYMM, RegMask }
vpcmpequd, 3, 0x661E, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpequd, 3, 0x661E, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpled, 3, 0x661F, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpled, 3, 0x661F, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpleud, 3, 0x661E, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpleud, 3, 0x661E, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpltd, 3, 0x661F, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpltd, 3, 0x661F, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpltud, 3, 0x661E, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpltud, 3, 0x661E, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpneqd, 3, 0x661F, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpneqd, 3, 0x661F, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpnequd, 3, 0x661E, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpnequd, 3, 0x661E, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpnled, 3, 0x661F, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpnled, 3, 0x661F, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpnleud, 3, 0x661E, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpnleud, 3, 0x661E, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpnltd, 3, 0x661F, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpnltd, 3, 0x661F, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpnltud, 3, 0x661E, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpnltud, 3, 0x661E, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpud, 4, 0x661E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpud, 4, 0x661E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpgtd, 3, 0x6666, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpgtd, 3, 0x6666, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpeqq, 3, 0x6629, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegMask }
vpcmpeqq, 3, 0x6629, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpeqq, 3, 0x6629, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpeqq, 3, 0x6629, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM, RegMask }
vpcmpeqq, 3, 0x661F, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpeqq, 3, 0x661F, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpeqq, 3, 0x661F, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM, RegYMM, RegMask }
vpcmpeqq, 3, 0x661F, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM, RegXMM, RegMask }
vpcmpequq, 3, 0x661E, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpequq, 3, 0x661E, 0, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpleq, 3, 0x661F, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpleq, 3, 0x661F, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpleuq, 3, 0x661E, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpleuq, 3, 0x661E, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpltq, 3, 0x661F, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpltq, 3, 0x661F, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpltuq, 3, 0x661E, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpltuq, 3, 0x661E, 1, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpneqq, 3, 0x661F, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpneqq, 3, 0x661F, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpnequq, 3, 0x661E, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpnequq, 3, 0x661E, 4, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpnleq, 3, 0x661F, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpnleq, 3, 0x661F, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpnleuq, 3, 0x661E, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpnleuq, 3, 0x661E, 6, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpnltq, 3, 0x661F, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpnltq, 3, 0x661F, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpnltuq, 3, 0x661E, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpnltuq, 3, 0x661E, 5, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpq, 4, 0x661F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpq, 4, 0x661F, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpuq, 4, 0x661E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpuq, 4, 0x661E, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpcmpgtq, 3, 0x6637, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vpcmpgtq, 3, 0x6637, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vptestmq, 3, 0x6627, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vptestmq, 3, 0x6627, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vpmovdb, 2, 0xF331, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovdb, 2, 0xF331, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovsdb, 2, 0xF321, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovsdb, 2, 0xF321, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovusdb, 2, 0xF311, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovusdb, 2, 0xF311, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovdb, 2, 0xF331, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovdb, 2, 0xF331, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsdb, 2, 0xF321, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsdb, 2, 0xF321, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovusdb, 2, 0xF311, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovusdb, 2, 0xF311, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovdw, 2, 0xF333, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovdw, 2, 0xF333, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovsdw, 2, 0xF323, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovsdw, 2, 0xF323, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovusdw, 2, 0xF313, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovusdw, 2, 0xF313, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovdw, 2, 0xF333, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovdw, 2, 0xF333, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsdw, 2, 0xF323, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsdw, 2, 0xF323, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovusdw, 2, 0xF313, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovusdw, 2, 0xF313, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovqb, 2, 0xF332, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovqb, 2, 0xF332, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsqb, 2, 0xF322, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsqb, 2, 0xF322, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovusqb, 2, 0xF312, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovusqb, 2, 0xF312, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovqb, 2, 0xF332, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovqb, 2, 0xF332, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovsqb, 2, 0xF322, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovsqb, 2, 0xF322, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovusqb, 2, 0xF312, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovusqb, 2, 0xF312, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovqd, 2, 0xF335, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovqd, 2, 0xF335, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovsqd, 2, 0xF325, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovsqd, 2, 0xF325, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovusqd, 2, 0xF315, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovusqd, 2, 0xF315, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovqd, 2, 0xF335, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovqd, 2, 0xF335, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsqd, 2, 0xF325, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsqd, 2, 0xF325, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovusqd, 2, 0xF315, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovusqd, 2, 0xF315, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovqw, 2, 0xF334, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovqw, 2, 0xF334, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovsqw, 2, 0xF324, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovsqw, 2, 0xF324, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovusqw, 2, 0xF314, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
vpmovusqw, 2, 0xF314, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
vpmovqw, 2, 0xF334, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovqw, 2, 0xF334, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsqw, 2, 0xF324, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsqw, 2, 0xF324, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovusqw, 2, 0xF314, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovusqw, 2, 0xF314, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
vpmovsxbd, 2, 0x6621, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpmovsxbd, 2, 0x6621, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpmovzxbd, 2, 0x6631, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpmovzxbd, 2, 0x6631, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpmovsxbq, 2, 0x6622, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VecESize=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpmovsxbq, 2, 0x6622, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VecESize=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpmovzxbq, 2, 0x6632, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VecESize=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpmovzxbq, 2, 0x6632, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VecESize=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpmovsxdq, 2, 0x6625, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpmovsxdq, 2, 0x6625, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpmovzxdq, 2, 0x6635, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpmovzxdq, 2, 0x6635, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpmovsxwd, 2, 0x6623, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpmovsxwd, 2, 0x6623, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpmovzxwd, 2, 0x6633, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpmovzxwd, 2, 0x6633, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpmovsxwq, 2, 0x6624, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VecESize=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpmovsxwq, 2, 0x6624, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vpmovzxwq, 2, 0x6634, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VecESize=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
vpmovzxwq, 2, 0x6634, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
vptestmd, 3, 0x6627, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vptestmd, 3, 0x6627, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vptestnmd, 3, 0xF327, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vptestnmd, 3, 0xF327, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vptestnmq, 3, 0xF327, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
vptestnmq, 3, 0xF327, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
vshufps, 4, 0xC6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vshufps, 4, 0xC6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vunpckhps, 3, 0x15, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vunpckhps, 3, 0x15, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
vunpcklps, 3, 0x14, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
vunpcklps, 3, 0x14, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
// AVX512VL instructions end.

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opcodes/i386-tbl.h
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