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Fix an issue with "Rearrange MIPS INSN* masks" patch.

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This fixes an issue with Mark Shinwell's "Rearrange MIPS INSN* masks" patch
(https://sourceware.org/ml/binutils/2007-11/msg00231.html).  In the patch
the pref instruction had its membership flags changed from I4|I32|G3 to
I4_32|G3.  Unfortunately G3 was defined as being I4, which made the actual
expanded flags as: I4|I32|I4 and therefore the membership flags should have
been I4_32.  Since the patch was committed G3 was redefined to be I4|EE.  This
fix just removes I4 from G3 making the expanded membership flags for pref as
I4_32|EE.

ChangeLog:

opcodes/
	* mips-opc.c (G3): Remove I4.
This commit is contained in:
Andrew Bennett 2014-05-06 15:43:13 +01:00
parent 5e45f04cf3
commit f7730599d8
2 changed files with 5 additions and 3 deletions
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4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
* mips-opc.c (G3): Remove I4.
2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/16893

4
opcodes/mips-opc.c
View file

@ -296,9 +296,7 @@ decode_mips_operand (const char *p)
#define G2 (T3 \
)
#define G3 (I4 \
|EE \
)
#define G3 EE
/* 64 bit CPU with 32 bit FPU (single float). */
#define SF EE