darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
20499 commits 1 branch 0 tags 272 MiB
Commit graph

149 commits

Author SHA1 Message Date
Andrew Cagney
232156dee9 o Add SIM_SIGFPE to sim-signals 
o Start SIM_SIG* at 64 so that the use of host signal numbers can be
  detected and reported.
o Update MIPS simulator to use sim-signal.
 1997-11-20 09:50:36 +00:00
Andrew Cagney
a09a30d298 Allow reads/writes to C0_CONFIG register. 1997-11-20 09:17:06 +00:00
Doug Evans
486740ce01 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). 1997-11-18 23:40:40 +00:00
Andrew Cagney
f23e93dab0 * mips.igen: Tag vr5000 instructions. 
(ANDI): Was missing mipsIV model, fix assembler syntax.
        (do_c_cond_fmt): New function.
        (C.cond.fmt): Handle mips I-III which do not support CC field
        separatly.
        (bc1): Handle mips IV which do not have a delaed FCC separatly.
        (SDR): Mask paddr when BigEndianMem, not the converse as specified
        in IV3.2 spec.
        (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
        vr5000 which saves LO in a GPR separatly.
        * configure.in (enable-sim-igen): For vr5000, select vr5000
        specific instructions.
        * configure: Re-generate.
 1997-11-14 08:27:38 +00:00
Andrew Cagney
a94c5493a7 Make the signess of compares between GPR's explicit using a cast to 
signed_word.
 1997-11-11 12:31:24 +00:00
Andrew Cagney
030843d7f8 Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, 
SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI,
MFHI instructions.
Trace nullified instruction.
 1997-11-11 07:50:13 +00:00
Andrew Cagney
95469cebdd Replace global IPC with function argument cia or current instruction 
address.
Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
 1997-11-06 14:24:57 +00:00
Andrew Cagney
7ce8b9178c IGEN likes to cache the current instruction address (CIA). Change the 
MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
 1997-11-06 09:16:16 +00:00
Andrew Cagney
44b8585a3d Add option --enable-sim-igen to mips configuration. Allows user to 
attempt a build of an older MIPS simulator using igen.
 1997-11-05 09:43:34 +00:00
Andrew Cagney
63be8febf7 Rewrite the MIPS simulator's memory model so that it uses the generic 
common/sim-core.

Add support for 3, 5, 6, 7 byte transfers to sim core.
 1997-11-05 08:17:26 +00:00
Andrew Cagney
22de994d0e Delete -l and -n options, didn't do anything. 
Rename option trace to dinero-trace & dinero-file - -t clashed with
common options.
Enable common trace options.
 1997-11-05 01:08:12 +00:00
Andrew Cagney
525d929e49 Rewrite sim_monitor (implements read, write, open, et.al. system 
calls) and sim_open so that they uses the virtual memory data transfer
functions sim_read & sim_write.  This eliminates all code (other than
in load_memory & store_memory) that makes assumptions about the
implementation of the underlying memory model.
 1997-11-05 00:08:14 +00:00
Gavin Romig-Koch
0425cfb3af Correct r5900 sanitization. 1997-11-04 05:50:22 +00:00
Gavin Romig-Koch
6205f37913 * gencode.c: Add tx49 configury and insns. 
* configure.in: Add tx49 configury.
	* configure: Update.
 1997-10-29 19:42:49 +00:00
Andrew Cagney
01b9cd49ca common/sim-bits.h: Document ROTn macro. 
igen/{igen.c,ld-insns.h}: Document mnemonic string formats.
mips/Makefile.in: Add dependencies for files included by mips.igen
mips/vr5400.igen: checkpoint vr5400 instructions.
 1997-10-29 04:02:30 +00:00
Andrew Cagney
89d0973831 Add support for 16 byte quantities to sim-endian macro H2T. 
Add model-filter field to option, include, model anf function igen records
 1997-10-28 07:10:36 +00:00
Andrew Cagney
16bd5d6e52 Separate r5900 specifoc and mips16 instructions. 
Add support for this to configure (vr5400 target only)
 1997-10-27 07:55:24 +00:00
Andrew Cagney
90ad43b2de Add mips64vr5400 to configuration list 
Mark mipsIV instructions as being implemented by the vr5400.
Sanitize.
 1997-10-27 06:42:13 +00:00
Gavin Romig-Koch
635ae9cb7c * sim/mips/gencode.c (build_instruction): Follow sim_write's lead in using 
BigEndianMem instead of !ByteSwapMem.
 1997-10-25 20:53:46 +00:00
Andrew Cagney
122edc03de Add basic igen configuration to autoconf. Disable. 1997-10-24 07:54:21 +00:00
Andrew Cagney
dad6f1f326 Add function to fetch 32bit instructions 
When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
 1997-10-24 06:43:51 +00:00
Andrew Cagney
49a7683337 Checkpoint IGEN version of mips sim 1997-10-24 06:38:44 +00:00
Andrew Cagney
92ad193bb0 Use SIM*_OVERFLOW_RESULT defined in sim-alu.h 1997-10-21 07:57:33 +00:00
Andrew Cagney
aa324b9b1e Output pc profile statistics once gathered. 1997-10-21 07:40:00 +00:00
Andrew Cagney
e2f8ffb736 Delete profile support from MIPS simulator, use sim/common/sim-profile 
module instead.
Generate a "gmon.out" (gprof) when profiling the target PC.
Add target PC profiling option --profile-pc-granularity (bucket size)
 1997-10-21 03:41:21 +00:00
Andrew Cagney
fb5a2a3e39 Make mips registers of type unsigned_word. 
Ensure all references to MIPS registers use same type.
 1997-10-20 06:28:53 +00:00
Andrew Cagney
ea985d2472 Move register definitions and macros out of interp.c and into sim-main.h 1997-10-16 03:50:48 +00:00
Andrew Cagney
085c1cb988 Checkpoint IGEN version of MIPS simulator. 1997-10-16 03:41:57 +00:00
Andrew Cagney
284e759d1f Rename generated file engine.c to oengine.c. 1997-10-16 03:39:13 +00:00
Andrew Cagney
339fb14904 * gencode.c (build_instruction): Use FPR_STATE not fpr_state. 1997-10-16 03:29:47 +00:00
Andrew Cagney
8b70f83790 * gencode.c (build_instruction): For "FPSQRT", output correct number 
of arguments to Recip.
 1997-10-16 03:23:16 +00:00
Andrew Cagney
055ee2977f Checkpoint IGEN version of MIPS simulator. 1997-10-14 09:34:08 +00:00
Andrew Cagney
0c2c5f6141 Move global MIPS simulator variables into sim_cpu struct. 1997-10-14 09:26:03 +00:00
Andrew Cagney
18c64df613 o Add support for configuring wordsize, fp hardware and target 
endianness.  Provide defaults for some tier-1 mips targets.
o	Parameterize all functions with SIM_DESC.
 1997-10-14 07:27:31 +00:00
Andrew Cagney
49a6eed58a Snap. Gets through igen's checks. 1997-10-09 08:38:22 +00:00
Andrew Cagney
f2b3001251 MIPS/IGEN checkpoint - doesn't build. 1997-10-08 04:16:01 +00:00
Andrew Cagney
391c71708e Checkpoint IGEN input file for MIPS simulator. 1997-10-07 08:45:11 +00:00
Andrew Cagney
adf4739efe Add access to hi part of r5900 128 bit registers. 1997-09-30 03:45:51 +00:00
Bob Manson
26b20b0a0e * configure: Regenerated. 
Can't hack one without the other...
 1997-09-29 21:46:32 +00:00
Mark Alexander
6eedf3f4e5 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. 1997-09-26 20:56:55 +00:00
Andrew Cagney
af51b8d56d Add/use SIM_AC_OPTION_BITSIZE. 1997-09-25 07:19:05 +00:00
Andrew Cagney
e63bc706fe Allow gencode.c to generate input to the igen generator. 1997-09-25 04:23:24 +00:00
Andrew Cagney
eb2e3c85ca Pacify GCC -Wall 1997-09-25 04:13:50 +00:00
Jeff Law
832f05e865 vr5900-r5900. 1997-09-23 16:21:23 +00:00
Andrew Cagney
92f91d1ff0 Remove need to update <targ>/Makefile.in when adding optional options 
to <targ>/configure.in.
Simplify logic used to select target [default] endianness.
 1997-09-23 01:25:26 +00:00
Andrew Cagney
76a6247f07 Add memory alignment config option. 1997-09-22 09:40:57 +00:00
Andrew Cagney
794e9ac96a Simplify logic behind the generic configuration option --enable-sim-alignment. 1997-09-22 02:49:57 +00:00
Andrew Cagney
b45caf050c Add support for --enable-sim-alignment to simulator common aclocal.m4 
Add support for --alignment={strict,nonstrict,forced} to simulator common
run-time options.
For v850 use, make the default NONSTRICT_ALIGNMENT.
 1997-09-22 00:24:46 +00:00
Gavin Romig-Koch
c476ac5560 Add handling for 3900's SDBBP, DERET, and RFE insns. 
* gencode.c (SDBBP,DERET): Added (3900) insns.
	(RFE): Turn on for 3900.
	* interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
	(dsstate): Made global.
	(SUBTARGET_R3900): Added.
	(CANCELDELAYSLOT): New.
	(SignalException): Ignore SystemCall rather than ignore and
	terminate.  Add DebugBreakPoint handling.
	(decode_coproc): New insns RFE, DERET; and new registers Debug
	and DEPC protected by SUBTARGET_R3900.
	(sim_engine_run): Use CANCELDELAYSLOT rather than clearing
	bits explicitly.
	* Makefile.in,configure.in: Add mips subtarget option.
	* configure: Update.
 1997-09-20 18:22:22 +00:00
Gavin Romig-Koch
7afa8d4edc * gencode.c: Add r3900 (tx39). 
* gencode.c: Fix some configuration problems by improving
	the relationship between tx19 and tx39.
 1997-09-19 13:39:55 +00:00