* config/m68k-parse.h (m68k_register): Use MBO instead of MBB.
(last_movec_reg): Change to MBO.
* config/tc-m68k.c (fido_ctrl): Use MBO instead of MBB.
(m68k_ip): Use MBO instead of MBO.
(init_table): Use MBO instead of MBO. Add an entry for mbo.
gas/testsuite/
* gas/m68k/fido.s: Add tests for %mbo.
* gas/m68k/fido.d: Update accordingly.
opcodes/
* m68k-dis.c (print_insn_arg): Use %mbo instead of %mbb.
2007-09-24 Carlos O'Donell <carlos@codesourcery.com>
* config/tc-mips.c (s_align): Set max_alignment to 28.
gas/testsuite/
2007-09-24 Carlos O'Donell <carlos@codesourcery.com>
* gas/mips/align.s, gas/mips/align.d: New test.
* gas/mips/mips.exp: Run it.
2007-09-17 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (intel_e04): Revert the last change.
gas/testsuite/
2007-09-17 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/x86-64-rip.s: Revert the last change.
* gas/i386/x86-64-rip-intel.d: Likewise.
* gas/i386/x86-64-rip.d: Likewise.
2007-08-28 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Handle cmpxchg8b in
Intel mode.
gas/testsuite/
2007-08-28 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/mem.s: New. Add tests for instructions with one
memory operand.
* gas/i386/x86-64-mem.s: Likewise.
* gas/i386/mem-intel.d: Updated.
* gas/i386/mem.d: Likewise.
* gas/i386/x86-64-mem-intel.d: Likewise.
* gas/i386/x86-64-mem.d: Likewise.
opcodes/
2007-08-28 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (Md): New.
(grps): Use 0 on invlpg. Use M on fxsave and fxrstor. Use
Md on ldmxcsr and stmxcsr. Use b_mode on clflush.
(OP_0fae): Clear bytemode for sfence.
* config/tc-i386.c (x86_cons): Complain about invalid @got etc.
expressions.
(i386_immediate): Detect and complain about more cases of
invalid immediate expressions. Return failure rather than
converting them to zero.
(i386_displacement): Likewise.
Check the return value of insert_reg_alias and do not continue to create aliases once an insertion has failed.
(s_unreq): Delete the all-upper-case and all-lower-case alternatives as well.
* testsuite/gas/arm/arm.s: Add tests for re-aliasing a previously removed alias.
* testsuite/gas/arm/arm.l: Add new expected warning message.
* config/tc-mips.c (mips_cpu_info_table): Add new entries for
{24k,24ke,34k,74k}f{2_1,1_1,x}. Also add an entry for 74kf3_2.
Deprecate *x and *fx.
* doc/c-mips.texi: Document the new CPU arguments. Deprecate
*x and *fx.
2007-07-04 H.J. Lu <hongjiu.lu@intel.com>
* config/obj-coff.h (x86_64_target_format): Renamed to ...
(i386_target_format): This
(TARGET_FORMAT): Use i386_target_format.
* config/tc-i386.c (x86_64_target_format): Removed.
(i386_target_format): Handle PE formats.
gas/testsuite/
2007-07-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run x86-64-nops-1 for x86_64-*-mingw*.
* elfxx-mips.c (mips_elf_calculate_relocation): Allow local stubs
to be used for calls from MIPS16 code.
gas/
* config/tc-mips.h (TC_SYMFIELD_TYPE): New.
* config/tc-mips.c (append_insn): Record which symbols have
R_MIPS16_26 relocations against them.
(mips_fix_adjustable): Don't reduce relocations against such symbols.
ld/testsuite/
* ld-mips-elf/mips16-local-stubs-1.s,
* ld-mips-elf/mips16-local-stubs-1.d: New tests.
* ld-mips-elf/mips-elf.exp: Run them.
use of literal_frag field.
* config/tc-xtensa.c (xtensa_mark_literal_pool_location): Record frag
in the literal_frag field.
(xtensa_move_literals): Use it here instead of searching. Update
literal_frag field with new value.
* elf32-xtensa.c (extend_ebb_bounds_forward): Use renamed
XTENSA_PROP_NO_TRANSFORM flag instead of XTENSA_PROP_INSN_NO_TRANSFORM.
(extend_ebb_bounds_backward, compute_text_actions): Likewise.
(compute_ebb_proposed_actions, coalesce_shared_literal): Likewise.
(xtensa_get_property_predef_flags): Likewise.
(compute_removed_literals): Pass new arguments to is_removable_literal.
(is_removable_literal): Add sec, prop_table and ptblsize arguments.
Do not remove literal if the NO_TRANSFORM property flag is set.
gas/
* config/tc-xtensa.c (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to...
(XTENSA_PROP_NO_TRANSFORM): ...this.
(frag_flags_struct): Move is_no_transform out of the insn sub-struct.
(xtensa_mark_frags_for_org): New.
(xtensa_handle_align): Set RELAX_ORG frag subtype for rs_org.
(xtensa_post_relax_hook): Call xtensa_mark_frags_for_org.
(get_frag_property_flags): Adjust reference to is_no_transform flag.
(xtensa_frag_flags_combinable): Likewise.
(frag_flags_to_number): Likewise. Use XTENSA_PROP_NO_TRANSFORM.
* config/tc-xtensa.h (xtensa_relax_statesE): Add RELAX_ORG.
include/elf/
* xtensa.h (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to...
(XTENSA_PROP_NO_TRANSFORM): ...this.
ld/
* emultempl/xtensaelf.em (replace_insn_sec_with_prop_sec): Use renamed
XTENSA_PROP_NO_TRANSFORM flag instead of XTENSA_PROP_INSN_NO_TRANSFORM.
number@ppu.
(tc_gen_reloc): Abort if neither addsy or subsy is set.
(md_apply_fix): Don't attempt to resolve SPU_PPU relocs.
* config/tc-spu.h (md_operand): Handle @ppu without sym.
top 32 bits of 64 bit value if so doing results in passing
range check. Rewrite sign extension fudges similarly. Enable
fudges for powerpc64 too. Report user value if range check
fails rather than fudged value. Negate PPC_OPERAND_NEGATIVE
range rather than value, also to report user value on failure.
* config/tc-m68k.c (relaxable_symbol): Make sure that the correct addend is stored for relocs against weak symbols.
(md_apply_fix): So not loose track of addend for relocs against weak symbols.
* testsuite/gas/m68k/p3041.s: New test case.
* testsuite/gas/m68k/p3041.d: New expected disassembly.
* testsuite/gas/m68k/all.exp: Run new test for m68k-*-netbsd toolchains.
Only run arch-cpu-1 test for ELF based toolchains.
Tidy ups for m68k-netbsd gas toolchain:
* testsuite/gas/m68k/cpu32.d: Allow for extra text after expected disassembly.
* testsuite/gas/m68k/mcf-trap.d: Allow for alternative trap mnemonics.
* testsuite/gas/m68k/br-isab.d: Fix name of test.
* testsuite/gas/m68k/br-isac.d: Fix name of test.
* config/tc-score.c (data_op2, validate_immediate): Fix bug for addri, addri.c, subi, and
subi.c when immediate number is hex.
(score_insns): Remove subis and subis.c.
(do_sub_rdi16): Delete.
* spu.h (R_SPU_PPU32, R_SPU_PPU64): Define.
bfd/
* reloc.c (BFD_RELOC_SPU_PPU32, BFD_RELOC_SPU_PPU64): Define.
* elf-bfd.h (struct elf_backend_data): Change return type of
elf_backend_relocate_section to int.
* elf32-spu.c (elf_howto_table): Add howtos for R_SPU_PPU32 and
R_SPU_PPU64.
(spu_elf_bfd_to_reloc_type): Convert new relocs.
(spu_elf_count_relocs): New function.
(elf_backend_count_relocs): Define.
(spu_elf_relocate_section): Arrange to emit R_SPU_PPU32 and
R_SPU_PPU64 relocs.
* elflink.c (elf_link_input_bfd): Emit relocs if relocate_section
returns 2.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-spu.c (md_pseudo_table): Add int, long, quad. Call
spu_cons for word.
(md_assemble): Tidy use of insn.flag.
(get_imm): Likewise. Handle uppercase input too.
(spu_cons): New function.
* config/tc-spu.h (tc_fix_adjustable): Don't adjust SPU_PPU relocs.
(TC_FORCE_RELOCATION): Don't resolve them either.
binutils/
* embedspu.sh (find_prog): Prefer prog in same dir as embedspu
over one found on the users path.
(main): Generate .reloc for each R_SPU_PPU* reloc.
* gas/config/tc-m68k.c (relaxable_symbol): Do not relax weak symbols.
(tc_gen_reloc): Adjust the addend of relocs against weak symbols.
(md_apply_fix): Put zero values into the frags referencing weak symbols.
* bfd/aoutx.h (swap_std_reloc_out): Treat relocs against weak symbols in the same way as relocs against external symbols.
2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Check suffix for crc32 in
Intel mdoe.
(process_suffix): Default the suffix of 8bit crc32 to
BYTE_MNEM_SUFFIX.
(check_byte_reg): Skip check for 8bit crc32.
gas/testsuite/
2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/crc32-intel.d: New file.
* gas/i386/crc32.d:Likewise.
* gas/i386/crc32.s:Likewise.
* gas/i386/x86-64-crc32-intel.d:Likewise.
* gas/i386/x86-64-crc32.d:Likewise.
* gas/i386/x86-64-crc32.s:Likewise.
* gas/i386/i386.exp: Run crc32, crc32-intel, x86-64-crc32
and x86-64-crc32-intel.
opcodes/
2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (CRC32_Fixup): Properly handle Intel mode and
check data size prefix in 16bit mode.
* i386-opc.c (i386_optab): Default crc32 to non-8bit and
support Intel mode.
PR 4436
* ppc-opc.c (powerpc_operands): Correct bitm for second entry of MBE.
gas/
PR 4436
* config/tc-ppc.c (ppc_insert_operand): Disable range check if
min > max.
gas/testsuite/
* gas/arm/thumb1_unified.d: New test.
* gas/arm/thumb1_unified.s: New test.
gas/
* config/tc-arm.c (md_assemble): Only allow 16-bit instructions on
Thumb-1. Add sanity check for bogus relaxations.
* config/tc-vax.c (vax_cons): Added to support %pcrel{8,16,32}(exp)
to emit pcrel relocations by DWARF2 in non-code sections. Borrowed
heavily from tc-sparc.c. (vax_cons_fix_new): Likewise.
* doc/as.texinfo: Add -mvxworks-pic to the list of MIPS options.
* doc/c-mips.texi (-KPIC, -mvxworks-pic): Document.
* config/tc-mips.c (md_show_usage): Mention -mvxworks-pic.
Do not check is_loop_target flag.
(xtensa_frob_label): Adjust calls to xtensa_move_labels.
(xg_assemble_vliw_tokens): Likewise. Also avoid calling
xtensa_move_labels for alignment of loop opcodes.
gas/
* config/tc-arm.c (encode_thumb2_ldmstm): New function.
(do_t_ldmstm): Generate 16-bit push/pop. Use encode_thumb2_ldmstm.
(do_t_push_pop): Use encode_thumb2_ldmstm.
gas/testsuite/
* gas/arm/thumb2_ldmstm.d: New test.
* gas/arm/thumb2_ldmstm.s: New test.
2007-03-28 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_modrm_byte): For instructions with 2
register operands, encode destination in i.rm.regmem if its
RegMem bit is set.
opcodes/
2007-03-28 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.c (i386_optab): Change InvMem to RegMem for mov and
movq. Remove InvMem from sldt, smsw and str.
* i386-opc.h (InvMem): Renamed to ...
(RegMem): Update comments.
(AnyMem): Remove InvMem.
(parse_qfloat_immediate): Disallow integer syntax for floating-point
immediates. Fix hex immediates, handle 0.0 and -0.0 specially.
(parse_neon_mov): Set immisfloat bit for operand if it parsed as a
float.
(neon_cmode_for_move_imm): Reject non-float immediates for float
operands.
(neon_move_immediate): Pass immisfloat bit to neon_cmode_for_move_imm.
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_begin): Use i386_regtab_size to scan
i386_regtab.
(parse_register): Use i386_regtab_size instead of ARRAY_SIZE
on i386_regtab.
opcodes/
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.c: Include "libiberty.h".
(i386_regtab): Remove the last entry.
(i386_regtab_size): New.
(i386_float_regtab_size): Likewise.
* i386-opc.h (i386_regtab_size): New.
(i386_float_regtab_size): Likewise.
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
* config/tc-m68k.c (mcfv4e_ctrl): Add ColdFire specific names.
(mcf5475_ctrl, mcf5485_ctrl): New.
(m68k_cpus): Use mcf5485_ctrl and mcf5485_ctrl for those families.
(m68k_ip): Add ASID, MMUBAR, ROMBAR0 handling.
(init_table): Add asid, mmubar, adjust rombar0.
* config/tc-i386.h (Seg2ShortForm, Seg3ShortForm): Delete.
* config/tc-i386.c: Wrap overly long lines, whitespace fixes.
(process_operands): Move old Seg2ShortForm and Seg3ShortForm
code, and test for these insns using a combination of
opcode_modifier and operand_types.
include/opcode/
* i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
and Seg3ShortFrom with Shortform.
(xtensa_elf_suffix): Use suffix_relocs instead of local mapping table.
(map_suffix_reloc_to_operator): New.
(map_operator_to_reloc): New.
(expression_maybe_register): Fix incorrect test of return value from
xtensa_elf_suffix. Rearrange to use map_suffix_reloc_to_operator.
(xg_assemble_literal, convert_frag_immed): Use map_operator_to_reloc.
gas/
* config/tc-arm.c (do_t_add_sub): Use Rd and Rs.
gas/testsuite/
* gas/arm/thumb2_add.d: Add test for missing operand.
* gas/arm/thumb2_add.s: Ditto.
* archures.c (bfd_mach_cpu32_fido): Rename to bfd_mach_fido.
* bfd-in2.h: Regenerate.
* cpu-m68k.c (arch_info_struct): Use bfd_mach_fido instead of
bfd_mach_cpu32_fido.
(m68k_arch_features): Use fido_a instead of cpu32.
(bfd_m68k_compatible): Reject the combination of Fido and
ColdFire. Accept the combination of CPU32 and Fido with a
warning.
* elf32-m68k.c (elf32_m68k_object_p,
elf32_m68k_merge_private_bfd_data,
elf32_m68k_print_private_bfd_data): Treat Fido as an
architecture by itself.
binutils/
* readelf.c (get_machine_flags): Treat Fido as an architecture
by itself.
gas/
* config/tc-m68k.c (m68k_archs, m68k_cpus): Treat Fido as an
architecture by itself.
(m68k_ip): Don't issue a warning for tbl instructions on fido.
(m68k_elf_final_processing): Treat Fido as an architecture by
itself.
include/elf/
* m68k.h (EF_M68K_FIDO): New.
(EF_M68K_ARCH_MASK): OR EF_M68K_FIDO.
(EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): Remove.
include/opcode/
* m68k.h (m68010up): OR fido_a.
opcodes/
* m68k-opc.c (m68k_opcodes): Replace cpu32 with
cpu32 | fido_a except on tbl instructions.
PR gas/3826
* config/tc-i386.c (register_prefix): New.
(set_intel_syntax): Set set_intel_syntax to "" if register
prefix is needed.
(check_byte_reg): Use register_prefix for error message.
(check_long_reg): Likewise.
(check_qword_reg): Likewise.
(check_word_reg): Likewise.
(do_neon_qshl_imm): Likewise.
(do_neon_rshl): New function. Handle rounding variants of
v{q}shl-by-register.
(insns): Use do_neon_rshl for vrshl, vqrshl.
* config/tc-i386.c (process_operands): Check i.reg_operands
and increment i.operands when adding a register operand.
(build_modrm_byte): Fix 4 operand instruction handling.
* config/tc-i386.c (disp_expressions): Use MAX_MEMORY_OPERANDS
for array size instead of 2.
(im_expressions): Use MAX_IMMEDIATE_OPERANDS for for array size
instead of 2.
(i386_immediate): Update immediate operand overflow error
message.
(i386_displacement): Check displacement operand overflow.
* config/m68k-parse.h (m68k_register): Add CAC and MBB.
* config/tc-m68k.c (fido_ctrl): New.
(m68k_archs): Use fido_ctrl for -mfidoa.
(m68k_cpus): Use fido_ctrl on fido-*-*.
(m68k_ip): Add support for CAC and MBB.
(init_table): Add CAC and MBB.
opcodes/
* m68k-dis.c (print_insn_arg): Add support for cac and mbb.
Delete the code handling large constant for PIC.
Modify some comments.
(score_relax_frag): Decrease insn_addr in certain situation.
(s_score_cprestore): Change .cprestore syntax from ".cprestore offset"
to ".cprestore reg, offset".
2006-12-13 H.J. Lu <hongjiu.lu@intel.com>
PR gas/3712
* config/tc-i386.c (match_template): Use MAX_OPERANDS for the
number of operands. Issue an error if MAX_OPERANDS != 4. Add
the 4th operand check.
gas/testsuite/
2006-12-13 H.J. Lu <hongjiu.lu@intel.com>
PR gas/3712
* gas/i386/inval.s: Add invalid insertq.
* gas/i386/x86-64-inval.s: Likewise.
* gas/i386/inval.l: Updated.
* gas/i386/x86-64-inval.l: Likewise.
Return NULL if symbol name characters follow the register number.
(parse_reg): Use NULL instead of 0 for pointer values. Stop
processing if whatreg returned NULL.
gas/
* config/tc-arm.c (arm_force_relocation): Return 1 for relocs against
function symbols.
gas/testsuite/
* gas/arm/thumbrel.s: New test.
* gas/arm/thumbrel.d: New test.
gas/
* config/tc-arm.c (arm_is_eabi): New function.
* config/tc-arm.h (arm_is_eabi): New prototype.
(THUMB_IS_FUNC): Use ELF function type for EABI objects.
* doc/c-arm.texi (.thumb_func): Update documentation.
* elf32-xtensa.c (elf_xtensa_special_sections): Add .xtensa.info.
gas/
* config/tc-xtensa.c (XSHAL_ABI): Add default definition.
(directive_state): Disable scheduling by default.
(xtensa_add_config_info): New.
(xtensa_end): Call xtensa_add_config_info.
gas/testsuite/
* gas/elf/section2.e-xtensa: New file.
* gas/elf/elf.exp: Use it.
include/
* xtensa-config.h (XSHAL_ABI): New.
(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New.
ld/
* emultempl/xtensaelf.em (XSHAL_ABI): Add default definition.
(replace_insn_sec_with_prop_sec): Use bfd_make_section_with_flags.
Delete redundant code to set sections flags and alignment.
(xt_config_info_unpack_and_check, check_xtensa_info): New.
(elf_xtensa_after_open): Iterate over input statements instead of
link_info.input_bfds.
(elf_xtensa_before_allocation): Likewise. Call check_xtensa_info for
each input, and write a new .xtensa.info section in the output.
* arm-dis.c (last_is_thumb): Delete.
(enum map_type, last_type): New.
(print_insn_data): New.
(get_sym_code_type): Take MAP_TYPE argument. Check the type of
the right symbol. Handle $d.
(print_insn): Check for mapping symbols even without a normal
symbol. Adjust searching. If $d is found see how much data
to print. Handle data.
gas/
* config/tc-arm.h (md_cons_align): Define.
(mapping_state): New prototype.
* config/tc-arm.c (mapping_state): Make global.
gas/testsuite/
* gas/arm/arm7t.d, gas/arm/neon-ldst-rm.d, gas/arm/thumb2_pool.d,
gas/arm/tls.d: Update for $d support.
* gas/arm/mapshort.d, gas/arm/mapshort.s: New test.
* gas/elf/section2.e-armeabi: Update.
* gas/elf/section2.e-armelf: New file.
* gas/elf/elf.exp: Use it.
ld/testsuite/
* ld-arm/mixed-app.d, ld-arm/tls-app.d, ld-arm/tls-lib.d: Update
for $d support.
* config/tc-m68k.c (m68k_ip): Correct output of cpu aliases.
gas/testsuite/
* gas/m68k/all.exp: Add mcf-trap.
* gas/m68k/mcf-trap.[sd]: New.
opcodes/
* m68k-opc.c (m68k_opcodes): Place trap instructions before set
conditionals. Add tpf coldfire instruction as alias for trapf.
(arm_fix_adjustable) [OBJ_ELF]: Use it on coff targets too.
* gas/arm/local_label_coff.s: New test.
* gas/arm/local_label_coff.d: New test.
* gas/arm/local_label_elf.s: New test.
* gas/arm/local_label_elf.d: New test.
* gas/arm/local_label_wince.s: New test.
* gas/arm/local_label_wince.d: New test.
* config/tc-mips.c (pic_need_relax): Return true for section symbols.
gas/testsuite:
* gas/mips/elf-rel26.s: New test.
* gas/mips/elf-rel26.d: Ditto.
* gas/mips/mips.exp: Run it.
(my_get_expression): Const operand of some instructions can not be symbol in assembly.
(get_insn_class_from_type): Handle instruction type Insn_internal.
(do_macro_ldst_label): Modify inst.type.
(Insn_PIC): Delete.
* score-inst.h (enum score_insn_type): Add Insn_internal.
* tc-score.c (data_op2): The immediate value in lw is 15 bit signed.
* score-dis.c (print_insn): Correct the error code to print correct PCE instruction disassembly.
* bfd/elf64-sparc.c: Add FreeBSD support.
(elf64_sparc_fbsd_post_process_headers): New function.
* bfd/targets.c (_bfd_target_vector): Add bfd_elf64_sparc_freebsd_vec.
* bfd/config.bfd (sparc64-*-freebsd*): Set targ_defvec to bfd_elf64_sparc_freebsd_vec.
* bfd/configure.in: Add entry for bfd_elf64_sparc_freebsd_vec.
* bfd/configure: Regenerate.
* gas/config/tc-sparc.c (md_parse_option): Treat any target starting with elf32-sparc
as a viable target for the -32 switch and any target starting with elf64-sparc as a
viable target for the -64 switch.
(sparc_target_format): For 64-bit ELF flavoured output use ELF_TARGET_FORMAT64
while for 32-bit ELF flavoured output use ELF_TARGET_FORMAT.
* gas/config/tc-sparc.h (ELF_TARGET_FORMAT, ELF_TARGET_FORMAT64): Define.
* ld/emulparams/elf64_sparc_fbsd.sh (OUTPUT_FORMAT): Define as elf64-sparc-freebsd.
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
gas/
* config/tc-arm.c (do_neon_dyadic_if_i): Remove.
(do_neon_dyadic_if_i_d): Avoid setting U bit.
(do_neon_mac_maybe_scalar): Ditto.
(do_neon_dyadic_narrow): Force operand type to NT_integer.
(insns): Remove out of date comments.
gas/testsuite/
* gas/arm/neon-cov.s: Test .u and .s aliases for .i suffixes.
* gas/arm/neon-cov.d: Adjust expected output.
opcodes/
* arm-dis.c (neon_opcode): Fix suffix on VMOVN.
* elf32-xtensa.c (xtensa_get_property_section_name): Delete.
(xtensa_get_property_section): New.
(xtensa_read_table_entries): Use xtensa_get_property_section.
(relax_property_section, xtensa_get_property_predef_flags): Handle
group name suffixes in property section names.
(match_section_group): New.
gas/
* config/tc-xtensa.c (FINI_LITERAL_SECTION_NAME): Delete.
(INIT_LITERAL_SECTION_NAME): Delete.
(lit_state struct): Remove segment names, init_lit_seg, and
fini_lit_seg. Add lit_prefix and current_text_seg.
(init_literal_head_h, init_literal_head): Delete.
(fini_literal_head_h, fini_literal_head): Delete.
(xtensa_begin_directive): Move argument parsing to
xtensa_literal_prefix function.
(xtensa_end_directive): Deallocate lit_prefix field of lit_state.
(xtensa_literal_prefix): Parse the directive argument here and
record it in the lit_prefix field. Remove code to derive literal
section names.
(linkonce_len): New.
(get_is_linkonce_section): Use linkonce_len. Check for any
".gnu.linkonce.*" section, not just text sections.
(md_begin): Remove initialization of deleted lit_state fields.
(xtensa_reorder_segments, xtensa_post_relax_hook): Remove references
to init_literal_head and fini_literal_head.
(xtensa_move_literals): Likewise. Skip literals for .init and .fini
when traversing literal_head list.
(match_section_group): New.
(cache_literal_section): Rewrite to determine the literal section
name on the fly, create the section and return it.
(xtensa_switch_to_literal_fragment): Adjust for cache_literal_section.
(xtensa_switch_to_non_abs_literal_fragment): Likewise.
(xtensa_create_property_segments, xtensa_create_xproperty_segments):
Use xtensa_get_property_section from bfd.
(retrieve_xtensa_section): Delete.
* doc/c-xtensa.texi (Xtensa Options): Fix --text-section-literals
description to refer to plural literal sections and add xref to
the Literal Directive section.
(Literal Directive): Describe new rules for deriving literal section
names. Add footnote for special case of .init/.fini with
--text-section-literals.
(Literal Prefix Directive): Replace old naming rules with xref to the
Literal Directive section.
ld/
* emulparams/elf32xtensa.sh (.xt.prop): Add .xt.prop.*.
* scripttempl/elfxtensa.sc (.text): Add .literal.*.
* config/tc-arm.c (s_arm_unwind_save_mmxwr): Correct condition for
merging with previous long opcode.
gas/testsuite:
* gas/arm/unwind.s: Test not merging iWMMXt register save with
previous long opcode.
* gas/arm/unwind.d, gas/arm/unwind_vxworks.d: Update.
* Makefile.am: Add rules to build pe-arm-wince.lo and pei-arm-wince.lo objects.
* Makefile.in: Regenerate.
* pe-arm-wince.c: New file.
* pei-arm-wince.c: New file.
* pei-arm.c: Remove ARM_WINCE block.
* pe-arm.c: Remove ARM_WINCE block. Rename
bfd_arm_pe_allocate_interworking_sections,
bfd_arm_pe_get_bfd_for_interworking, and
bfd_arm_pe_process_before_allocation to
bfd_armpe_allocate_interworking_sections,
bfd_armpe_get_bfd_for_interworking, and
bfd_armpe_process_before_allocation. Move them before including bfd.h.
* bfd.c: ARM wince bfd format names were renamed. Adjust.
* coff-arm.c [ARM_WINCE]: Adjust so Windows CE doesn't end up with unexpected/conflicting relocs.
* targets.c: The arm-wince-pe target got its own new vector. Adjust.
* config.bfd: Likewise.
* configure.in: Likewise.
* configure: Regenerate.
binutils
* configure.in: Split arm-pe and arm-wince-pe. Build dlltool with -DDLLTOOL_ARM_WINCE for Windows CE case.
* configure: Regenerate.
* dlltool.c: Add support for arm-wince.
gas
* Makefile.am (TARG_ENV_HFILES): Add te-wince-pe.h.
* Makefile.in: Regenerate.
* config/tc-arm.h [TARGET_FORMAT]: ARM wince bfd names were renamed. Adjust.
ld
* Makefile.am: Split arm-wince into its own emulation.
* Makefile.in: Regenerate.
* configure.tgt: Set targ_emul to arm_wince_pe for ARM Windows CE targets.
* pe-dll.c : Define PE_ARCH_arm_wince.
(pe_detail_list): Add PE_ARCH_arm_wince case.
(make_one): Handle PE_ARCH_arm_epoc and PE_ARCH_arm_wince cases.
* emulparams/arm_wince_pe.sh: New file.
* emultempl/pe.em: Handle new TARGET_IS_arm_wince_pe define.
Remap bfd_arm_allocate_interworking_sections, bfd_arm_get_bfd_for_interworking and
bfd_arm_process_before_allocation for arm-pe and arm-wince-pe targets too.
(gld_${EMULATION_NAME}_recognized_file): Handle arm-wince and arm-epoc bfd format names.
to use ARM instructions on non-ARM-supporting cores.
(autoselect_thumb_from_cpu_variant): New function. Switch on Thumb
mode automatically based on cpu variant.
(md_begin): Call above function.
* coff-arm.c (coff_arm_rtype_to_howto) [COFF_WITH_PE]: Handle ARM_SECREL.
(coff_arm_reloc_type_lookup): Map BFD_RELOC_32_SECREL to ARM_SECREL.
* pe-arm.c [COFF_SECTION_ALIGNMENT_ENTRIES]: Define.
* pei-arm.c [TARGET_UNDERSCORE]: Define for ARM_WINCE like in pe-arm.c.
[COFF_SECTION_ALIGNMENT_ENTRIES]: Define.
* config/tc-arm.c: Move "dwarf2dbg.h" inclusion out of OBJ_ELF only block.
(pe_directive_secrel) [TE_PE]: New function.
(md_pseudo_table) [!OBJ_ELF]: Handle 2byte, 4byte, 8byte, file, loc, loc_mark_labels.
[TE_PE]: Handle secrel32.
(output_relax_insn): Remove OBJ_ELF around dwarf2_emit_insn call.
(output_inst): Remove OBJ_ELF around dwarf2_emit_insn call.
(arm_frob_label): Remove OBJ_ELF around dwarf2_emit_label call.
(md_section_align): Only round section sizes here for AOUT targets.
(tc_arm_regname_to_dw2regnum): Move out for OBJ_ELF only block.
(tc_pe_dwarf2_emit_offset): New function.
(md_apply_fix) [TE_PE]: Handle BFD_RELOC_32_SECREL.
(cons_fix_new_arm): Handle O_secrel.
* config/tc-arm.h : Move DWARF2_LINE_MIN_INSN_LENGTH, DWARF2_DEFAULT_RETURN_COLUMN and DWARF2_CIE_DATA_ALIGNMENT out of OBJ_ELF only block.
[TE_PE]: Define O_secrel, TC_DWARF2_EMIT_OFFSET, and declare tc_pe_dwarf2_emit_offset.
* ld-pe/pe.exp: Enable tests on arm-wince-pe.
* ld-pe/secrel.d: Adjust test to work on arm-wince-pe too.
2006-08-02 Richard Sandiford <richard@codesourcery.com>
Kazu Hirata <kazu@codesourcery.com>
Phil Edwards <phil@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
* config.bfd (sh-*-vxworks): Use bfd_elf32_shvxworks_vec and
bfd_elf32_shlvxworks_vec.
* configure.in (bfd_elf32_sh64_vec): Add elf-vxworks.lo.
(bfd_elf32_sh64l_vec, bfd_elf32_sh64lin_vec): Likewise.
(bfd_elf32_sh64blin_vec, bfd_elf32_sh64lnbsd_vec): Likewise.
(bfd_elf32_sh64nbsd_vec, bfd_elf32_sh_vec): Likewise.
(bfd_elf32_shblin_vec, bfd_elf32_shl_vec): Likewise.
(bfd_elf32_shl_symbian_vec, bfd_elf32_shlin_vec): Likewise.
(bfd_elf32_shlnbsd_vec, bfd_elf32_shnbsd_vec): Likewise.
(bfd_elf32_shlvxworks_vec, bfd_elf32_shvxworks_vec): New stanzas.
* configure: Regenerate.
* Makefile.am: Regenerate dependencies.
* Makefile.in: Regenerate.
* elf-vxworks.c (elf_vxworks_gott_symbol_p): New function.
(elf_vxworks_add_symbol_hook): Use it.
(elf_vxworks_link_output_symbol_hook): Likewise. Use the hash
table entry to check for weak undefined symbols and to obtain
the original bfd.
(elf_vxworks_emit_relocs): Use target_index instead of this_idx.
* elf32-sh-relocs.h: New file, split from elf32-sh.c.
(R_SH_DIR32): Use SH_PARTIAL32 for the partial_inplace field,
SH_SRC_MASK32 for the src_mask field, and SH_ELF_RELOC for the
special_function field.
(R_SH_REL32): Use SH_PARTIAL32 and SH_SRC_MASK32 here too.
(R_SH_REL32, R_SH_TLS_GD_32, R_SH_TLS_LD_32): Likewise.
(R_SH_TLS_LDO_32, R_SH_TLS_IE_32, R_SH_TLS_LE_32): Likewise.
(R_SH_TLS_DTPMOD32, R_SH_TLS_DTPOFF32, R_SH_TLS_TPOFF32): Likewise.
(R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT): Likewise.
(R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): Likewise.
(SH_PARTIAL32, SH_SRC_MASK32, SH_ELF_RELOC): Undefine at end of file.
* elf32-sh.c: Include elf32-vxworks.h.
(MINUS_ONE): Define.
(sh_elf_howto_table): Include elf32-sh-relocs.h with SH_PARTIAL32
set to TRUE, SH_SRC_MASK32 set to 0xffffffff, and SH_ELF_RELOC set
to sh_elf_reloc.
(sh_vxworks_howto_table): New variable. Include elf32-sh-relocs.h
with SH_PARTIAL32 set to FALSE, SH_SRC_MASK32 set to 0, and
SH_ELF_RELOC set to bfd_elf_generic_reloc.
(vxworks_object_p, get_howto_table): New functions.
(sh_elf_reloc_type_lookup): Fix typo. Use get_howto_table.
(sh_elf_info_to_howto): Use get_howto_table.
(sh_elf_relax_section): Honor the partial_inplace field of the
R_SH_DIR32 howto.
(sh_elf_relax_delete_bytes): Likewise.
(elf_sh_plt_info): New structure.
(PLT_ENTRY_SIZE): Replace both definitions with...
(ELF_PLT_ENTRY_SIZE): ...this new macro, with separate definitions for
INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
(elf_sh_plt0_entry_be): Update sizes of both definitions accordingly.
(elf_sh_plt0_entry_le): Likewise.
(elf_sh_plt_entry_be, elf_sh_plt_entry_le): Likewise.
(elf_sh_pic_plt_entry_be, elf_sh_pic_plt_entry_le): Likewise.
(elf_sh_plts): New structure, with separate definitions for
INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
(elf_sh_plt0_entry): Delete both definitions.
(elf_sh_plt_entry, elf_sh_pic_plt_entry): Likewise.
(elf_sh_sizeof_plt, elf_sh_plt_plt0_offset): Likewise.
(elf_sh_plt_temp_offset, elf_sh_plt_symbol_offset): Likewise.
(elf_sh_plt_reloc_offset): Likewise.
(movi_shori_putval): Delete in favor of...
(install_plt_field): ...this new function, with separate definitions
for INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
(get_plt_info): New function, with separate definitions
for INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
(elf_sh_plt0_linker_offset, elf_sh_plt0_gotid_offset): Delete.
(VXWORKS_PLT_HEADER_SIZE, VXWORKS_PLT_ENTRY_SIZE): New macros.
(vxworks_sh_plt0_entry_be, vxworks_sh_plt0_entry_le): New constants.
(vxworks_sh_plt_entry_be, vxworks_sh_plt_entry_le): Likewise.
(vxworks_sh_pic_plt_entry_be, vxworks_sh_pic_plt_entry_le): Likewise.
(get_plt_index, get_plt_offset): New functions.
(elf_sh_link_hash_table): Add srelplt2, plt_info and vxworks_p fields.
(sh_elf_link_hash_table_create): Initialize them.
(sh_elf_create_dynamic_sections): Call
elf_vxworks_create_dynamic_sections for VxWorks.
(allocate_dynrelocs): Use htab->plt_info to get the size of PLT
entries. Allocate relocation entries in .rela.plt.unloaded if
generating a VxWorks executable.
(sh_elf_always_size_sections): New function.
(sh_elf_size_dynamic_sections): Extend .rela.plt handling to
.rela.plt.unloaded.
(sh_elf_relocate_section): Use get_howto_table. Honor
partial_inplace when calculating the addend for dynamic
relocations. Use get_plt_index.
(sh_elf_finish_dynamic_symbol): Use get_plt_index, install_plt_field
and htab->plt_info. Fill in the bra .plt offset for VxWorks
executables. Populate .rela.plt.unloaded. Do not make
_GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
(sh_elf_finish_dynamic_sections): Use install_plt_field and
htab->plt_info. Handle cases where there is no special PLT header.
Populate the first relocation in .rela.plt.unloaded and fix up
the remaining entries.
(sh_elf_plt_sym_val): Use get_plt_info.
(elf_backend_always_size_sections): Define.
(TARGET_BIG_SYM, TARGET_BIG_NAME): Override for VxWorks.
(TARGET_LITTLE_SYM, TARGET_BIG_SYM): Likewise.
(elf32_bed, elf_backend_want_plt_sym): Likewise.
(elf_symbol_leading_char, elf_backend_want_got_underscore): Likewise.
(elf_backend_grok_prstatus, elf_backend_grok_psinfo): Likewise.
(elf_backend_add_symbol_hook): Likewise.
(elf_backend_link_output_symbol_hook): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_final_write_processing): Likewise.
(ELF_MAXPAGESIZE, ELF_COMMONPAGESIZE): Likewise.
* targets.c (bfd_elf32_shlvxworks_vec): Declare.
(bfd_elf32_shvxworks_vec): Likewise.
(_bfd_target_vector): Include bfd_elf32_shlvxworks_vec and
bfd_elf32_shvxworks_vec.
gas/
* config/tc-sh.c (apply_full_field_fix): New function.
(md_apply_fix): Use it instead of md_number_to_chars. Do not fill
in fx_addnumber for BFD_RELOC_32_PLT_PCREL.
(tc_gen_reloc): Use fx_addnumber rather than 0 as the default case.
* config/tc-sh.h (TARGET_FORMAT): Override for TE_VXWORKS.
ld/
2006-08-02 Richard Sandiford <richard@codesourcery.com>
Kazu Hirata <kazu@codesourcery.com>
Phil Edwards <phil@codesourcery.com>
* Makefile.am (ALL_EMULATIONS): Add eshelf_vxworks.o and
eshlelf_vxworks.o.
(eshelf_vxworks.c, eshlelf_vxworks.c): New rules.
* Makefile.in: Regenerate.
* configure.tgt (sh-*-vxworks): Use shelf_vxworks and
shlelf_vxworks.
* emulparams/shelf_vxworks.sh: New file.
* emulparams/shlelf_vxworks.sh: Likewise.
* emulparams/vxworks.sh (FINI): Prefix _etext with ${SYMPREFIX}.
(OTHER_END_SYMBOLS): Likewise _ehdr.
(DATA_END_SYMBOLS): Likewise _edata.
* emultempl/vxworks.em (vxworks_after_open): Check whether output_bfd
is indeed an ELF file before dealing with --force-dynamic.
ld/testsuite/
* ld-sh/rd-sh.exp: Treat vxworks1-static.d specially.
* ld-sh/sh-vxworks.exp: New file.
* ld-sh/sh.exp: Extend sh-linux SIZEOF_HEADERS handling to
sh-*-vxworks.
* ld-sh/vxworks1-le.dd, ld-sh/vxworks1-lib-le.dd,
* ld-sh/vxworks1-lib.dd, ld-sh/vxworks1-lib.nd,
* ld-sh/vxworks1-lib.rd, ld-sh/vxworks1-lib.s,
* ld-sh/vxworks1-static.d, ld-sh/vxworks1.dd,
* ld-sh/vxworks1.ld, ld-sh/vxworks1.rd, ld-sh/vxworks1.s,
* ld-sh/vxworks2-static.sd, ld-sh/vxworks2.s,
* ld-sh/vxworks2.sd, ld-sh/vxworks3-le.dd,
* ld-sh/vxworks3-lib-le.dd, ld-sh/vxworks3-lib.dd,
* ld-sh/vxworks3-lib.s, ld-sh/vxworks3.dd, ld-sh/vxworks3.s,
* ld-sh/vxworks4.d, ld-sh/vxworks4a.s, ld-sh/vxworks4b.s,
* ld-sh/reloc1.s, ld-sh/reloc1.d: New tests.
* config/tc-arm.c (parse_operands): Handle invalid register name
for OP_RIWR_RIWC.
gas/testsuite:
* gas/arm/iwmmxt-bad.s: Test invalid register names for wldrw and
wstrw.
* gas/arm/iwmmxt-bad.l: Update.
* config/tc-arm.c (enum operand_parse_code): Add OP_RIWC_RIWG.
(parse_operands): Handle it.
(insns): Use it for tmcr and tmrc.
gas/testsuite:
* gas/arm/iwmmxt.s: Test tmcr and tmrc with wcgr registers.
* gas/arm/iwmmxt.d: Update.
* bfd/elf64-x86-64.c: Add FreeBSD support.
(elf64_x86_64_fbsd_post_process_headers): New function.
* bfd/targets.c (_bfd_target_vector): Add bfd_elf64_x86_64_freebsd_vec.
* bfd/config.bfd (x64_64-*-freebsd*): Add bfd_elf64_x86_64_freebsd_vec to the targ_selvecs.
* bfd/configure.in: Add entry for bfd_elf64_x86_64_freebsd_vec.
* bfd/configure: Regenerate.
* gas/config/tc-i386.c (md_parse_option): Treat any target starting with elf64_x86_64 as a viable target for the -64 switch.
(i386_target_format): For 64-bit ELF flavoured output use ELF_TARGET_FORMAT64.
* gas/config/tc-i386.h (ELF_TARGET_FORMAT64): Define.
* ld/emulparams/elf_x86_64_fbsd.sh (OUTPUT_FORMAT): Define as elf64-x86-64-freebsd.
bfd/
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_ADD_IMM.
gas/
* tc-arm.c (do_t_add_sub): Use addw/subw when source is PC.
(md_convert_frag): Use correct reloc for add_pc. Use
BFD_RELOC_ARM_T32_ADD_IMM for normal add/sum.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_ADD_IMM.
(arm_force_relocation): Handle BFD_RELOC_ARM_T32_ADD_IMM.
gas/testsuite/
* gas/arm/thumb2_add.d: New test.
* gas/arm/thumb2_add.s: New test.
fixup_segment() to repeat a range check on a value that have already
been checked here.
* gas/sh/basic.exp: Run "too_large" dump test.
* gas/sh/too_large.s: New test file. Check that .byte directives do not
generate a bogus overflow message.
* gas/sh/too_large.s: New test control file.
* doc/as.texi: Fix spelling typo: branchs => branches.
* doc/c-m68hc11.texi: Likewise.
* config/tc-m68hc11.c: Likewise.
Support old spelling of command line switch for backwards compatibility.
2006-06-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch_tune_set): New.
(cpu_arch_isa): Likewise.
(i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
nops with short or long nop sequences based on -march=/.arch
and -mtune=.
(set_cpu_arch): Set cpu_arch_isa. If cpu_arch_tune_set is 0,
set cpu_arch_tune and cpu_arch_tune_flags.
(md_parse_option): For -march=, set cpu_arch_isa and set
cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
0. Set cpu_arch_tune_set to 1 for -mtune=.
(i386_target_format): Don't set cpu_arch_tune.
gas/testsuite/
2006-06-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run nops-1, nops-1-i386, nops-1-i686,
nops-1-merom, nops-2, nops-2-i386, nops-2-merom, x86-64-nops-1,
x86-64-nops-1-k8, x86-64-nops-1-nocona and x86-64-nops-1-merom.
* gas/i386/nops-1.s: New file.
* gas/i386/nops-2.s: Likewise.
* gas/i386/nops-1-i386.d: Likewise.
* gas/i386/nops-1-i686.d: Likewise.
* gas/i386/nops-1-merom.d: Likewise.
* gas/i386/nops-1.d: Likewise.
* gas/i386/nops-2-i386.d: Likewise.
* gas/i386/nops-2-merom.d: Likewise.
* gas/i386/nops-2.d: Likewise.
* gas/i386/x86-64-nops-1.s: Likewise.
* gas/i386/x86-64-nops-1-k8.d: Likewise.
* gas/i386/x86-64-nops-1-merom.d: Likewise.
* gas/i386/x86-64-nops-1-nocona.d: Likewise.
* gas/i386/x86-64-nops-1.d: Likewise.
* gas/i386/sse2.d: Updated to expect xchg %ax,%ax as 2 byte
nop.
* config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse
a directive saving VFP registers for ARMv6 or later.
(s_arm_unwind_save): Add parameter arch_v6 and call
s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
appropriate.
(md_pseudo_table): Add entry for new "vsave" directive.
* doc/c-arm.texi: Correct error in example for "save"
directive (fstmdf -> fstmdx). Also document "vsave" directive.
