2007-03-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Use Opcode_XXX instead of XXX on i.tm.base_opcode. (match_template): Likewise. (process_operands): Use ~0x3 mask to match MOV_AX_DISP32. * config/tc-i386.h (Opcode_D): New. (Opcode_FloatR): Likewise. (Opcode_FloatD): Likewise. (D): Redefined. (W): Likewise. (FloatMF): Likewise. (FloatR): Likewise. (FloatD): Likewise.
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3 changed files with 37 additions and 10 deletions
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@ -1,3 +1,19 @@
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2007-03-12 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (md_assemble): Use Opcode_XXX instead of XXX
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on i.tm.base_opcode.
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(match_template): Likewise.
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(process_operands): Use ~0x3 mask to match MOV_AX_DISP32.
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* config/tc-i386.h (Opcode_D): New.
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(Opcode_FloatR): Likewise.
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(Opcode_FloatD): Likewise.
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(D): Redefined.
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(W): Likewise.
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(FloatMF): Likewise.
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(FloatR): Likewise.
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(FloatD): Likewise.
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2007-03-09 Alexandre Oliva <aoliva@redhat.com>
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* app.c (do_scrub_chars): Recognize comments after # line "file".
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@ -1766,7 +1766,7 @@ md_assemble (line)
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/* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
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if (SYSV386_COMPAT
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&& (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
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i.tm.base_opcode ^= FloatR;
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i.tm.base_opcode ^= Opcode_FloatR;
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/* Zap movzx and movsx suffix. The suffix may have been set from
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"word ptr" or "byte ptr" on the source operand, but we'll use
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@ -2657,7 +2657,14 @@ match_template (void)
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}
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/* found_reverse_match holds which of D or FloatDR
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we've found. */
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found_reverse_match = t->opcode_modifier & (D | FloatDR);
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if ((t->opcode_modifier & D))
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found_reverse_match = Opcode_D;
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else if ((t->opcode_modifier & FloatD))
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found_reverse_match = Opcode_FloatD;
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else
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found_reverse_match = 0;
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if ((t->opcode_modifier & FloatR))
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found_reverse_match |= Opcode_FloatR;
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}
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else
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{
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@ -3322,7 +3329,7 @@ process_operands (void)
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default_seg = build_modrm_byte ();
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}
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else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
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else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
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{
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default_seg = &ds;
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}
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@ -159,6 +159,11 @@ typedef struct
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/* base_opcode is the fundamental opcode byte without optional
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prefix(es). */
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unsigned int base_opcode;
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#define Opcode_D 0x2 /* Direction bit:
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set if Reg --> Regmem;
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unset if Regmem --> Reg. */
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#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
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#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
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/* extension_opcode is the 3 bit extension for group <n> insns.
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This field is also used to store the 8-bit opcode suffix for the
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@ -207,19 +212,18 @@ typedef struct
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unsigned int opcode_modifier;
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/* opcode_modifier bits: */
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#define W 0x1 /* set if operands can be words or dwords
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#define D 0x1 /* has direction bit. */
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#define W 0x2 /* set if operands can be words or dwords
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encoded the canonical way */
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#define D 0x2 /* D = 0 if Reg --> Regmem;
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D = 1 if Regmem --> Reg: MUST BE 0x2 */
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#define Modrm 0x4
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#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
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#define Modrm 0x4 /* insn has a modrm byte. */
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#define ShortForm 0x10 /* register is in low 3 bits of opcode */
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#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
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#define Jump 0x40 /* special case for jump insns. */
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#define JumpDword 0x80 /* call and jump */
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#define JumpByte 0x100 /* loop and jecxz */
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#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
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#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
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#define FloatMF 0x400 /* FP insn memory format bit, sized by 0x4 */
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#define FloatR 0x800 /* src/dest swap for floats. */
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#define FloatD 0x1000 /* has float insn direction bit. */
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#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
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#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
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#define Size64 0x8000 /* needs size prefix if in 64-bit mode */
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