* config/tc-score.c (score_relax_frag): If next frag contains 32 bit branch
instruction, handle it specially. (score_insns): Modify 32 bit branch instruction.
This commit is contained in:
Mei Ligang
parent
c06b7b0ba3
commit
41c55c875a
1 changed files with 23 additions and 25 deletions
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@ -375,21 +375,21 @@ static const struct asm_opcode score_insns[] =
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{"andri", 0x18000000, 0x3e000001, 0x8000, Rd_Rs_I14, do_rdrsi14},
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{"andri.c", 0x18000001, 0x3e000001, 0x8000, Rd_Rs_I14, do_rdrsi14},
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{"and!", 0x2004, 0x700f, 0x00000021, Rd_Rs, do16_rdrs},
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{"bcs", 0x08000000, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bcc", 0x08000400, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bcnz", 0x08003800, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bcs", 0x08000000, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bcc", 0x08000400, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bcnz", 0x08003800, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bcsl", 0x08000001, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bccl", 0x08000401, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bcnzl", 0x08003801, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bcs!", 0x4000, 0x7f00, 0x08000000, PC_DISP8div2, do16_branch},
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{"bcc!", 0x4100, 0x7f00, 0x08000400, PC_DISP8div2, do16_branch},
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{"bcnz!", 0x4e00, 0x7f00, 0x08003800, PC_DISP8div2, do16_branch},
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{"beq", 0x08001000, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"beq", 0x08001000, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"beql", 0x08001001, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"beq!", 0x4400, 0x7f00, 0x08001000, PC_DISP8div2, do16_branch},
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{"bgtu", 0x08000800, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bgt", 0x08001800, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bge", 0x08002000, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bgtu", 0x08000800, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bgt", 0x08001800, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bge", 0x08002000, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bgtul", 0x08000801, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bgtl", 0x08001801, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bgel", 0x08002001, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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@ -405,9 +405,9 @@ static const struct asm_opcode score_insns[] =
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{"bitset!", 0x6005, 0x7007, 0x0000002b, Rd_I5, do16_rdi5},
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{"bittst!", 0x6006, 0x7007, 0x0000002d, Rd_I5, do16_rdi5},
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{"bittgl!", 0x6007, 0x7007, 0x0000002f, Rd_I5, do16_rdi5},
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{"bleu", 0x08000c00, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"ble", 0x08001c00, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"blt", 0x08002400, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bleu", 0x08000c00, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"ble", 0x08001c00, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"blt", 0x08002400, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bleul", 0x08000c01, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"blel", 0x08001c01, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bltl", 0x08002401, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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@ -415,13 +415,13 @@ static const struct asm_opcode score_insns[] =
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{"bleu!", 0x4300, 0x7f00, 0x08000c00, PC_DISP8div2, do16_branch},
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{"ble!", 0x4700, 0x7f00, 0x08001c00, PC_DISP8div2, do16_branch},
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{"blt!", 0x4900, 0x7f00, 0x08002400, PC_DISP8div2, do16_branch},
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{"bmi", 0x08002800, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bmi", 0x08002800, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bmil", 0x08002801, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bmi!", 0x00004a00, 0x00007f00, 0x08002800, PC_DISP8div2, do16_branch},
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{"bne", 0x08001400, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bne", 0x08001400, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bnel", 0x08001401, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bne!", 0x4500, 0x7f00, 0x08001400, PC_DISP8div2, do16_branch},
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{"bpl", 0x08002c00, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bpl", 0x08002c00, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bpll", 0x08002c01, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bpl!", 0x4b00, 0x7f00, 0x08002c00, PC_DISP8div2, do16_branch},
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{"brcs", 0x00000008, 0x3e007fff, 0x0004, x_Rs_x, do_rs},
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@ -488,14 +488,14 @@ static const struct asm_opcode score_insns[] =
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{"brvcl!", 0x0d0c, 0x7f0f, 0x00003409, x_Rs, do16_xrs},
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{"brcnzl!", 0x0e0c, 0x7f0f, 0x00003809, x_Rs, do16_xrs},
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{"brl!", 0x0f0c, 0x7f0f, 0x00003c09, x_Rs, do16_xrs},
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{"bvs", 0x08003000, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bvc", 0x08003400, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bvs", 0x08003000, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bvc", 0x08003400, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"bvsl", 0x08003001, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bvcl", 0x08003401, 0x3e007c01, 0x8000, PC_DISP19div2, do_branch},
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{"bvs!", 0x4c00, 0x7f00, 0x08003000, PC_DISP8div2, do16_branch},
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{"bvc!", 0x4d00, 0x7f00, 0x08003400, PC_DISP8div2, do16_branch},
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{"b!", 0x4f00, 0x7f00, 0x08003c00, PC_DISP8div2, do16_branch},
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{"b", 0x08003c00, 0x3e007c01, 0x08003c00, PC_DISP19div2, do_branch},
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{"b", 0x08003c00, 0x3e007c01, 0x4000, PC_DISP19div2, do_branch},
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{"cache", 0x30000000, 0x3ff00000, 0x8000, OP5_rvalueRs_SI15, do_cache},
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{"ceinst", 0x38000000, 0x3e000000, 0x8000, I5_Rs_Rs_I5_OP5, do_ceinst},
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{"clz", 0x3800000d, 0x3e007fff, 0x8000, Rd_Rs_x, do_rdrs},
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@ -4609,11 +4609,10 @@ do_branch (char *str)
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/* Branch 32 offset field : 20 bit, 16 bit branch offset field : 8 bit. */
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inst.instruction |= (inst.reloc.exp.X_add_number & 0x3fe) | ((inst.reloc.exp.X_add_number & 0xffc00) << 5);
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/* Take the branch condition code. */
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inst.relax_inst = 0x4000 | (((inst.instruction >> 10) & 0xf) << 8);
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if ((abs_value & 0xfffffe00) == 0)
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/* Compute 16 bit branch instruction. */
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if ((inst.relax_inst != 0x8000) && (abs_value & 0xfffffe00) == 0)
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{
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inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 8);
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inst.relax_inst |= ((inst.reloc.exp.X_add_number >> 1) & 0xff);
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inst.relax_size = 2;
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}
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@ -4621,9 +4620,6 @@ do_branch (char *str)
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{
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inst.relax_inst = 0x8000;
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}
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if (inst.instruction & 1)
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inst.relax_inst = 0x8000;
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}
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static void
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@ -5045,7 +5041,9 @@ score_relax_frag (asection * sec ATTRIBUTE_UNUSED, fragS * fragp, long stretch A
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n_insn_size = RELAX_OLD (next_fragp->fr_subtype);
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}
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n_relaxable_p = RELAX_OPT (next_fragp->fr_subtype);
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if (RELAX_TYPE (next_fragp->fr_subtype) == PC_DISP19div2)
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b32_relax_to_b16 (next_fragp);
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n_relaxable_p = RELAX_OPT (next_fragp->fr_subtype);
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if (word_align_p)
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{
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@ -5061,7 +5059,7 @@ score_relax_frag (asection * sec ATTRIBUTE_UNUSED, fragS * fragp, long stretch A
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else if (insn_size == 2)
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{
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/* 16 -> 32. */
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if (relaxable_p && ((n_insn_size == 4) && !n_relaxable_p))
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if (relaxable_p && (((n_insn_size == 4) && !n_relaxable_p) || (n_insn_size > 4)))
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{
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grows += 2;
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do_relax_p = 1;
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