gas/
2006-09-28 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.h (CpuMNI): Renamed to ... (CpuSSSE3): This. (CpuUnknownFlags): Updated. (processor_type): Replace PROCESSOR_YONAH with PROCESSOR_CORE and PROCESSOR_MEROM with PROCESSOR_CORE2. * config/tc-i386.c: Updated. * doc/c-i386.texi: Likewise. * config/tc-i386.c (cpu_arch): Add ".ssse3", "core" and "core2". include/opcode/ 2006-09-28 H.J. Lu <hongjiu.lu@intel.com> * i386.h: Replace CpuMNI with CpuSSSE3.
This commit is contained in:
H.J. Lu
parent
07adf1816d
commit
ef05d49568
6 changed files with 80 additions and 55 deletions
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@ -1,3 +1,15 @@
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2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.h (CpuMNI): Renamed to ...
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(CpuSSSE3): This.
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(CpuUnknownFlags): Updated.
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(processor_type): Replace PROCESSOR_YONAH with PROCESSOR_CORE
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and PROCESSOR_MEROM with PROCESSOR_CORE2.
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* config/tc-i386.c: Updated.
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* doc/c-i386.texi: Likewise.
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* config/tc-i386.c (cpu_arch): Add ".ssse3", "core" and "core2".
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2006-09-28 Bridge Wu <mingqiao.wu@gmail.com>
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* config/tc-arm.c (md_apply_fix): Do not clear write_back bit.
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@ -469,12 +469,18 @@ static const arch_entry cpu_arch[] =
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{"nocona", PROCESSOR_NOCONA,
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
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{"yonah", PROCESSOR_YONAH,
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{"yonah", PROCESSOR_CORE,
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
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{"merom", PROCESSOR_MEROM,
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{"core", PROCESSOR_CORE,
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuMNI},
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|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
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{"merom", PROCESSOR_CORE2,
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
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{"core2", PROCESSOR_CORE2,
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
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{"k6", PROCESSOR_K6,
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
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{"k6_2", PROCESSOR_K6,
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@ -503,6 +509,8 @@ static const arch_entry cpu_arch[] =
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CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
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{".sse3", PROCESSOR_UNKNOWN,
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CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
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{".ssse3", PROCESSOR_UNKNOWN,
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CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
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{".3dnow", PROCESSOR_UNKNOWN,
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CpuMMX|Cpu3dnow},
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{".3dnowa", PROCESSOR_UNKNOWN,
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@ -750,9 +758,9 @@ i386_align_code (fragP, count)
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1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
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f32_patt will be used.
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2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
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3. For PROCESSOR_MEROM, alt_long_patt will be used.
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3. For PROCESSOR_CORE2, alt_long_patt will be used.
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4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
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PROCESSOR_YONAH, PROCESSOR_MEROM, PROCESSOR_K6, PROCESSOR_ATHLON
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PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
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and PROCESSOR_GENERIC64, alt_short_patt will be used.
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When -mtune= isn't used, alt_short_patt will be used if
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@ -809,13 +817,13 @@ i386_align_code (fragP, count)
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else
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patt = f32_patt;
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break;
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case PROCESSOR_MEROM:
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case PROCESSOR_CORE2:
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patt = alt_long_patt;
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break;
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case PROCESSOR_PENTIUMPRO:
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case PROCESSOR_PENTIUM4:
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case PROCESSOR_NOCONA:
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case PROCESSOR_YONAH:
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case PROCESSOR_CORE:
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case PROCESSOR_K6:
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case PROCESSOR_ATHLON:
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case PROCESSOR_K8:
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@ -845,7 +853,7 @@ i386_align_code (fragP, count)
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case PROCESSOR_PENTIUMPRO:
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case PROCESSOR_PENTIUM4:
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case PROCESSOR_NOCONA:
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case PROCESSOR_YONAH:
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case PROCESSOR_CORE:
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case PROCESSOR_K6:
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case PROCESSOR_ATHLON:
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case PROCESSOR_K8:
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@ -858,7 +866,7 @@ i386_align_code (fragP, count)
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else
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patt = f32_patt;
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break;
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case PROCESSOR_MEROM:
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case PROCESSOR_CORE2:
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if ((cpu_arch_isa_flags & Cpu686) != 0)
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patt = alt_long_patt;
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else
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@ -3883,10 +3891,11 @@ output_insn ()
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unsigned char *q;
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unsigned int prefix;
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/* All opcodes on i386 have either 1 or 2 bytes. Merom New
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Instructions have 3 bytes. We may use one more higher byte
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to specify a prefix the instruction requires. */
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if ((i.tm.cpu_flags & CpuMNI) != 0)
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/* All opcodes on i386 have either 1 or 2 bytes. Supplemental
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Streaming SIMD extensions 3 Instructions have 3 bytes. We may
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use one more higher byte to specify a prefix the instruction
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requires. */
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if ((i.tm.cpu_flags & CpuSSSE3) != 0)
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{
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if (i.tm.base_opcode & 0xff000000)
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{
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@ -3927,7 +3936,7 @@ output_insn ()
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}
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else
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{
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if ((i.tm.cpu_flags & CpuMNI) != 0)
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if ((i.tm.cpu_flags & CpuSSSE3) != 0)
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{
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p = frag_more (3);
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*p++ = (i.tm.base_opcode >> 16) & 0xff;
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@ -5980,7 +5989,7 @@ md_show_usage (stream)
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fprintf (stream, _("\
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-march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
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i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
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yonah, merom, k6, athlon, k8, generic32, generic64\n"));
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core, core2, k6, athlon, k8, generic32, generic64\n"));
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}
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@ -187,7 +187,7 @@ typedef struct
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#define CpuPadLock 0x10000 /* VIA PadLock required */
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#define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */
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#define CpuVMX 0x40000 /* VMX Instructions required */
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#define CpuMNI 0x80000 /* Merom New Instructions required */
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#define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */
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#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */
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#define CpuABM 0x200000 /* ABM New Instructions required */
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@ -198,7 +198,7 @@ typedef struct
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/* The default value for unknown CPUs - enable all features to avoid problems. */
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#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuMNI|CpuABM|CpuSSE4a)
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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@ -390,8 +390,8 @@ enum processor_type
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PROCESSOR_PENTIUMPRO,
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PROCESSOR_PENTIUM4,
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PROCESSOR_NOCONA,
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PROCESSOR_YONAH,
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PROCESSOR_MEROM,
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PROCESSOR_CORE,
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PROCESSOR_CORE2,
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PROCESSOR_K6,
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PROCESSOR_ATHLON,
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PROCESSOR_K8,
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@ -95,8 +95,8 @@ instructions. The following architectures are recognized:
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@code{pentium4},
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@code{prescott},
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@code{nocona},
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@code{yonah},
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@code{merom},
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@code{core},
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@code{core2},
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@code{k6},
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@code{k6_2},
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@code{athlon},
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@ -752,7 +752,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
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@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
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@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
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@item @samp{prescott} @tab @samp{nocona} @tab @samp{yonah} @tab @samp{merom}
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@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
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@item @samp{k6} @tab @samp{athlon} @tab @samp{sledgehammer} @tab @samp{k8}
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@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.padlock} @tab @samp{.pacifica}
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@ -1,3 +1,7 @@
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2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
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* i386.h: Replace CpuMNI with CpuSSSE3.
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2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
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Joseph Myers <joseph@codesourcery.com>
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Ian Lance Taylor <ian@wasabisystems.com>
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@ -1375,40 +1375,40 @@ static const template i386_optab[] =
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{"vmxoff", 0, 0x0f01, 0xc4, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} },
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{"vmxon", 1, 0xf30fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} },
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/* Merom New Instructions. */
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/* Supplemental Streaming SIMD extensions 3 Instructions. */
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{"phaddw", 2, 0x0f3801,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phaddw", 2, 0x660f3801,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phaddd", 2, 0x0f3802,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phaddd", 2, 0x660f3802,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phaddsw", 2, 0x0f3803,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phaddsw", 2, 0x660f3803,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phsubw", 2, 0x0f3805,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phsubw", 2, 0x660f3805,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phsubd", 2, 0x0f3806,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phsubd", 2, 0x660f3806,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phsubsw", 2, 0x0f3807,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phsubsw", 2, 0x660f3807,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pmaddubsw", 2, 0x0f3804,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"pmaddubsw", 2, 0x660f3804,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pmulhrsw", 2, 0x0f380b,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"pmulhrsw", 2, 0x660f380b,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pshufb", 2, 0x0f3800,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"pshufb", 2, 0x660f3800,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"psignb", 2, 0x0f3808,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"psignb", 2, 0x660f3808,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"psignw", 2, 0x0f3809,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"psignw", 2, 0x660f3809,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"psignd", 2, 0x0f380a,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"psignd", 2, 0x660f380a,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"palignr", 3, 0x0f3a0f,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LongMem, RegMMX } },
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{"palignr", 3, 0x660f3a0f,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
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{"pabsb", 2, 0x0f381c,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"pabsb", 2, 0x660f381c,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pabsw", 2, 0x0f381d,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"pabsw", 2, 0x660f381d,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pabsd", 2, 0x0f381e,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"pabsd", 2, 0x660f381e,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phaddw", 2, 0x0f3801,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phaddw", 2, 0x660f3801,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phaddd", 2, 0x0f3802,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phaddd", 2, 0x660f3802,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phaddsw", 2, 0x0f3803,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phaddsw", 2, 0x660f3803,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phsubw", 2, 0x0f3805,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phsubw", 2, 0x660f3805,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phsubd", 2, 0x0f3806,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phsubd", 2, 0x660f3806,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"phsubsw", 2, 0x0f3807,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"phsubsw", 2, 0x660f3807,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pmaddubsw", 2, 0x0f3804,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"pmaddubsw", 2, 0x660f3804,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pmulhrsw", 2, 0x0f380b,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"pmulhrsw", 2, 0x660f380b,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pshufb", 2, 0x0f3800,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"pshufb", 2, 0x660f3800,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"psignb", 2, 0x0f3808,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"psignb", 2, 0x660f3808,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"psignw", 2, 0x0f3809,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"psignw", 2, 0x660f3809,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"psignd", 2, 0x0f380a,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"psignd", 2, 0x660f380a,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"palignr", 3, 0x0f3a0f,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LongMem, RegMMX } },
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{"palignr", 3, 0x660f3a0f,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
|
||||
{"pabsb", 2, 0x0f381c,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pabsb", 2, 0x660f381c,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pabsw", 2, 0x0f381d,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pabsw", 2, 0x660f381d,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pabsd", 2, 0x0f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pabsd", 2, 0x660f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
|
||||
/* AMD 3DNow! instructions. */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue