(load_address, macro): Use load_delay_nop() to build a nop
which can be omitted with gpr_interlocks.
* gas/mips/lb-xgot-ilocks.d: Remove nops in load delay slot.
* gas/mips/mips-abi32-pic.d: Likewise.
* gas/mips/mips-abi32-pic2.d: Likewise.
* gas/mips/mips-gp32-fp32-pic.d: Likewise.
* gas/mips/mips-gp32-fp64-pic.d: Likewise.
* gas/mips/mips-gp64-fp32-pic.d: Likewise.
* gas/mips/mips-gp64-fp64-pic.d: Likewise.
* gas/mips/relax-swap1-mips2.d: Likewise.
* gas/mips/lb-svr4pic-ilocks.d: New test.
* gas/mips/mips.exp: Run it.
* elf32-xtensa.c (elf_xtensa_check_relocs): Remove code to read
literal tables and check for relocs outside of literal pools.
(elf_xtensa_make_sym_local): Don't clear ELF_LINK_NON_GOT_REF flag.
(elf_xtensa_fix_refcounts): Don't check ELF_LINK_NON_GOT_REF or
set DF_TEXTREL.
(elf_xtensa_size_dynamic_sections): Don't add DT_TEXTREL entry.
(elf_xtensa_relocate_section): Read literal tables and check for
dynamic relocations in read-only sections and not in literal pools.
gas/ChangeLog:
* config/tc-xtensa.c (xtensa_post_relax_hook): Create literal
tables even when use_literal_section flag is not set.
--mul-bug-abort and the default behavior.
* config/tc-cris.c (cris_insn_kind): New member CRIS_INSN_MUL.
(err_for_dangerous_mul_placement): New variable.
(STATE_MUL, OPTION_MULBUG_ABORT_ON, OPTION_MULBUG_ABORT_OFF): New
macros.
(md_cris_relax_table): Have placeholder for STATE_MUL.
(md_longopts): New options --mul-bug-abort and --no-mul-bug-abort.
(cris_relax_frag) <case ENCODE_RELAX (STATE_MUL, STATE_BYTE)>: New
case doing nothing.
(md_estimate_size_before_relax) <case ENCODE_RELAX (STATE_MUL,
STATE_BYTE)>: Ditto.
(md_convert_frag) <ENCODE_RELAX (STATE_MUL, STATE_BYTE)>: Check
alignment and position of this frag, emit error message if
suspicious.
(md_assemble): For a multiply insn and when checking it,
transform the current frag into a special frag for that purpose.
(md_parse_option) <case OPTION_MULBUG_ABORT_OFF, case
OPTION_MULBUG_ABORT_ON>: Handle new options.
(xtensa_move_literals): Call mark_literal_frags for all literal
segments, including init and fini literal segments.
(xtensa_post_relax_hook): Swap use of xt_insn_sec and xt_literal_sec.
R_PARISC_PCREL32 and R_PARISC_PCREL64 relocations.
* tc-hppa.c (cons_fix_new_hppa): Check for PC relative base type.
(pa_comm): Set BSF_OBJECT in symbol flags.
* config/tc-ia64.c (dot_align): New.
(ia64_do_align): Make it static.
(md_pseudo_table): Use "dot_align" for "align".
(ia64_md_do_align): Don't set align_frag here.
(ia64_handle_align): Add a stop bit to the previous bundle if
needed.
* config/tc-ia64.h (ia64_do_align): Removed.
opcodes:
* sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
* sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
accordingly.
bfd:
* archures.c: Add bfd_mach_sh4_nommu_nofpu.
* cpu-sh.c: Ditto.
* elf32-sh.c: Ditto.
* bfd-in2.h: Regenerate.
include/elf:
* sh.h: Add EF_SH4_NOMMU_NOFPU.
gas:
* config/tc-sh.c (md_parse_option): Add -isa=sh4-nofpu and
-isa=sh4-nommu-nofpu options. Adjust help messages accordingly.
(sh_elf_final_processing): Output BFD type sh4_nofpu if that is
the most general type or the user specifically requested it.
(md_assemble): Add a new error message for when an instruction
is understood, but is not allowed due to an -isa option.
* config/tc-ia64.c (align_frag): New.
(md_assemble): Set the tc_frag_data field in align_frag for
IA64_OPCODE_FIRST instructions.
(ia64_md_do_align): Set align_frag.
(ia64_handle_align): Add a stop bit if needed.
* config/tc-ia64.h (TC_FRAG_TYPE): New.
(TC_FRAG_INIT): New.
gas:
* tc-sh.c (build_Mytes): Add REG_N_D and REG_N_B01
nibble types to assembler.
opcodes:
* sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
ensure that double registers have even numbers.
Add REG_N_B01 for nn01 (binary 01) nibble to ensure
that reserved instruction 0xfffd does not decode the same
as 0xfdfd (ftrv).
* sh-opc.h: Add REG_N_D nibble type and use it whereever
REG_N refers to a double register.
Add REG_N_B01 nibble type and use it instead of REG_NM
in ftrv.
Adjust the bit patterns in a few comments.
* config/tc-ia64.c (output_endp): New.
(count_bits): Delete.
(ia64_flush_insns, process_one_record, optimize_unw_records): Handle
endp unwind records.
(fixup_unw_records): Handle endp unwind records. Delete code for
shortening prologue regions not followed by a body record.
(dot_endp): Call add_unwind_entry to emit endp unwind record.
* config/tc-ia64.h (unw_record_type): Add endp.
* config/tc-ia64.c (ia64_convert_frag): Call md_number_to_chars to
fill padding bytes with zeroes.
(emit_one_bundle): New locals last_ptr, end_ptr. Rewrite code that
sets unwind_record slot_number and slot_frag fields.
* config/tc-mips.c (hilo_interlocks): Change definition
so that MIPS32, MIPS64 and later ISAs are included, along with
the already-included machines. Update comments.
(RELAX_FIRST, RELAX_SECOND): Turn into 8-bit quantities.
(RELAX_USE_SECOND): Bump to 0x10000.
(RELAX_SECOND_LONGER, RELAX_NOMACRO, RELAX_DELAY_SLOT): New flags.
(mips_macro_warning): New variable.
(md_assemble): Wrap macro expansion in macro_start() and macro_end().
(s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Likewise.
(relax_close_frag): Set mips_macro_warning.first_frag. Adjust use
of RELAX_ENCODE.
(append_insn): Update mips_macro_warning.sizes.
(macro_start, macro_warning, macro_end): New functions.
(macro_build): Don't emit warnings here.
(macro_build_lui, md_estimate_size_before_relax): ...or here.
(md_convert_frag): Check for cases where one macro alternative
needs a warning and the other doesn't. Emit a warning if the
longer sequence was chosen.
* config/tc-mips.c (RELAX_ENCODE): Take three arguments: the size of
the first sequence, the size of the second sequence, and a flag
that says whether we should warn.
(RELAX_OLD, RELAX_NEW, RELAX_RELOC[123]): Delete.
(RELAX_FIRST, RELAX_SECOND): New.
(mips_relax): New variable.
(relax_close_frag, relax_start, relax_switch, relax_end): New fns.
(append_insn): Remove "place" argument. Use mips_relax.sequence
rather than "place" to check whether we're expanding the second
alternative of a relaxable macro. Remove redundant check for
branch relaxation. If generating a normal insn, and there
is not enough room in the current frag, call relax_close_frag()
to close it. Update mips_relax.sizes[]. Emit fixups for the
second version of a relaxable macro. Record the first relaxable
fixup in mips_relax. Remove tc_gen_reloc workaround.
(macro_build): Remove all uses of "place". Use mips_relax.sequence
in the same way as in append_insn.
(mips16_macro_build): Remove "place" argument.
(macro_build_lui): As for macro_build. Don't drop the add_symbol
when generating the second version of a relaxable macro.
(load_got_offset, add_got_offset): New functions.
(load_address, macro): Use new relaxation machinery. Remove
tc_gen_reloc workarounds.
(md_estimate_size_before_relax): Set RELAX_USE_SECOND if the second
version of a relaxable macro is needed. Return -RELAX_SECOND if the
first version is needed.
(tc_gen_reloc): Remove relaxation handling.
(md_convert_frag): Go through the fixups for a relaxable macro and
mark those that belong to the unneeded alternative as done. If the
second alternative is needed, adjust the fixup addresses to account
for the deleted first alternative.
testsuite/
* gas/mips/elf-rel19.[sd]: New test.
* gas/mips/mips.exp: Run it.
* config/tc-mips.c (append_insn): Properly detect variant frags
that preclude swapping of relaxed branches. Correctly swap
instructions between frags when dealing with relaxed branches.
gas/testsuite/
* gas/mips/relax-swap1-mips1.d: New test for branch relaxation
with swapping for MIPS1.
* gas/mips/relax-swap1-mips2.d: New test for branch relaxation
with swapping for MIPS2.
* gas/mips/relax-swap1.l: Stderr output for the new tests.
* gas/mips/relax-swap1.s: Source for the new tests.
* gas/mips/relax-swap2.d: New test for branch likely relaxation
with swapping.
* gas/mips/relax-swap2.l: Stderr output for the new test.
* gas/mips/relax-swap2.s: Source for the new test.
* gas/mips/mips.exp: Run the new tests.
* config/tc-mips.c (macro_build_jalr): When adding an R_MIPS_JALR
reloc, reserve space for the delay slot as well as the jalr itself.
gas/testsuite/
* gas/mips/elf-rel18.[sd]: New test.
* gas/mips/mips.exp: Run it.
(cop_interlocks): Check ISA level.
(cop_mem_interlocks): Define.
(reg_needs_delay): Check cop_interlocks rather than
ISA_HAS_COPROC_DELAYS.
(append_insn): Likewise. Use cop_mem_interlocks rather than
directly checking mips_opts.isa.
(mips_emit_delays): Likewise.
* config/tc-ia64.c (unwind): Move next_slot_number and
next_slot_frag to ...
(unw_rec_list): Here.
(free_list_records): Removed.
(output_unw_records): Likewise.
(generate_unwind_image): Make it void.
(alloc_record): Initialize next_slot_number and next_slot_frag.
(slot_index): Take .org, .space and .align into account.
(fixup_unw_records): Don't set slot_number to 0. Use
list->next_slot_number and list->next_slot_frag instead of
unwind.next_slot_number and unwind.next_slot_frag.
(ia64_convert_frag): New.
(generate_unwind_image): Generate a rs_machine_dependent frag
for unwind record.
(emit_one_bundle): Use list->next_slot_number and
list->next_slot_frag instead of unwind.next_slot_number and
unwind.next_slot_frag.
* config/tc-ia64.h (md_convert_frag): Defined as
ia64_convert_frag.
(md_estimate_size_before_relax): Defined as (f)->fr_var.
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
(ctrl_table): Add "flags" keyword and some comments.
(flag_table): Convert to uppercase.
(get_flags_operand): Be case insensitive.
(get_interrupt_operand): Be case insensitive. Support notation
where the inperrupt arguments are separated by commas.
(get_operands): Check whether get_flags_operand consumed all
arguments. Return failure if get_ctrl_operand didn't recognize a
valid control register.
(get_specific): Add case CLASS_CTRL: Test for valid control
register for ldctlb opcode.
(build_bytes): Check for valid control registers.
(s_comm): Split out code to..
(s_comm_internal): ..here. Tidy error returns. Rearrange so that
"name" from input line may be used in more places. Merge code
testing for valid size from elf_common. Merge code from
s_lcomm_internal. Call comm_parse_extra.
(bss_alloc): New function, split out of s_lcomm_internal and
elf_common.
(parse_align): Likewise.
(s_lcomm_internal): Rewrite.
(s_lcomm, s_lcomm_bytes): Use s_comm_internal.
* read.h (bss_alloc, parse_align, s_comm_internal): Declare.
* config/obj-elf.c (elf_common): Split out code to..
(elf_common_parse): ..here. Remove code common to s_comm_internal,
parse_align and bss_alloc. Rearrange and Tidy.
* config/tc-alpha.h (TC_IMPLICIT_LCOMM_ALIGNMENT): Define.
* ppc-opc.c (MO): Make optional.
(RAO, RSO, SHO): New optional forms of RA, RS, SH operands.
(tlbwe): Accept for both PPC403 and BOOKE. Make all operands optional.
gas:
* tc-ppc.c (md_assemble): Rewrite comment about optional operands
to indicate that 'all or none' is also handled. Pluralize a
word in another comment.
gas/testsuite:
* gas/ppc/booke.s: Add two more forms of the mbar instruction
and three forms of the tlbwe instruction.
* gas/ppc/booke.d: Update to match.
* config/tc-mips.c (macro): Switch misordered call to frag_grow()
and setting of tc_fr_offset.
gas/testsuite/
* gas/mips/elf-rel16.[sd]: New test.
* gas/mips/mips.exp: Run it.
* gas/mips/elf-rel-xgot-n32.d: Fix addends for "lw $5,dl1+34($5)".
* gas/mips/elf-rel-xgot-n64.d: Likewise.
* config/tc-sh.c: Add support for sh4a and no-fpu variants,
with appropriate additions to md_show_usage.
* testsuite/gas/sh/basic.exp: Call tests for sh4a.
* testsuite/gas/sh/{err-sh4a-fp.s, err-sh4a.s,
err-sh4al-dsp.s, sh4a-dsp.d, sh4a-dsp.s, sh4a-fp.d,
sh4a-fp.s, sh4a.d, sh4a.s, sh4al-dsp.d, sh4al-dsp.s:
New files, tests for sh4a and related variants.
* doc/c-sh.texi: Document new -isa options.
* doc/c-sh64.texi: Ditto.
* NEWS: Mention new support for sh4a.
(md_apply_fix3): Likewise.
(cc_names): Add alias names for the names generated by the
disassembler.
(get_cc_operand): Be case insensitive.
(get_operands): Improve error handling for cc operands.
(check_operand): Not used, remove.
(md_assemble): Remove unused variable prev_opcode. Skip
whitespace until end-of-line only. Restore *op_end after call to
hash_find.
for loading addresses using CALL relocations.
Don't emit CALL relocations when a base register is used.
* gas/mips/lca-svr4pic.d: New test for the "lca" macro.
* gas/mips/lca-xgot.d: Likewise.
* gas/mips/lca.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
* opcode/mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB.
* mips-opc.c (mips_builtin_opcodes): Handle new macros: "lca" and
"dlca".
(rn_table, iwmmxt_table, cp_table, cn_table, fn_table, sn_table,
dn_table, mav_mvf_table, mac_mvd_table, mav_mvfx_table,
mav_mvax_table, mav_dspc_table): Initialise new field.
(insert_reg_alias): Initialise new field.
(md_pseudo_table): Add "unreq" entry.
(s_unreq): New function: Undo the effects of a previous .req.
* doc/c-arm.texi: Document new pseudo op.
* NEWS: Mention new feature.
* testsuite/gas/arm/req.s: New test file. Check .req and .unreq psuedo ops.
* testsuite/gas/arm/req.l: Expected error output from req.s test.
* testsuite/gas/arm/copro.d: Set target architecture for objdump so that the
test will work on architectures which cannot encode higher arm architecture
types in their file headers.
* testsuite/gas/arm/arm.exp: Run new req.s test.
Skip thumb instruction test for PE targets which do not support
thumb relocations.
* testsuite/gas/elf/elf.exp: Skip special handling of section2 test for XScale
targets - it is no longer needed.
2003-10-22 Andreas Schwab <schwab@suse.de>
H.J. Lu <hongjiu.lu@intel.com>
Jim Wilson <wilson@specifixinc.com>
* config/tc-ia64.c (update_qp_mutex): New.
(note_register_values): Properly handle one of PRs in compare
is PR0. Don't add a mutex relation for .and.orcm/.or.andcm.
Clear mutex relation for .none/.unc. Don't clear mutex relation
on predicated compare.
testsuite/
2003-10-22 Andreas Schwab <schwab@suse.de>
H.J. Lu <hongjiu.lu@intel.com>
* gas/ia64/dv-mutex-err.s: Add more tests for compare.
* gas/ia64/dv-mutex.s: Likewise.
* gas/ia64/dv-mutex-err.l: Updated.
* gas/ia64/dv-mutex.d: Likewise.
2003-10-14 Bob Wilson <bob.wilson@acm.org>
* elf32-xtensa.c (get_is_linkonce_section): Delete.
(xtensa_is_property_section, xtensa_is_littable_section): Use
XTENSA_INSN_SEC_NAME and XTENSA_LIT_SEC_NAME macros. Do not recognize
linkonce sections containing ".xt.insn" and ".xt.lit" substrings.
(xtensa_get_property_section_name): Check section name instead of
calling get_is_linkonce_section. Remove unused bfd parameter. Use
XTENSA_INSN_SEC_NAME and XTENSA_LIT_SEC_NAME macros. Never generate
linkonce section names by appending ".xt.insn" or ".xt.lit".
(xtensa_read_table_entries): Remove bfd argument in call to
xtensa_get_property_section_name. Free section name when done.
(elf_xtensa_combine_prop_entries): Free leaking table.
gas ChangeLog:
2003-10-14 Bob Wilson <bob.wilson@acm.org>
* config/tc-xtensa.c (xtensa_create_property_segments): Remove bfd
argument in call to xtensa_get_property_section_name. Formatting.
include ChangeLog:
2003-10-14 Bob Wilson <bob.wilson@acm.org>
* elf/xtensa.h: Formatting. Fix comments about property section
names for linkonce sections.
* tc-z8k.c (newfix): Tell fix_new_exp about pc relativeness.
(md_apply_fix3): Fix R_JR, R_DISP7, and R_CALLR cases.
(md_pcrel_from): This function now gets called. Supply return
value.
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (mips_ip): Capitalize first word of
existing condition code warning, and add condition code
warnings for .ps instructions, and for bc1any[24][tf].
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* lib/gas-defs.exp (run_dump_test): If stderr file is specified
and there was no stderr output, compare anyway (i.e., cause a
test failure).
* gas/mips/mips64-mips3d.s: Add some new instructions to test warnings.
* gas/mips/mips64-mips3d.l: New file.
* gas/mips/mips64-mips3d.d: Use mips64-mips3d.l, and update for
changes to mips64-mips3d.s.
* gas/mips/mips64-mips3d-incl.d: Likewise.
* gas/mips/set-arch.l: New file.
* gas/mips/set-arch.d: Specify set-arch.l as stderr output to check.
* gas/mips/mips5.l: Make error messages match source.
literal_syms): New global variables.
(xtensa_define_label, add_target_symbol, xtensa_find_label,
map_over_defined_symbols, is_loop_target_label,
xtensa_mark_target_fragments, xtensa_move_frag_symbol,
xtensa_move_frag_symbols, defined_symbols, branch_targets): Delete.
(xtensa_begin_directive): Call md_flush_pending_output. Move symbols
from insn_labels to saved_insn_labels when entering a literal region.
(xtensa_end_directive): Call md_flush_pending_output. Restore
insn_labels list when leaving a literal region.
(xtensa_literal_position): Call xtensa_clear_insn_labels.
(xtensa_literal_pseudo): Add check to disallow .literal inside a
literal region. Move insn_labels to saved_insn_labels and then restore
insn_labels on exit.
(xg_add_branch_and_loop_targets): Replace add_target_symbol calls with
code to set is_loop_target or is_branch_target flag on the symbol
(xtensa_create_literal_symbol): Call xtensa_add_literal_sym.
(xtensa_add_literal_sym, xtensa_add_insn_label,
xtensa_clear_insn_labels): New functions.
(xtensa_move_labels): Remove old_frag and old_offset arguments. Add
loops_ok argument. Rewrite to use insn_labels list instead of
calling xtensa_find_label and to check the is_loop_target flag on
symbols when loops_ok is false.
(xtensa_frob_label): Remove call to xtensa_define_label. Add call
to either xtensa_add_literal_sym or xtensa_add_insn_label. Adjust
call to xtensa_move_labels. Propagate is_branch_target and
is_loop_target flags from symbols to frags.
(xtensa_flush_pending_output): Call xtensa_clear_insn_labels.
(md_assemble): Use xtensa_move_labels with loops_ok = FALSE when
aligning a loop instruction. Adjust call to xtensa_move_labels for
aligning entry instructions. Add call to xtensa_clear_insn_labels.
(xtensa_end): Remove call to xtensa_mark_target_fragments.
(xtensa_move_literals): Replace xtensa_move_frag_symbols call with
code to use new literal_syms list.
* config/tc-xtensa.h (xtensa_symfield_type): Add is_loop_target and
is_branch_target flags.
"move_labels" argument and corresponding call to xtensa_move_labels.
(md_assemble): Add a separate call to xtensa_move_labels and remove
argument for call to xtensa_mark_literal_pool_location.
(xtensa_literal_position, xtensa_switch_to_literal_fragment): Fix
calls to xtensa_mark_literal_pool_location.
(xtensa_create_local_symbol): Delete and inline the code into...
(xtensa_create_literal_symbol): ...here.
(xtensa_frob_label): Combine conditionals.
(expression_maybe_register, xtensa_symbol_new_hook,
fix_new_exp_in_seg): Use symbol_get_tc.
ppc_cpu selection rather than replacing.
(ppc_set_cpu): Ignore and preserve PPC_OPCODE_ANY in ppc_cpu.
(md_begin): When PPC_OPCODE_ANY, insert all opcodes in ppc_hash.
(dot_cfi, output_cfi_insn): Handle DW_CFA_GNU_window_save.
(output_cie): Don't use DW_EH_PE_pcrel if neither DIFF_EXPR_OK
nor tc_cfi_emit_pcrel_expr are defined.
(output_fde): Use tc_cfi_emit_pcrel_expr if available and
DIFF_EXPR_OK is not defined.
* config/tc-sparc.h (TARGET_USE_CFIPOP): Define.
(tc_cfi_frame_initial_instructions, tc_regname_to_dw2regnum,
tc_cfi_emit_pcrel_expr): Define.
(sparc_cfi_frame_initial_instructions, sparc_regname_to_dw2regnum,
sparc_cfi_emit_pcrel_expr): New prototypes.
(sparc_cie_data_alignment): New decl.
(DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT): Define.
* config/tc-sparc.c: Include dw2gencfi.h.
(sparc_cie_data_alignment): New variable.
(md_begin): Initialize it.
(sparc_cfi_frame_initial_instructions): New function.
(sparc_regname_to_dw2regnum): Likewise.
(sparc_cfi_emit_pcrel_expr): Likewise.
* doc/as.texinfo: Document .cfi_gnu_window_save.
* config/tc-sparc.c (s_common): Cast last argument to long and
change format string to shut up warning.
testsuite/
* gas/cfi/cfi-sparc-1.s: New test.
* gas/cfi/cfi-sparc-1.d: New test.
* gas/cfi/cfi-sparc64-1.s: New test.
* gas/cfi/cfi-sparc64-1.d: New test.
* gas/cfi/cfi.exp: Run them.
* config/tc-i860.c (i860_check_label): New function.
* config/tc-i860.h (i860_check_label): New prototype.
(tc_check_label): Define macro as i860_check_label.
* config/tc-i860.c (s_align_wrapper): New function and prototype.
(md_pseudo_table): Change s_align_bytes to s_align_wrapper, remove
surrounding OBJ_ELF ifdef, and re-format slightly.
* doc/c-i860.texi: Document the special .align syntax available
in Intel mode.
2003-08-06 Jason Eckhardt <jle@rice.edu>
* config/tc-i860.c (i860_handle_align): New function.
* config/tc-i860.h (HANDLE_ALIGN): Define macro.
(MAX_MEM_FOR_RS_ALIGN_CODE): Define macro.
gas/testsuite:
2003-08-06 Jason Eckhardt <jle@rice.edu>
* gas/i860/dir-align01.{s,d}: New files.
* gas/i860/i860.exp: Execute the new test above.
2003-08-06 Jason Eckhardt <jle@rice.edu>
* config/tc-i860.c (i860_process_insn): Check that instructions
with their dual-bit set are 8-byte aligned.
gas/testsuite:
2003-08-06 Jason Eckhardt <jle@rice.edu>
* gas/i860/dual02-err.l: Update expected error message.
* gas/i860/README.i860: Remove dual02-err from known failure list.
* config/tc-i860.c: Remove SYNTAX_SVR4 macro and occurrences.
(target_intel_syntax): Declare variable.
(OPTION_INTEL_SYNTAX): Declare macro.
(md_longopts): Add option -mintel-syntax.
(md_parse_option): Set target_intel_syntax.
(md_show_usage): Add -mintel-syntax usage.
(md_begin): Set reg_prefix based on target_intel_syntax.
(i860_process_insn): Skip register prefix only if there is one.
Parse relocatable expressions in either Intel or AT&T syntax based
on target_intel_syntax instead of the SYNTAX_SVR4 macro.
* doc/c-i860.texi: Document -mintel-syntax option and give blurb
about the differences in syntax.
2003-07-30 Jason Eckhardt <jle@rice.edu>
* elf32-i860.c: Convert to ISO C90. Remove superflous prototypes.
gas:
2003-07-30 Jason Eckhardt <jle@rice.edu>
* config/tc-i860.c: Convert to ISO C90.
2003-07-25 H.J. Lu <hongjiu.lu@intel.com>
* elf.c (_bfd_elf_new_section_hook): Set the default section
type to SHT_NULL.
(elf_fake_sections): Set the section type based on asect->flags
if it is SHT_NULL. Don't abort on processor specific section
types.
gas/
2003-07-25 H.J. Lu <hongjiu.lu@intel.com>
* config/obj-elf.c (obj_elf_change_section): Update
elf_section_type and elf_section_flags only when they are
specified.
* mips.h (CPU_RM7000): New macro.
(OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns.
bfd/
* archures.c (bfd_mach_mips7000): New.
* bfd-in2.h: Regenerated.
* cpu-mips.c (arch_info_struct): Add an entry for mips:7000.
* elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips7000.
(mips_mach_extensions): Add an entry for it.
opcodes/
* mips-dis.c (mips_arch_choices): Add rm7000 and rm9000 entries.
gas/
* config/tc-mips.c (hilo_interlocks): True for CPU_RM7000.
(mips_cpu_info_table): Add rm7000 and rm9000 entries.
gas/testsuite/
* gas/mips/rm7000.[sd]: New test.
* gas/mips/mips.exp: Run it.
* config/tc-mn10300.c (mn10300_check_fixup): Set GOT_PCREL type
for subtracts from GLOBAL_OFFSET_TABLE that could not be
simplified.
2002-07-18 Alexandre Oliva <aoliva@redhat.com>
* config/tc-mn10300.c (mn10300_check_fixup): Accept subtracts that
could not be simplified.
(tc_gen_reloc): Turn an absolute fx_subsy into part of fx_offset.
2001-11-04 Alexandre Oliva <aoliva@redhat.com>
* config/tc-mn10300.h (TC_RELOC_RTSYM_LOC_FIXUP): Don't adjust
BDF_RELOC_MN10300_GOT32.
* config/tc-mn10300.c (mn10300_fix_adjustable): If
TC_RELOC_RTSYM_LOC_FIXUP doesn't hold, it's not adjustable.
2001-05-09 Alexandre Oliva <aoliva@redhat.com>
* config/tc-mn10300.c (mn10300_parse_name): Don't return a
symbol if we know its value.
2001-05-09 Alexandre Oliva <aoliva@redhat.com>
* config/tc-mn10300.h (GLOBAL_OFFSET_TABLE_NAME): Remove
duplicate underscore prefix.
2001-05-09 Alexandre Oliva <aoliva@redhat.com>
* config/tc-mn10300.c (mn10300_parse_name): Store relocation
type in X_md, not X_add_number. Zero X_add_number.
(mn10300_check_fixup): Extract relocation type from X_md.
* config/tc-mn10300.h: Update comment.
2001-04-14 Alexandre Oliva <aoliva@redhat.com>
* config/tc-mn10300.h (O_GOTOFF, O_PLT, O_GOT): Replace with...
(O_PIC_reloc): this.
* config/tc-mn10300.c (mn10300_PIC_related_p): Use it.
(mn10300_check_fixup): Likewise.
(mn10300_parse_name): Set X_add_number to relocation type.
* config/tc-mn10300.h (DIFF_EXPR_OK, GLOBAL_OFFSET_TABLE_NAME,
TC_RELOC_RTSYM_LOC_FIXUP, md_parse_name, TC_CONS_FIX_NEW,
O_GOTOFF, O_PLT, O_GOT): Define.
* config/tc-mn10300.c (mn10300_PIC_related_p): New fn.
(mn10300_check_fixup): New fn.
(md_assemble): Call it. Check for PIC-related relocs.
(mn10300_cons_fix_new): Likewise. New fn.
(mn10300_end_of_match): New fn.
(mn10300_md_parse_name_cont): New fn.
2003-07-08 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (mips_validate_fix): Do not warn about branch
target being a global symbol if not compiling SVR4 PIC code.
[ gas/testsuite/ChangeLog ]
2003-07-08 Chris Demetriou <cgd@broadcom.com>
* gas/testsuite/gas/mips/mips.exp: Make sure that branch-misc-2 is
run to compile non-PIC code, and add branch-misc-2pic.
* gas/mips/branch-misc-2.l: Adjust for change in non-PIC warnings.
* gas/mips/branch-misc-2pic.l: New file.
* gas/mips/branch-misc-2pic.s: New file.
(DSYMMODE): Remove.
(parse_exp): Replace expressionS argument with a h8_op. Parse the
operand size as well.
(skip_colonthing): Remove unused expression argument. Tighten checks
for 2-digit sizes.
(colonmod24): Remove.
(get_mova_operands): Combine calls to parse_exp and skip_colonthing.
(get_operand): Likewise. Use the standard code to read the size of
pc-relative operands.
(fix_operand_size): Include the size-guessing logic that used to be
in colonmod24 and get_operand. Don't apply dd:2 optimizations to
offsets with a symbolic component.
testsuite/
* gas/h8300/h8sx_disp2.[sd]: Add tests for symbolic displacements.
(md_begin): Add minimal cpu type logic for instructions with different
binary format depending on the cpu.
(md_assemble): Remove check for minimal cpu.
(s390_insert_operand): Add support for long displacements.
(md_gather_operands): Likewise.
(tc_s390_fix_adjustable): Likewise.
(tc_s390_force_relocation): Likewise.
(md_apply_fix3): Likewise.
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (md_assemble): Support Intel Precott New
Instructions.
* gas/config/tc-i386.h (CpuPNI): New.
(CpuUnknownFlags): Add CpuPNI.
gas/testsuite/
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add prescott.
* gas/i386/prescott.d: New file.
* gas/i386/prescott.s: Likewise.
include/opcode/
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Support Intel Precott New Instructions.
opcodes/
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in
Intel Precott New Instructions.
(PREGRP27): New. Added for "addsubpd" and "addsubps".
(PREGRP28): New. Added for "haddpd" and "haddps".
(PREGRP29): New. Added for "hsubpd" and "hsubps".
(PREGRP30): New. Added for "movsldup" and "movddup".
(PREGRP31): New. Added for "movshdup" and "movhpd".
(PREGRP32): New. Added for "lddqu".
(dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry.
Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for
entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for
entry 0xd0. Use PREGRP32 for entry 0xf0.
(twobyte_has_modrm): Updated.
(twobyte_uses_SSE_prefix): Likewise.
(grps): Use PNI_Fixup in the "sidtQ" entry.
(prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30,
PREGRP31 and PREGRP32.
(float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb.
Use "fisttpll" in entry 1 in opcode 0xdd.
Use "fisttp" in entry 1 in opcode 0xdf.
special handling for n32 ABI.
(macro): Likewise.
* gas/mips/elf-rel-got-n32.d: Remove special handling for n32 ABI.
* gas/mips/elf-rel-xgot-n32.d: Likewise.
* gas/mips/jal-newabi.d: Likewise.
* ld-mips-elf/elf-rel-got-n32.d: Remove special handling for n32 ABI.
* ld-mips-elf/elf-rel-xgot-n32.d: Likewise.
now, not only a warning. Add some more checks to detect invalid
registers.
(get_operand): For CLASS_IR remember register size in mode struct.
(get_specific): Handle new CLASS_IRO type. Add register size
checks for CLASS_IR and CLASS_IRO.
(md_apply_fix3): Fix undefined usage of buf.
(FPU_DEFAULT, case TE_NetBSD): Default to FPU_ARCH_VFP for ELF,
FPU_ARCH_FPA for AOUT.
(md_begin): Don't try to guess the floating point architecture from
the CPU if the OS ABI (Linux, NetBSD) mandates a particular form.
(elf_mips_howto_table_rel): Use it.
(gprel32_with_gp): Move prototype.
(mips_elf_hi16_reloc): Check for ! BSF_LOCAL instead of zero addend.
Use mips_elf_generic_reloc.
(mips_elf_got16_reloc): Check for ! BSF_LOCAL instead of zero addend.
Code cleanup.
(_bfd_mips_elf32_gprel16_reloc): Check for ! BSF_LOCAL instead of
zero addend.
(mips_elf_gprel32_reloc): Likewise. Use the same GP assignment logic
as in the other *_gprel*_reloc functions.
(gprel32_with_gp): Handle partial_inplace properly.
(mips32_64bit_reloc): Use mips_elf_generic_reloc.
(mips16_gprel_reloc): Check for ! BSF_LOCAL instead of zero addend.
Do addend handling directly instead of calling
_bfd_mips_elf_gprel16_with_gp. Handle partial_inplace properly.
* elf64-mips.c (mips_elf64_hi16_reloc): Check for ! BSF_LOCAL instead
of zero addend. Handle partial_inplace properly.
(mips_elf64_got16_reloc): Check for ! BSF_LOCAL instead of zero
addend.
(mips_elf64_gprel16_reloc): Likewise.
(mips_elf64_literal_reloc): Likewise.
(mips_elf64_gprel32_reloc): Likewise. Use the same GP assignment
logic as in the other *_gprel*_reloc functions. Handle
partial_inplace properly.
(mips_elf64_shift6_reloc): Check for ! BSF_LOCAL instead of zero
addend. Handle partial_inplace properly.
(mips16_gprel_reloc): Likewise. Do addend handling directly instead
of calling _bfd_mips_elf_gprel16_with_gp.
* elfn32-mips.c (mips_elf_got16_reloc): Check for BSF_LOCAL.
(mips_elf_gprel32_reloc): Check for ! BSF_LOCAL instead
of zero addend.
(mips_elf_shift6_reloc): Handle partial_inplace properly.
(mips16_gprel_reloc): Likewise. Do addend handling directly instead
of calling _bfd_mips_elf_gprel16_with_gp.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Handle
partial_inplace properly. Fix wrong addend handling. Fix overflow
check.
(_bfd_mips_elf_sign_extend): Renamed from mips_elf_sign_extend and
exported.
(mips_elf_calculate_relocation): Use _bfd_mips_elf_sign_extend.
(_bfd_mips_elf_relocate_section): Likewise.
(mips_elf_create_dynamic_relocation): Update sec_info_type access.
* elfxx-mips.h (_bfd_mips_relax_section): Fix prototype declaration.
(_bfd_mips_elf_sign_extend): New prototype.
* config/tc-mips.c (md_pcrel_from): Return actual pcrel address.
(md_apply_fix3): Ignore non-special relocations. Remove superfluous
exceptions from size assert. Remove most of the addend fixup
specialcasing. Remove value, use valP directly. simplify fx_addnumber
handling. Remove zero addend specialcases.
(tc_gen_reloc): Use appropriate value for reloc2 addend. Remove
the addend fixup specialcase.
* config/tc-mips.h (MD_APPLY_SYM_VALUE): Define as 0.
* NEWS: Updated for the new -n option for the i386 assembler.
* config/tc-i386.c (optimize_align_code): New.
(md_shortopts): Add 'n'.
(md_parse_option): Handle 'n'.
(md_show_usage): Add '-n'.
* config/tc-i386.h (optimize_align_code): Declared.
(md_do_align): Optimize code alignment only if optimize_align_code
is not 0.
* doc/as.texinfo: Add the new -n option.
* doc/c-i386.texi: Document the new -n option.
* config/tc-h8sx.c (get_specific): Distinguish h8h from h8s ops.
(build_bytes): Ditto.
2003-06-05 Richard Sandiford <rsandifo@redhat.com>
* config/tc-h8sx.c (DMODE): Remove.
(colonmod24): Don't choose a default if the operand is a 16-bit
constant integer.
(fix_operand_size): New function.
(md_assemble): Use it to choose between @(d:2, ERn) and @(d:16,ERn).
Adjust @(d:2,ERn) operands before choosing the specific opcodes.
From Bernd Schmidt <bernds@redhat.com>
and Michael Snyder <msnyder@redhat.com>
and Alexandre Oliva <aoliva@redhat.com>
* config/tc-h8300.c: Add insns and addressing modes for h8300sx.
* config/tc-h8300.h: Ditto.
fixp's. Don't relax overflow checking for partial_inplace relocations.
Use the actual relocation type in combined relocs, not just the type
of the first one.
(macro_build_jalr): Use actual relocation size for new fix.
(s_cpsetup, s_gpdword): Likewise.
Alexandre Oliva <aoliva@redhat.com>
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Adjust
pic tests, change to warning.
(_bfd_mips_elf_final_link): Remove EF_MIPS_CPIC flag setting.
2003-05-07 Eric Christopher <echristo@redhat.com>
* config/tc-mips.c (mips_abicalls): New variable.
(md_parse_option): Use.
(s_option): Ditto.
(s_abicalls): Ditto.
(mips_elf_final_processing): Set EF_MIPS_PIC and
EF_MIPS_CPIC dependent on above.
