2000-05-25 Alexandre Oliva <aoliva@cygnus.com>
* config/tc-mn10300.c (mn10300_insert_operand): Negate negative accumulator's shift. 2000-05-08 Alexandre Oliva <aoliva@cygnus.com> * config/tc-mn10300.c (md_relax_table, md_convert_frag, md_assemble, md_estimate_size_before_relax): Handle fbCC. 2000-04-20 Alexandre Oliva <aoliva@cygnus.com> * config/tc-mn10300.c (HAVE_AM33): Redefine in terms of HAVE_AM33_2. 2000-04-03 Alexandre Oliva <aoliva@cygnus.com> * config/tc-mn10300.c (md_pseudo_table): Use AM33_2 constant. (HAVE_AM33): Match AM33_2 too. (HAVE_AM33_2): New macro. (md_assemble): Use it. Match 2.0 registers only if HAVE_AM33_2. 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> * config/tc-mn10300.c (md_pseudo_table): Added `am33_2'. (float_registers, double_registers): New variables. (float_register_name, double_register_name): New functions. (md_assemble): Recognize FP registers. Implement FMT_D3. (mn10300_insert_operand): Support FP registers.
This commit is contained in:
Alexandre Oliva
parent
e1f834a331
commit
e7b715256e
2 changed files with 440 additions and 1 deletions
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@ -1,3 +1,26 @@
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2003-07-09 Alexandre Oliva <aoliva@redhat.com>
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2000-05-25 Alexandre Oliva <aoliva@cygnus.com>
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* config/tc-mn10300.c (mn10300_insert_operand): Negate negative
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accumulator's shift.
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2000-05-08 Alexandre Oliva <aoliva@cygnus.com>
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* config/tc-mn10300.c (md_relax_table, md_convert_frag,
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md_assemble, md_estimate_size_before_relax): Handle fbCC.
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2000-04-20 Alexandre Oliva <aoliva@cygnus.com>
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* config/tc-mn10300.c (HAVE_AM33): Redefine in terms of
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HAVE_AM33_2.
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2000-04-03 Alexandre Oliva <aoliva@cygnus.com>
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* config/tc-mn10300.c (md_pseudo_table): Use AM33_2 constant.
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(HAVE_AM33): Match AM33_2 too.
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(HAVE_AM33_2): New macro.
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(md_assemble): Use it. Match 2.0 registers only if HAVE_AM33_2.
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2000-04-01 Alexandre Oliva <aoliva@cygnus.com>
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* config/tc-mn10300.c (md_pseudo_table): Added `am33_2'.
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(float_registers, double_registers): New variables.
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(float_register_name, double_register_name): New functions.
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(md_assemble): Recognize FP registers. Implement FMT_D3.
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(mn10300_insert_operand): Support FP registers.
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2003-07-08 Chris Demetriou <cgd@broadcom.com>
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* config/tc-mips.c (mips_validate_fix): Do not warn about branch
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@ -78,6 +78,11 @@ const relax_typeS md_relax_table[] = {
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{0x7fff, -0x8000, 3, 12},
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{0x7fffffff, -0x80000000, 5, 0},
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/* fbCC relaxing */
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{0x7f, -0x80, 3, 14},
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{0x7fff, -0x8000, 6, 15},
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{0x7fffffff, -0x80000000, 8, 0},
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};
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/* Local functions. */
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@ -127,11 +132,13 @@ const pseudo_typeS md_pseudo_table[] =
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{
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{ "am30", set_arch_mach, AM30 },
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{ "am33", set_arch_mach, AM33 },
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{ "am33_2", (void (*) PARAMS ((int))) set_arch_mach, AM33_2 },
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{ "mn10300", set_arch_mach, MN103 },
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{NULL, 0, 0}
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};
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#define HAVE_AM33 (current_machine == AM33)
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#define HAVE_AM33_2 (current_machine == AM33_2)
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#define HAVE_AM33 (current_machine == AM33 || HAVE_AM33_2)
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#define HAVE_AM30 (current_machine == AM30)
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/* Opcode hash table. */
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@ -251,6 +258,69 @@ static const struct reg_name other_registers[] =
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#define OTHER_REG_NAME_CNT \
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(sizeof (other_registers) / sizeof (struct reg_name))
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static const struct reg_name float_registers[] =
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{
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{ "fs0", 0 },
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{ "fs1", 1 },
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{ "fs10", 10 },
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{ "fs11", 11 },
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{ "fs12", 12 },
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{ "fs13", 13 },
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{ "fs14", 14 },
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{ "fs15", 15 },
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{ "fs16", 16 },
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{ "fs17", 17 },
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{ "fs18", 18 },
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{ "fs19", 19 },
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{ "fs2", 2 },
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{ "fs20", 20 },
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{ "fs21", 21 },
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{ "fs22", 22 },
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{ "fs23", 23 },
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{ "fs24", 24 },
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{ "fs25", 25 },
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{ "fs26", 26 },
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{ "fs27", 27 },
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{ "fs28", 28 },
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{ "fs29", 29 },
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{ "fs3", 3 },
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{ "fs30", 30 },
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{ "fs31", 31 },
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{ "fs4", 4 },
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{ "fs5", 5 },
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{ "fs6", 6 },
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{ "fs7", 7 },
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{ "fs8", 8 },
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{ "fs9", 9 },
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};
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#define FLOAT_REG_NAME_CNT \
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(sizeof (float_registers) / sizeof (struct reg_name))
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static const struct reg_name double_registers[] =
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{
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{ "fd0", 0 },
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{ "fd10", 10 },
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{ "fd12", 12 },
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{ "fd14", 14 },
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{ "fd16", 16 },
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{ "fd18", 18 },
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{ "fd2", 2 },
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{ "fd20", 20 },
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{ "fd22", 22 },
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{ "fd24", 24 },
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{ "fd26", 26 },
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{ "fd28", 28 },
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{ "fd30", 30 },
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{ "fd4", 4 },
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{ "fd6", 6 },
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{ "fd8", 8 },
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};
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#define DOUBLE_REG_NAME_CNT \
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(sizeof (double_registers) / sizeof (struct reg_name))
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/* reg_name_search does a binary search of the given register table
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to see if "name" is a valid regiter name. Returns the register
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number from the array on success, or -1 on failure. */
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@ -518,6 +588,101 @@ other_register_name (expressionP)
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return FALSE;
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}
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static bfd_boolean double_register_name PARAMS ((expressionS *));
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static bfd_boolean float_register_name PARAMS ((expressionS *));
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/* Summary of float_register_name:
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in: Input_line_pointer points to 1st char of operand.
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out: A expressionS.
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The operand may have been a register: in this case, X_op == O_register,
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X_add_number is set to the register number, and truth is returned.
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Input_line_pointer->(next non-blank) char after operand, or is in
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its original state. */
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static bfd_boolean
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float_register_name (expressionP)
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expressionS *expressionP;
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{
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int reg_number;
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char *name;
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char *start;
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char c;
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/* Find the spelling of the operand. */
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start = name = input_line_pointer;
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c = get_symbol_end ();
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reg_number = reg_name_search (float_registers, FLOAT_REG_NAME_CNT, name);
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/* Put back the delimiting char. */
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* input_line_pointer = c;
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/* Look to see if it's in the register table. */
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if (reg_number >= 0)
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{
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expressionP->X_op = O_register;
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expressionP->X_add_number = reg_number;
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/* Make the rest nice. */
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expressionP->X_add_symbol = NULL;
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expressionP->X_op_symbol = NULL;
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return TRUE;
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}
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/* Reset the line as if we had not done anything. */
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input_line_pointer = start;
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return FALSE;
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}
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/* Summary of double_register_name:
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in: Input_line_pointer points to 1st char of operand.
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out: A expressionS.
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The operand may have been a register: in this case, X_op == O_register,
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X_add_number is set to the register number, and truth is returned.
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Input_line_pointer->(next non-blank) char after operand, or is in
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its original state. */
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static bfd_boolean
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double_register_name (expressionP)
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expressionS *expressionP;
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{
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int reg_number;
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char *name;
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char *start;
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char c;
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/* Find the spelling of the operand. */
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start = name = input_line_pointer;
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c = get_symbol_end ();
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reg_number = reg_name_search (double_registers, DOUBLE_REG_NAME_CNT, name);
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/* Put back the delimiting char. */
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* input_line_pointer = c;
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/* Look to see if it's in the register table. */
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if (reg_number >= 0)
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{
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expressionP->X_op = O_register;
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expressionP->X_add_number = reg_number;
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/* Make the rest nice. */
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expressionP->X_add_symbol = NULL;
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expressionP->X_op_symbol = NULL;
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return TRUE;
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}
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/* Reset the line as if we had not done anything. */
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input_line_pointer = start;
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return FALSE;
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}
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void
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md_show_usage (stream)
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FILE *stream;
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@ -865,6 +1030,151 @@ md_convert_frag (abfd, sec, fragP)
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fragP->fr_var = 0;
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fragP->fr_fix += 5;
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}
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else if (fragP->fr_subtype == 13)
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{
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fix_new (fragP, fragP->fr_fix + 2, 1, fragP->fr_symbol,
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fragP->fr_offset + 2, 1, BFD_RELOC_8_PCREL);
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fragP->fr_var = 0;
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fragP->fr_fix += 3;
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}
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else if (fragP->fr_subtype == 14)
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{
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/* Reverse the condition of the first branch. */
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int offset = fragP->fr_fix;
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int opcode = fragP->fr_literal[offset + 1] & 0xff;
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switch (opcode)
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{
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case 0xd0:
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opcode = 0xd1;
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break;
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case 0xd1:
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opcode = 0xd0;
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break;
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case 0xd2:
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opcode = 0xdc;
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break;
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case 0xd3:
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opcode = 0xdb;
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break;
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case 0xd4:
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opcode = 0xda;
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break;
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case 0xd5:
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opcode = 0xd9;
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break;
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case 0xd6:
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opcode = 0xd8;
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break;
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case 0xd7:
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opcode = 0xdd;
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break;
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case 0xd8:
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opcode = 0xd6;
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break;
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case 0xd9:
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opcode = 0xd5;
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break;
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case 0xda:
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opcode = 0xd4;
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break;
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case 0xdb:
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opcode = 0xd3;
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break;
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case 0xdc:
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opcode = 0xd2;
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break;
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case 0xdd:
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opcode = 0xd7;
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break;
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default:
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abort ();
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}
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fragP->fr_literal[offset + 1] = opcode;
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/* Create a fixup for the reversed conditional branch. */
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sprintf (buf, ".%s_%ld", FAKE_LABEL_NAME, label_count++);
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fix_new (fragP, fragP->fr_fix + 2, 1,
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symbol_new (buf, sec, 0, fragP->fr_next),
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fragP->fr_offset + 2, 1, BFD_RELOC_8_PCREL);
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/* Now create the unconditional branch + fixup to the
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final target. */
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fragP->fr_literal[offset + 3] = 0xcc;
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fix_new (fragP, fragP->fr_fix + 4, 2, fragP->fr_symbol,
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fragP->fr_offset + 1, 1, BFD_RELOC_16_PCREL);
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fragP->fr_var = 0;
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fragP->fr_fix += 6;
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}
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else if (fragP->fr_subtype == 15)
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{
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/* Reverse the condition of the first branch. */
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int offset = fragP->fr_fix;
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int opcode = fragP->fr_literal[offset + 1] & 0xff;
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switch (opcode)
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{
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case 0xd0:
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opcode = 0xd1;
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break;
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case 0xd1:
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opcode = 0xd0;
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break;
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case 0xd2:
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opcode = 0xdc;
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break;
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case 0xd3:
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opcode = 0xdb;
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break;
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case 0xd4:
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opcode = 0xda;
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break;
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case 0xd5:
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opcode = 0xd9;
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break;
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case 0xd6:
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opcode = 0xd8;
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break;
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case 0xd7:
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opcode = 0xdd;
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break;
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case 0xd8:
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opcode = 0xd6;
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break;
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case 0xd9:
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opcode = 0xd5;
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||||
break;
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case 0xda:
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opcode = 0xd4;
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||||
break;
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case 0xdb:
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||||
opcode = 0xd3;
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||||
break;
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||||
case 0xdc:
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||||
opcode = 0xd2;
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||||
break;
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case 0xdd:
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opcode = 0xd7;
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||||
break;
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default:
|
||||
abort ();
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}
|
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fragP->fr_literal[offset + 1] = opcode;
|
||||
|
||||
/* Create a fixup for the reversed conditional branch. */
|
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sprintf (buf, ".%s_%ld", FAKE_LABEL_NAME, label_count++);
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fix_new (fragP, fragP->fr_fix + 2, 1,
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symbol_new (buf, sec, 0, fragP->fr_next),
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fragP->fr_offset + 2, 1, BFD_RELOC_8_PCREL);
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||||
|
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/* Now create the unconditional branch + fixup to the
|
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final target. */
|
||||
fragP->fr_literal[offset + 3] = 0xdc;
|
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fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
|
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fragP->fr_offset + 1, 1, BFD_RELOC_32_PCREL);
|
||||
fragP->fr_var = 0;
|
||||
fragP->fr_fix += 8;
|
||||
}
|
||||
else
|
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abort ();
|
||||
}
|
||||
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|
@ -965,6 +1275,7 @@ md_assemble (str)
|
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/* If the instruction is not available on the current machine
|
||||
then it can not possibly match. */
|
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if (opcode->machine
|
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&& !(opcode->machine == AM33_2 && HAVE_AM33_2)
|
||||
&& !(opcode->machine == AM33 && HAVE_AM33)
|
||||
&& !(opcode->machine == AM30 && HAVE_AM30))
|
||||
goto error;
|
||||
|
|
@ -1059,6 +1370,39 @@ md_assemble (str)
|
|||
goto error;
|
||||
}
|
||||
}
|
||||
else if (operand->flags & MN10300_OPERAND_FSREG)
|
||||
{
|
||||
if (!float_register_name (&ex))
|
||||
{
|
||||
input_line_pointer = hold;
|
||||
str = hold;
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
else if (operand->flags & MN10300_OPERAND_FDREG)
|
||||
{
|
||||
if (!double_register_name (&ex))
|
||||
{
|
||||
input_line_pointer = hold;
|
||||
str = hold;
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
else if (operand->flags & MN10300_OPERAND_FPCR)
|
||||
{
|
||||
char *start = input_line_pointer;
|
||||
char c = get_symbol_end ();
|
||||
|
||||
if (strcasecmp (start, "fpcr") != 0)
|
||||
{
|
||||
*input_line_pointer = c;
|
||||
input_line_pointer = hold;
|
||||
str = hold;
|
||||
goto error;
|
||||
}
|
||||
*input_line_pointer = c;
|
||||
goto keep_going;
|
||||
}
|
||||
else if (operand->flags & MN10300_OPERAND_USP)
|
||||
{
|
||||
char *start = input_line_pointer;
|
||||
|
|
@ -1298,6 +1642,18 @@ md_assemble (str)
|
|||
str = hold;
|
||||
goto error;
|
||||
}
|
||||
else if (HAVE_AM33_2 && float_register_name (&ex))
|
||||
{
|
||||
input_line_pointer = hold;
|
||||
str = hold;
|
||||
goto error;
|
||||
}
|
||||
else if (HAVE_AM33_2 && double_register_name (&ex))
|
||||
{
|
||||
input_line_pointer = hold;
|
||||
str = hold;
|
||||
goto error;
|
||||
}
|
||||
else if (*str == ')' || *str == '(')
|
||||
{
|
||||
input_line_pointer = hold;
|
||||
|
|
@ -1324,6 +1680,8 @@ md_assemble (str)
|
|||
mask = MN10300_OPERAND_DREG | MN10300_OPERAND_AREG;
|
||||
if (HAVE_AM33)
|
||||
mask |= MN10300_OPERAND_RREG | MN10300_OPERAND_XRREG;
|
||||
if (HAVE_AM33_2)
|
||||
mask |= MN10300_OPERAND_FSREG | MN10300_OPERAND_FDREG;
|
||||
if ((operand->flags & mask) == 0)
|
||||
{
|
||||
input_line_pointer = hold;
|
||||
|
|
@ -1491,6 +1849,9 @@ keep_going:
|
|||
if (opcode->format == FMT_D2)
|
||||
size = 4;
|
||||
|
||||
if (opcode->format == FMT_D3)
|
||||
size = 5;
|
||||
|
||||
if (opcode->format == FMT_D4)
|
||||
size = 6;
|
||||
|
||||
|
|
@ -1529,6 +1890,8 @@ keep_going:
|
|||
/* jmp */
|
||||
else if (size == 3 && opcode->opcode == 0xcc0000)
|
||||
type = 10;
|
||||
else if (size == 3 && (opcode->opcode & 0xfff000) == 0xf8d000)
|
||||
type = 13;
|
||||
/* bCC (uncommon cases) */
|
||||
else
|
||||
type = 3;
|
||||
|
|
@ -1635,6 +1998,12 @@ keep_going:
|
|||
is really two 8bit immediates. */
|
||||
number_to_chars_bigendian (f, insn, 4);
|
||||
}
|
||||
else if (opcode->format == FMT_D3)
|
||||
{
|
||||
number_to_chars_bigendian (f, (insn >> 16) & 0xffff, 2);
|
||||
number_to_chars_littleendian (f + 2, insn & 0xffff, 2);
|
||||
number_to_chars_bigendian (f + 4, extension & 0xff, 1);
|
||||
}
|
||||
else if (opcode->format == FMT_D4)
|
||||
{
|
||||
unsigned long temp = ((insn & 0xffff) << 16) | (extension & 0xffff);
|
||||
|
|
@ -1897,6 +2266,8 @@ md_estimate_size_before_relax (fragp, seg)
|
|||
|| seg != S_GET_SEGMENT (fragp->fr_symbol)))
|
||||
fragp->fr_subtype = 12;
|
||||
|
||||
if (fragp->fr_subtype == 13)
|
||||
return 3;
|
||||
if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
|
||||
abort ();
|
||||
|
||||
|
|
@ -2075,6 +2446,51 @@ mn10300_insert_operand (insnp, extensionp, operand, val, file, line, shift)
|
|||
*extensionp |= ((val & ((1 << (24 - operand->bits)) - 1))
|
||||
<< operand->shift);
|
||||
}
|
||||
else if ((operand->flags & (MN10300_OPERAND_FSREG | MN10300_OPERAND_FDREG)))
|
||||
{
|
||||
/* See devo/opcodes/m10300-opc.c just before #define FSM0 for an
|
||||
explanation of these variables. Note that FMT-implied shifts
|
||||
are not taken into account for FP registers. */
|
||||
unsigned long mask_low, mask_high;
|
||||
int shl_low, shr_high, shl_high;
|
||||
|
||||
switch (operand->bits)
|
||||
{
|
||||
case 5:
|
||||
/* Handle regular FP registers. */
|
||||
if (operand->shift >= 0)
|
||||
{
|
||||
/* This is an `m' register. */
|
||||
shl_low = operand->shift;
|
||||
shl_high = 8 + (8 & shl_low) + (shl_low & 4) / 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* This is an `n' register. */
|
||||
shl_low = -operand->shift;
|
||||
shl_high = shl_low / 4;
|
||||
}
|
||||
|
||||
mask_low = 0x0f;
|
||||
mask_high = 0x10;
|
||||
shr_high = 4;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
/* Handle accumulators. */
|
||||
shl_low = -operand->shift;
|
||||
shl_high = 0;
|
||||
mask_low = 0x03;
|
||||
mask_high = 0x04;
|
||||
shr_high = 2;
|
||||
break;
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
*insnp |= ((((val & mask_high) >> shr_high) << shl_high)
|
||||
| ((val & mask_low) << shl_low));
|
||||
}
|
||||
else if ((operand->flags & MN10300_OPERAND_EXTENDED) == 0)
|
||||
{
|
||||
*insnp |= (((long) val & ((1 << operand->bits) - 1))
|
||||
|
|
|
|||
Loading…
Reference in a new issue