opcodes:
* ppc-opc.c (MO): Make optional. (RAO, RSO, SHO): New optional forms of RA, RS, SH operands. (tlbwe): Accept for both PPC403 and BOOKE. Make all operands optional. gas: * tc-ppc.c (md_assemble): Rewrite comment about optional operands to indicate that 'all or none' is also handled. Pluralize a word in another comment. gas/testsuite: * gas/ppc/booke.s: Add two more forms of the mbar instruction and three forms of the tlbwe instruction. * gas/ppc/booke.d: Update to match.
This commit is contained in:
Zack Weinberg
parent
7ae4c3a566
commit
1f6c9eb084
7 changed files with 126 additions and 86 deletions
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@ -1,3 +1,9 @@
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2003-12-10 Zack Weinberg <zack@codesourcery.com>
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* tc-ppc.c (md_assemble): Rewrite comment about optional operands
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to indicate that 'all or none' is also handled. Pluralize a
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word in another comment.
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2003-12-10 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (FPU_MAVERICK): Define.
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@ -32,7 +38,7 @@
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2003-12-05 Ricardo Anguiano <anguiano@codesourcery.com>
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Mark Mitchell <mark@codesourcery.com>
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Richard Earnshaw <rearnsha@arm.com>
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Add V6 support.
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* config/tc-arm.c (ARM_EXT_V6): New macro.
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(ARM_ARCH_V6): Likewise.
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@ -96,11 +102,11 @@
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* config/tc-sh.c: Add support for sh4a and no-fpu variants.
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* testsuite/gas/sh/basic.exp: Call tests for sh4a.
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* testsuite/gas/sh/{err-sh4a-fp.s, err-sh4a.s,
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err-sh4al-dsp.s, sh4a-dsp.d, sh4a-dsp.s, sh4a-fp.d,
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* testsuite/gas/sh/{err-sh4a-fp.s, err-sh4a.s,
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err-sh4al-dsp.s, sh4a-dsp.d, sh4a-dsp.s, sh4a-fp.d,
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sh4a-fp.s, sh4a.d, sh4a.s, sh4al-dsp.d, sh4al-dsp.s:
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New files, tests for sh4a and related variants.
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2003-12-05 Michael Snyder <msnyder@redhat.com>
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* config/tc-sh.c (md_show_usage): Mention new -isa options.
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@ -2136,13 +2136,14 @@ md_assemble (str)
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/* PowerPC operands are just expressions. The only real issue is
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that a few operand types are optional. All cases which might use
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an optional operand separate the operands only with commas (in
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some cases parentheses are used, as in ``lwz 1,0(1)'' but such
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cases never have optional operands). There is never more than
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one optional operand for an instruction. So, before we start
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seriously parsing the operands, we check to see if we have an
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optional operand, and, if we do, we count the number of commas to
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see whether the operand should be omitted. */
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an optional operand separate the operands only with commas (in some
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cases parentheses are used, as in ``lwz 1,0(1)'' but such cases never
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have optional operands). Most instructions with optional operands
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have only one. Those that have more than one optional operand can
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take either all their operands or none. So, before we start seriously
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parsing the operands, we check to see if we have optional operands,
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and if we do, we count the number of commas to see which operands
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have been omitted. */
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skip_optional = 0;
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for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
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{
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@ -2178,7 +2179,7 @@ md_assemble (str)
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/* If there are fewer operands in the line then are called
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for by the instruction, we want to skip the optional
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operand. */
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operands. */
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if (opcount < num_operands_expected)
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skip_optional = 1;
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@ -1,3 +1,9 @@
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2003-12-10 Zack Weinberg <zack@codesourcery.com>
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* gas/ppc/booke.s: Add two more forms of the mbar instruction
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and three forms of the tlbwe instruction.
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* gas/ppc/booke.d: Update to match.
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2003-12-10 Paul Brook <paul@codesourcery.com>
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* gas/arm/arm.exp: Add r15-bad.
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@ -95,13 +101,13 @@
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2003-11-14 Nick Clifton <nickc@redhat.com>
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* gas/arm/arm7.d: Pass -D instead of -d to objdump in order to
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display the contents of data fields in the .text section.
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This change is necessary after the addition of arm elf mapping
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symbol support to gas.
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* gas/arm/pic.d: Expect addresses with function name offsets.
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This change is necessary after the addition of arm elf mapping
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symbol support to gas.
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display the contents of data fields in the .text section.
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This change is necessary after the addition of arm elf mapping
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symbol support to gas.
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* gas/arm/pic.d: Expect addresses with function name offsets.
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This change is necessary after the addition of arm elf mapping
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symbol support to gas.
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2003-11-13 Nick Clifton <nickc@redhat.com>
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* gas/arm/mapping.s: New test: Source for ARM ELF mapping
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@ -215,10 +221,10 @@
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* gas/z8k/jr-back.d: New file.
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* gas/z8k/jr-forw.d: New file.
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* gas/z8k/jr-back.s: Fix displacement length. Add some more jumps
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for jr-back.d.
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for jr-back.d.
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* gas/z8k/jr-backf.s: Fix displacement length.
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* gas/z8k/jr-forw.s: Fix displacement length. Add some more jumps
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for jr-forw.d.
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for jr-forw.d.
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* gas/z8k/jr-forwf.s: Fix displacement length.
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* gas/z8k/z8k.exp: Run new tests.
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@ -372,11 +378,11 @@
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2003-09-01 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
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* gas/mips/elf-rel-got-n32.d: Fix ulw and usw patterns for
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little-endian.
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* gas/mips/elf-rel-got-n64.d: Likewise.
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* gas/mips/elf-rel-xgot-n32.d: Likewise.
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* gas/mips/elf-rel-xgot-n64.d: Likewise.
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* gas/mips/elf-rel-got-n32.d: Fix ulw and usw patterns for
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little-endian.
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* gas/mips/elf-rel-got-n64.d: Likewise.
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* gas/mips/elf-rel-xgot-n32.d: Likewise.
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* gas/mips/elf-rel-xgot-n64.d: Likewise.
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2003-08-29 Jakub Jelinek <jakub@redhat.com>
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@ -81,59 +81,64 @@ Disassembly of section \.text:
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dc: 7c 09 56 26 tlbivaxe r9,r10
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e0: 7c 0b 67 24 tlbsx r11,r12
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e4: 7c 0d 77 26 tlbsxe r13,r14
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e8: 7c 00 07 a4 tlbwe
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ec: 7c 00 07 a4 tlbwe
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f0: 7c 21 0f a4 tlbwe r1,r1,1
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0+00000e8 <branch_target_7>:
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e8: 7c 22 1b 14 adde64 r1,r2,r3
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ec: 7c 85 37 14 adde64o r4,r5,r6
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f0: 7c e8 03 d4 addme64 r7,r8
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f4: 7d 2a 07 d4 addme64o r9,r10
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f8: 7d 6c 03 94 addze64 r11,r12
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fc: 7d ae 07 94 addze64o r13,r14
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100: 7e 80 04 40 mcrxr64 cr5
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104: 7d f0 8b 10 subfe64 r15,r16,r17
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108: 7e 53 a7 10 subfe64o r18,r19,r20
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10c: 7e b6 03 d0 subfme64 r21,r22
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110: 7e f8 07 d0 subfme64o r23,r24
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114: 7f 3a 03 90 subfze64 r25,r26
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118: 7f 7c 07 90 subfze64o r27,r28
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0+00000f4 <branch_target_7>:
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f4: 7c 22 1b 14 adde64 r1,r2,r3
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f8: 7c 85 37 14 adde64o r4,r5,r6
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fc: 7c e8 03 d4 addme64 r7,r8
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100: 7d 2a 07 d4 addme64o r9,r10
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104: 7d 6c 03 94 addze64 r11,r12
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108: 7d ae 07 94 addze64o r13,r14
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10c: 7e 80 04 40 mcrxr64 cr5
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110: 7d f0 8b 10 subfe64 r15,r16,r17
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114: 7e 53 a7 10 subfe64o r18,r19,r20
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118: 7e b6 03 d0 subfme64 r21,r22
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11c: 7e f8 07 d0 subfme64o r23,r24
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120: 7f 3a 03 90 subfze64 r25,r26
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124: 7f 7c 07 90 subfze64o r27,r28
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0+000011c <branch_target_8>:
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11c: e8 22 03 28 stbe r1,50\(r2\)
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120: e8 64 02 89 stbue r3,40\(r4\)
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124: 7c a6 39 fe stbuxe r5,r6,r7
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128: 7d 09 51 be stbxe r8,r9,r10
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12c: 7d 6c 6b ff stdcxe\. r11,r12,r13
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130: f9 cf 00 78 stde r14,28\(r15\)
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134: fa 11 00 59 stdue r16,20\(r17\)
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138: 7e 53 a7 3e stdxe r18,r19,r20
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13c: 7e b6 bf 7e stduxe r21,r22,r23
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140: f8 38 00 3e stfde f1,12\(r24\)
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144: f8 59 00 0f stfdue f2,0\(r25\)
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148: 7c 7a dd be stfdxe f3,r26,r27
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14c: 7c 9c ed fe stfduxe f4,r28,r29
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150: 7c be ff be stfiwxe f5,r30,r31
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154: f8 de 00 6c stfse f6,24\(r30\)
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158: f8 fd 00 5d stfsue f7,20\(r29\)
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15c: 7d 1c dd 3e stfsxe f8,r28,r27
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160: 7d 3a cd 7e stfsuxe f9,r26,r25
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164: 7f 17 b7 3c sthbrxe r24,r23,r22
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168: ea b4 01 ea sthe r21,30\(r20\)
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16c: ea 72 02 8b sthue r19,40\(r18\)
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170: 7e 30 7b 7e sthuxe r17,r16,r15
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174: 7d cd 63 3e sthxe r14,r13,r12
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178: 7d 6a 4d 3c stwbrxe r11,r10,r9
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17c: 7d 07 31 3d stwcxe\. r8,r7,r6
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180: e8 a4 03 2e stwe r5,50\(r4\)
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184: e8 62 02 8f stwue r3,40\(r2\)
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188: 7c 22 19 7e stwuxe r1,r2,r3
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18c: 7c 85 31 3e stwxe r4,r5,r6
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190: 4c 00 00 66 rfci
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194: 7c 60 01 06 wrtee r3
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198: 7c 00 81 46 wrteei 1
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19c: 7c 85 02 06 mfdcrx r4,r5
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1a0: 7c aa 3a 86 mfdcr r5,234
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1a4: 7c e6 03 06 mtdcrx r6,r7
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1a8: 7d 10 6b 86 mtdcr 432,r8
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1ac: 7c 00 04 ac msync
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1b0: 7c 09 55 ec dcba r9,r10
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1b4: 7c 00 06 ac mbar 0
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0+0000128 <branch_target_8>:
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128: e8 22 03 28 stbe r1,50\(r2\)
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12c: e8 64 02 89 stbue r3,40\(r4\)
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130: 7c a6 39 fe stbuxe r5,r6,r7
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134: 7d 09 51 be stbxe r8,r9,r10
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138: 7d 6c 6b ff stdcxe\. r11,r12,r13
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13c: f9 cf 00 78 stde r14,28\(r15\)
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140: fa 11 00 59 stdue r16,20\(r17\)
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144: 7e 53 a7 3e stdxe r18,r19,r20
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148: 7e b6 bf 7e stduxe r21,r22,r23
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14c: f8 38 00 3e stfde f1,12\(r24\)
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150: f8 59 00 0f stfdue f2,0\(r25\)
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154: 7c 7a dd be stfdxe f3,r26,r27
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158: 7c 9c ed fe stfduxe f4,r28,r29
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15c: 7c be ff be stfiwxe f5,r30,r31
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160: f8 de 00 6c stfse f6,24\(r30\)
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164: f8 fd 00 5d stfsue f7,20\(r29\)
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168: 7d 1c dd 3e stfsxe f8,r28,r27
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16c: 7d 3a cd 7e stfsuxe f9,r26,r25
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170: 7f 17 b7 3c sthbrxe r24,r23,r22
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174: ea b4 01 ea sthe r21,30\(r20\)
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178: ea 72 02 8b sthue r19,40\(r18\)
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17c: 7e 30 7b 7e sthuxe r17,r16,r15
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180: 7d cd 63 3e sthxe r14,r13,r12
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184: 7d 6a 4d 3c stwbrxe r11,r10,r9
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188: 7d 07 31 3d stwcxe\. r8,r7,r6
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18c: e8 a4 03 2e stwe r5,50\(r4\)
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190: e8 62 02 8f stwue r3,40\(r2\)
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194: 7c 22 19 7e stwuxe r1,r2,r3
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198: 7c 85 31 3e stwxe r4,r5,r6
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19c: 4c 00 00 66 rfci
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1a0: 7c 60 01 06 wrtee r3
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1a4: 7c 00 81 46 wrteei 1
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1a8: 7c 85 02 06 mfdcrx r4,r5
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1ac: 7c aa 3a 86 mfdcr r5,234
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1b0: 7c e6 03 06 mtdcrx r6,r7
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1b4: 7d 10 6b 86 mtdcr 432,r8
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1b8: 7c 00 04 ac msync
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1bc: 7c 09 55 ec dcba r9,r10
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1c0: 7c 00 06 ac mbar
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1c4: 7c 00 06 ac mbar
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1c8: 7c 20 06 ac mbar 1
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@ -72,6 +72,9 @@ branch_target_6:
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tlbivaxe 9, 10
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tlbsx 11, 12
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tlbsxe 13, 14
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tlbwe
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tlbwe 0,0,0
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tlbwe 1,1,1
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branch_target_7:
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adde64 1, 2, 3
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@ -128,4 +131,6 @@ branch_target_8:
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mtdcr 432, 8
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msync
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dcba 9, 10
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mbar
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mbar 0
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mbar 1
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@ -1,3 +1,9 @@
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2003-12-10 Zack Weinberg <zack@codesourcery.com>
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* ppc-opc.c (MO): Make optional.
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(RAO, RSO, SHO): New optional forms of RA, RS, SH operands.
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(tlbwe): Accept for both PPC403 and BOOKE. Make all operands optional.
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2003-12-05 Ricardo Anguiano <anguiano@codesourcery.com>
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Mark Mitchell <mark@codesourcery.com>
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Richard Earnshaw <rearnsha@arm.com>
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@ -344,7 +344,7 @@ const struct powerpc_operand powerpc_operands[] =
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/* The MO field in an mbar instruction. */
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#define MO MB6 + 1
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{ 5, 21, 0, 0, 0 },
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{ 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
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/* The NB field in an X form instruction. The value 32 is stored as
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0. */
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@ -384,8 +384,12 @@ const struct powerpc_operand powerpc_operands[] =
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#define RAS RAM + 1
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{ 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
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/* The RA field of the tlbwe instruction, which is optional. */
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#define RAO RAS + 1
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{ 5, 16, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
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/* The RB field in an X, XO, M, or MDS form instruction. */
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#define RB RAS + 1
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#define RB RAO + 1
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#define RB_MASK (0x1f << 11)
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{ 5, 11, 0, 0, PPC_OPERAND_GPR },
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@ -413,8 +417,12 @@ const struct powerpc_operand powerpc_operands[] =
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#define RTQ RSQ + 1
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{ 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
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/* The RS field of the tlbwe instruction, which is optional. */
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#define RSO RTQ + 1
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{ 5, 21, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
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/* The SH field in an X or M form instruction. */
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#define SH RTQ + 1
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#define SH RSO + 1
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#define SH_MASK (0x1f << 11)
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{ 5, 11, 0, 0, 0 },
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@ -423,8 +431,12 @@ const struct powerpc_operand powerpc_operands[] =
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#define SH6_MASK ((0x1f << 11) | (1 << 1))
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{ 6, 1, insert_sh6, extract_sh6, 0 },
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/* The SH field of the tlbwe instruction, which is optional. */
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#define SHO SH6 + 1
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{ 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
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/* The SI field in a D form instruction. */
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#define SI SH6 + 1
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#define SI SHO + 1
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{ 16, 0, 0, 0, PPC_OPERAND_SIGNED },
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/* The SI field in a D form instruction when we accept a wide range
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@ -4256,8 +4268,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
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{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
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{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
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{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
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{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAO, SHO } },
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{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
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{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
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Loading…
Reference in a new issue