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* config/tc-a29k.h: Fix comment typos.

Browse source 
* config/tc-alpha.c: Likewise.
	* config/tc-alpha.h: Likewise.
	* config/tc-arc.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-arm.h: Likewise.
	* config/tc-cris.c: Likewise.
	* config/tc-d10v.c: Likewise.
	* config/tc-d30v.c: Likewise.
	* config/tc-dlx.c: Likewise.
	* config/tc-dlx.h: Likewise.
This commit is contained in:
Kazu Hirata 2003-11-21 00:24:40 +00:00
parent 2d8c1c6261
commit 2d2255b58e
11 changed files with 33 additions and 33 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
gas/config/tc-a29k.h
View file

@ -40,7 +40,7 @@ extern int a29k_unrecognized_line PARAMS ((int));
#define BFD_ARCH bfd_arch_a29k
#define COFF_MAGIC SIPFBOMAGIC
/* Should the reloc be output ?
on the 29k, this is true only if there is a symbol attatched.
on the 29k, this is true only if there is a symbol attached.
on the h8, this is allways true, since no fixup is done
*/
#define TC_COUNT_RELOC(x) (x->fx_addsy)

8
gas/config/tc-alpha.c
View file

@ -533,7 +533,7 @@ static const int alpha_num_reloc_op
/* Maximum # digits needed to hold the largest sequence # */
#define ALPHA_RELOC_DIGITS 25
/* Structure to hold explict sequence information. */
/* Structure to hold explicit sequence information. */
struct alpha_reloc_tag
{
fixS *master; /* the literal reloc */
@ -1727,7 +1727,7 @@ alpha_adjust_relocs (abfd, sec, ptr)
if (! seginfo->fix_root)
return;
/* First rebuild the fixup chain without the expicit lituse and
/* First rebuild the fixup chain without the explicit lituse and
gpdisp_lo16 relocs. */
prevP = &seginfo->fix_root;
for (fixp = seginfo->fix_root; fixp; fixp = next)
@ -3014,7 +3014,7 @@ add_to_link_pool (basesym, sym, addend)
but this is what OSF/1 does.
If explicit relocations of the form !literal!<number> are allowed,
and used, then explict_reloc with be an expression pointer.
and used, then explicit_reloc with be an expression pointer.
Finally, the return value is nonzero if the calling macro may emit
a LITUSE reloc if otherwise appropriate; the return value is the
@ -3365,7 +3365,7 @@ load_expression (targreg, exp, pbasereg, poffset)
}
/* The lda macro differs from the lda instruction in that it handles
most simple expressions, particualrly symbol address loads and
most simple expressions, particularly symbol address loads and
large constants. */
static void

2
gas/config/tc-alpha.h
View file

@ -110,7 +110,7 @@ extern int alpha_elf_section_letter PARAMS ((int, char **));
extern flagword alpha_elf_section_flags PARAMS ((flagword, int, int));
#endif
/* Whether to add support for explict !relocation_op!sequence_number. At the
/* Whether to add support for explicit !relocation_op!sequence_number. At the
moment, only do this for ELF, though ECOFF could use it as well. */
#ifdef OBJ_ELF

2
gas/config/tc-arc.c
View file

@ -1832,7 +1832,7 @@ get_arc_exp_reloc_type (data_p, default_type, exp, expnew)
expressionS *expnew;
{
/* If the expression is "symbol >> 2" we must change it to just "symbol",
as fix_new_exp can't handle it. Similarily for (symbol - symbol) >> 2.
as fix_new_exp can't handle it. Similarly for (symbol - symbol) >> 2.
That's ok though. What's really going on here is that we're using
">> 2" as a special syntax for specifying BFD_RELOC_ARC_B26. */

24
gas/config/tc-arm.c
View file

@ -362,7 +362,7 @@ struct asm_psr
unsigned long field;
};
/* The bit that distnguishes CPSR and SPSR. */
/* The bit that distinguishes CPSR and SPSR. */
#define SPSR_BIT (1 << 22)
/* How many bits to shift the PSR_xxx bits up by. */
@ -2597,7 +2597,7 @@ validate_immediate (val)
return FAIL;
}
/* Check to see if an immediate can be computed as two seperate immediate
/* Check to see if an immediate can be computed as two separate immediate
values, added together. We already know that this value cannot be
computed by just one ARM instruction. */
@ -3899,12 +3899,12 @@ do_mrs (str)
if ( strcmp (str, "CPSR") == 0
|| strcmp (str, "SPSR") == 0
/* Lower case versions for backwards compatability. */
/* Lower case versions for backwards compatibility. */
|| strcmp (str, "cpsr") == 0
|| strcmp (str, "spsr") == 0)
skip = 4;
/* This is for backwards compatability with older toolchains. */
/* This is for backwards compatibility with older toolchains. */
else if ( strcmp (str, "cpsr_all") == 0
|| strcmp (str, "spsr_all") == 0)
skip = 8;
@ -4522,7 +4522,7 @@ do_clz (str)
/* ARM V5 (argument parse)
LDC2{L} <coproc>, <CRd>, <addressing mode>
STC2{L} <coproc>, <CRd>, <addressing mode>
Instruction is not conditional, and has 0xf in the codition field.
Instruction is not conditional, and has 0xf in the condition field.
Otherwise, it's the same as LDC/STC. */
static void
@ -5892,7 +5892,7 @@ decode_shift (str, unrestrict)
}
/* Do those data_ops which can take a negative immediate constant
by altering the instuction. A bit of a hack really.
by altering the instruction. A bit of a hack really.
MOV <-> MVN
AND <-> BIC
ADC <-> SBC
@ -9805,7 +9805,7 @@ do_mav_ldst (str, reg0)
if (negative)
offset = -offset;
else
inst.instruction |= CP_T_UD; /* Postive, so set bit U. */
inst.instruction |= CP_T_UD; /* Positive, so set bit U. */
inst.instruction |= offset >> 2;
end_of_line (str);
@ -9925,7 +9925,7 @@ find_real_start (symbolP)
const char * name = S_GET_NAME (symbolP);
symbolS * new_target;
/* This definiton must agree with the one in gcc/config/arm/thumb.c. */
/* This definition must agree with the one in gcc/config/arm/thumb.c. */
#define STUB_NAME ".real_start_of"
if (name == NULL)
@ -10872,8 +10872,8 @@ md_pcrel_from (fixP)
}
#ifdef TE_WINCE
/* The pattern was adjusted to accomodate CE's off-by-one fixups,
so we un-adjust here to compensate for the accomodation. */
/* The pattern was adjusted to accommodate CE's off-by-one fixups,
so we un-adjust here to compensate for the accommodation. */
return fixP->fx_where + fixP->fx_frag->fr_address + 8;
#else
return fixP->fx_where + fixP->fx_frag->fr_address;
@ -11238,7 +11238,7 @@ md_apply_fix3 (fixP, valP, seg)
the absolute address that is the destination of the branch in the
24 bits of the branch instruction. If however, we happen to know
that the destination of the branch is in the same section as the
branch instruciton itself, then we can compute the relocation for
branch instruction itself, then we can compute the relocation for
ourselves and not have to bother the linker with it.
FIXME: The tests for OBJ_ELF and ! target_oabi are only here
@ -13097,7 +13097,7 @@ arm_frag_align_code (n, max)
{
char * p;
/* We assume that there will never be a requirment
/* We assume that there will never be a requirement
to support alignments greater than 32 bytes. */
if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));

2
gas/config/tc-arm.h
View file

@ -137,7 +137,7 @@ bfd_boolean arm_fix_adjustable PARAMS ((struct fix *));
#define ARM_RESET_FLAG(s,v) (*symbol_get_tc (s) &= ~(v))
#define ARM_FLAG_THUMB (1 << 0) /* The symbol is a Thumb symbol rather than an Arm symbol. */
#define ARM_FLAG_INTERWORK (1 << 1) /* The symbol is attached to code that suppports interworking. */
#define ARM_FLAG_INTERWORK (1 << 1) /* The symbol is attached to code that supports interworking. */
#define THUMB_FLAG_FUNC (1 << 2) /* The symbol is attached to the start of a Thumb function. */
#define ARM_IS_THUMB(s) (ARM_GET_FLAG (s) & ARM_FLAG_THUMB)

6
gas/config/tc-cris.c
View file

@ -232,7 +232,7 @@ const char FLT_CHARS[] = "";
#define STATE_UNDF (3)
#define STATE_MAX_LENGTH (3)
/* These displacements are relative to the adress following the opcode
/* These displacements are relative to the address following the opcode
word of the instruction. The first letter is Byte, Word. The 2nd
letter is Forward, Backward. */
@ -971,7 +971,7 @@ md_assemble (str)
{
if (output_instruction.imm_oprnd_size > 0)
{
/* The intruction has an immediate operand. */
/* The instruction has an immediate operand. */
enum bfd_reloc_code_real reloc = BFD_RELOC_NONE;
switch (output_instruction.imm_oprnd_size)
@ -2109,7 +2109,7 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
advanced to the character following the indirect operand on success, or
has an unspecified value on failure.
cPP Pointer to pointer to string begining
cPP Pointer to pointer to string beginning
with the operand
prefixp Pointer to structure containing an

4
gas/config/tc-d10v.c
View file

@ -635,7 +635,7 @@ build_insn (opcode, opers, insn)
if (AT_WORD_P (&opers[i]))
{
/* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
/* Recognize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
opers[i].X_op = O_symbol;
opers[i].X_op_symbol = NULL; /* Should free it. */
@ -1554,7 +1554,7 @@ find_opcode (opcode, myops)
break;
}
/* Unfortunatly, for the indirect operand in instructions such
/* Unfortunately, for the indirect operand in instructions such
as ``ldb r1, @(c,r14)'' this function can be passed
X_op == O_register (because 'c' is a valid register name).
However we cannot just ignore the case when X_op == O_register

8
gas/config/tc-d30v.c
View file

@ -101,7 +101,7 @@ static int d30v_current_align;
static segT d30v_current_align_seg;
/* The last seen label in the current section. This is used to auto-align
labels preceeding instructions. */
labels preceding instructions. */
static symbolS *d30v_last_label;
/* Two nops. */
@ -796,7 +796,7 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
return 1;
}
/* Note: we do not have to worry about subroutine calls occuring
/* Note: we do not have to worry about subroutine calls occurring
in the right hand container. The return address is always
aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
switch (exec_type)
@ -1564,7 +1564,7 @@ do_assemble (str, opcode, shortp, is_parallel)
insn = build_insn (opcode, myops);
/* Propigate multiply status. */
/* Propagate multiply status. */
if (insn != -1)
{
if (is_parallel && prev_mul32_p)
@ -2109,7 +2109,7 @@ d30v_align (n, pfill, label)
/* Do not assume that if 'd30v_current_align >= n' and
'! switched_seg_p' that it is safe to avoid performing
this alignement request. The alignment of the current frag
this alignment request. The alignment of the current frag
can be changed under our feet, for example by a .ascii
directive in the source code. cf testsuite/gas/d30v/reloc.s */
d30v_cleanup (FALSE);

6
gas/config/tc-dlx.c
View file

@ -631,7 +631,7 @@ dlx_parse_loadop (str)
imm[m2] = '\0';
/* Assemble the instruction to gas intrernal format. */
/* Assemble the instruction to gas internal format. */
for (i = 0; rd[i] != '\0'; i++)
iBuf[i] = rd[i];
@ -754,7 +754,7 @@ dlx_parse_storeop (str)
imm[i] = '\0';
/* Assemble the instruction to gas intrernal format. */
/* Assemble the instruction to gas internal format. */
for (i = 0; rd[i] != '\0'; i++)
iBuf[i] = rd[i];
iBuf[i++] = ',';
@ -1304,7 +1304,7 @@ md_undefined_symbol (name)
/* Parse an operand that is machine-specific, the function was called
in expr.c by operand() function, when everything failed bdfore it
in expr.c by operand() function, when everything failed before it
call a quit. */
void

2
gas/config/tc-dlx.h
View file

@ -63,7 +63,7 @@ extern int dlx_unrecognized_line PARAMS ((int));
#define BFD_ARCH bfd_arch_dlx
#define COFF_MAGIC DLXMAGIC
/* Should the reloc be output ?
on the 29k, this is true only if there is a symbol attatched.
on the 29k, this is true only if there is a symbol attached.
on the h8, this is allways true, since no fixup is done
on dlx, I have no idea!! but lets keep it here just for fun.
*/