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Author SHA1 Message Date
Frank Ch. Eigler
6b0c51c929 * You bop one on the head ... another one appears. 
Wed Apr 1 08:20:31 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
 1998-04-01 13:19:07 +00:00
Frank Ch. Eigler
6ed00b0607 * Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide 
128-bit MIPS part.

[ChangeLog]

Mon Mar 30 18:41:43 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* interp.c (decode_coproc): Continuing COP2 work.
  	(cop_[ls]q): Hide 128-bit COP2 more.

	* sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more.

[ChangeLog.sky]

Mon Mar 30 18:44:15 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* sky-libvpe.c: Code too wide - ran indent on SCEI code.

	* sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2
 	interface.

	* sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
 1998-03-30 23:56:52 +00:00
Gavin Romig-Koch
34f51d8723 * configure.in (mipstx39*-*-*): Use gencode simulator rather 
than igen one.
	* configure : Rebuild.
 1998-03-30 19:54:15 +00:00
Frank Ch. Eigler
7dd4a46650 * Oops, added #ifdef TARGET_SKY around R5900 COP2 implementation skeleton. 1998-03-29 22:53:31 +00:00
Frank Ch. Eigler
15232df4a3 * Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code 
into single PKE-style vu.[ch].


[ChangeLog]

Fri Mar 27 16:19:29 1998  Frank Ch. Eigler  <fche@cygnus.com>

start-sanitize-sky
	* Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.

	* interp.c (sim_{load,store}_register): Use new vu[01]_device
 	static to access VU registers.
	(decode_coproc): Added skeleton of sky COP2 (VU) instruction
 	decoding.  Work in progress.

	* mips.igen (LDCzz, SDCzz): Removed *5900 case for this
 	overlapping/redundant bit pattern.
	(LQC2, SQC2): Added *5900 COP2 instruction skeleta.  Work in
	progress.

	* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
 	status register.

end-sanitize-sky

	* interp.c (cop_lq, cop_sq): New functions for future 128-bit
 	access to coprocessor registers.

	* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.

[ChangeLog.sky]

	* sky-engine.c (engine_run): Adapted from vu[01] -> vu merge.

	* sky-hardware.c (register_devices): Ditto

	* sky-pke.c (pke_fifo_*): Made these functions private again, now
 	that the GPUIF code does not use them.

	* sky-pke.h (pke_fifo_*): Removed newly private declarations.

	* sky-vu.c (*): Major rework: merge of old sky-vu0.c and
 	sky-vu1.c.  Management of two VU devices parallels two PKEs.
	Work in progress.

	* sky-vu.h (*): Other half of merge.
	(vu_device): New struct, parallel to pke_device.
 1998-03-27 22:00:56 +00:00
Andrew Cagney
d8f5304972 Do top level sim-hw module for device tree. 
Add to aclocal.m4, update all configure files.
 1998-03-27 11:42:16 +00:00
Andrew Cagney
82ea14fd9d Define CPU_INDEX. Initialize. 
For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
 1998-03-27 04:25:45 +00:00
Andrew Cagney
d89fa2d80a Re-do --enable-sim-hardware so that each simulator can specify the devices 
it wants built.
Generate hw-config.h.
 1998-03-25 01:41:33 +00:00
Andrew Cagney
612a649eee * interp.c (Max, Min): Comment out functions. Not yet used. 
* vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
 1998-03-24 23:16:57 +00:00
Frank Ch. Eigler
9b23b76d68 * Added --with-sim-gpu2=<path> option for linking SCEI's GPU2 library with 
the stand-alone executable.


[in ChangeLog.sky:]

	* sky-gpuif.c (call_gs): Call properly into GPU2 library if
 	configured --with-sim-gpu2.  Use SKY_GPU2_REFRESH symbol as
 	placeholder for future GPU2-refresh policy.

[in ChangeLog:]

	* Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 	configurable settings for stand-alone simulator.

start-sanitize-sky
	* configure.in: Added --with-sim-gpu2 option to specify path of
 	sky GPU2 library.  Triggers -DSKY_GPU2 for sky-gpuif.c, and
 	links/compiles stand-alone simulator with this library.

	* interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
end-sanitize-sky

	* configure.in: Added X11 search, just in case.

	* configure: Regenerated.
 1998-03-18 00:20:40 +00:00
Gavin Romig-Koch
5fa71251a0 * vr4320.igen (clz,dclz) : Added. 
(dmac): Replaced 99, with LO.
 1998-03-10 15:37:24 +00:00
Andrew Cagney
6ba4c1539f Fix opcode fields in SHFL.* 1998-03-05 21:32:31 +00:00
Gavin Romig-Koch
dd15abd5a6 * vr4320.igen: New file. 
* Makefile.in (vr4320.igen) : Added.
	* configure.in (mips64vr4320-*-*): Added.
	* configure : Rebuilt.
	* mips.igen : Correct the bfd-names in the mips-ISA model entries.
	Add the vr4320 model entry and mark the vr4320 insn as necessary.
 1998-03-03 17:03:57 +00:00
Andrew Cagney
ca6f76d135 Fix DIV, DIV1 (wrong check for overflow) and DIVU1 (shouldn't check 
for overflow).
Pacify GCC.
 1998-03-03 05:39:49 +00:00
Andrew Cagney
0e701ac37b Add generic sim-info.c:sim_info() function using module mechanism. 
Clean up compile probs in mips/vr5400.
 1998-02-28 02:51:06 +00:00
Doug Evans
7c5d88c1bb * interp.c (DECLARE_OPTION_HANDLER): Use it. 
(mips_option_handler): New argument `cpu'.
	(sim_open): Update call to sim_add_option_table.
 1998-02-28 02:43:31 +00:00
Andrew Cagney
f89c0689a1 Finish implementation of r5900 instructions. 1998-02-25 15:31:15 +00:00
Andrew Cagney
d3e1d59414 Add tracing to r5900 p* instructions. 1998-02-24 03:42:27 +00:00
Andrew Cagney
a48e8c8d21 sim-main.h: Re-arange r5900 registers so that they have their own 
little struct.
interp.c: Update.  Also add floating point Max/Min functions.
mips.igen: Remove r5900 tag from any floating point instructions.
r5900.igen: Rewrite.  Implement *all* floating point insns (except ld/st).
r5400.igen: Tag mdmx functions as being mdmx specific.
 1998-02-23 16:55:38 +00:00
Gavin Romig-Koch
f319bab251 * interp.c (load_memory): Add missing "break"'s. 1998-02-19 15:24:10 +00:00
Andrew Cagney
452b380811 Fix double dependency for itable.[hc]. Was causing both the mips16 and the 
normal mips simulators to be built.
 1998-02-07 06:24:51 +00:00
Andrew Cagney
37379a256b IGEN - Replace IMEM (IMEM_IMMED) macro with IMEM<insn-size> macro, 
update v850, tic80 and mips simulators.
IGEN - Prepend prefix to more generated symbols and macros
(idecode_issue, instruction_word).
IGEN - Add -Wnowith option to supress warnings about word size
inflicts in input files.
MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so
that a mips16 simulator built using IGEN can be compiled.
 1998-02-03 05:39:15 +00:00
Andrew Cagney
a97f304b04 Add support for configuring the size of the floating point unit (fp_word). 
For mips, move fp_registers into a separate array of type fp_word[].
 1998-02-02 14:06:52 +00:00
Andrew Cagney
2acd126a47 Rewrite the mipsI/II/III pending-slot code. 1998-02-02 13:49:17 +00:00
Andrew Cagney
192ae475f9 Always compile FP code (test for FP at run-time). 
Remove dependance of interp.c on gencode.c's output.
 1998-02-02 08:25:33 +00:00
Andrew Cagney
01737f42d8 mips: Add multi-processor support for r5900. Others might work. 
common, igen: Fix MP related bugs.
 1998-02-01 03:29:48 +00:00
Andrew Cagney
412c4e940e Add config support for the size of the target address and OF cell. 1998-01-31 14:07:23 +00:00
Andrew Cagney
c4db5b04f8 mips - for r5900 generate igen simulator. 
igen - stop crash when simulator isn't multi-sim'ed
 1998-01-31 06:56:13 +00:00
Andrew Cagney
9ec6741b17 igen: Fix SMP simulator generator support. 
Use the bfd-processor name in the sim-engine switch.
	Add nr_cpus argument to sim_engine_run.
tic80, v850, d30v, mips, common:
	Update
mips:	Fill in bfd-processor field of model records so that
	they match ../bfd/archures.
 1998-01-31 06:23:41 +00:00
Andrew Cagney
2d44e12a27 Use macro GPR_SET(N,VAL) to clear zero registers. 1998-01-21 22:08:37 +00:00
Doug Evans
462cfbc4eb * aclocal.m4: Recognize --enable-maintainer-mode. 
*/configure: Regenerated.
 1998-01-20 06:37:00 +00:00
Mark Alexander
e0e0fc765e * interp.c (sim_monitor): Handle Densan monitor outbyte 
and inbyte functions.
 1998-01-05 23:43:30 +00:00
Felix Lee
76ef416550 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). 1997-12-29 16:03:23 +00:00
Andrew Cagney
9c8ec16d78 In nrun.c, look for sigaction & SA_RESTART. When both present, 
install cntrl-c (SIGINT) handler with no SA_RESTART bit set.
 1997-12-15 12:33:59 +00:00
Andrew Cagney
b17d2d1474 For MADD et.al. instructions sign extend 32 bit result assigned to a 
register.
 1997-12-13 04:23:31 +00:00
Jeff Law
255cbbf190 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or 
vr5400 with the vr5000 as the default.
 1997-12-12 19:24:34 +00:00
Jeff Law
23850e9219 * mips.igen (MSUB): Fix to work like MADD. 
* gencode.c (MSUB): Similarly.
 1997-12-11 00:11:04 +00:00
Andrew Cagney
c02ed6a8a3 For bfd, add vr5400 and vr5000 mips machine variants to list of machines. 
For sim/mips, enable multi-sim support when mips64vr5400-elf is target.
For sim/igen, allow specification of a default machine (will need
more work later).
 1997-12-09 04:01:06 +00:00
Doug Evans
6e51f990a2 Regenerate configure files. 1997-12-04 17:26:06 +00:00
Andrew Cagney
0931ce5aa7 Missing change log entry. 1997-12-03 22:54:44 +00:00
Andrew Cagney
0d5d0d102d Fix typo in format argument to sim_io_eprintf. 1997-11-26 12:07:27 +00:00
Andrew Cagney
35c246c9d7 Move MDMX instructions which are public knowledge from vr5400.igen 
into mdmx.igen (MDMX is MMX on steroids).  Keep the file secret.
 1997-11-26 11:47:36 +00:00
Andrew Cagney
8c31916d92 sanitize-r5900 not v5900 1997-11-25 22:02:59 +00:00
Andrew Cagney
58fb5d0a4f vr5400 sanitize cleanups 1997-11-25 21:47:16 +00:00
Andrew Cagney
232156dee9 o Add SIM_SIGFPE to sim-signals 
o Start SIM_SIG* at 64 so that the use of host signal numbers can be
  detected and reported.
o Update MIPS simulator to use sim-signal.
 1997-11-20 09:50:36 +00:00
Andrew Cagney
a09a30d298 Allow reads/writes to C0_CONFIG register. 1997-11-20 09:17:06 +00:00
Doug Evans
486740ce01 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). 1997-11-18 23:40:40 +00:00
Andrew Cagney
f23e93dab0 * mips.igen: Tag vr5000 instructions. 
(ANDI): Was missing mipsIV model, fix assembler syntax.
        (do_c_cond_fmt): New function.
        (C.cond.fmt): Handle mips I-III which do not support CC field
        separatly.
        (bc1): Handle mips IV which do not have a delaed FCC separatly.
        (SDR): Mask paddr when BigEndianMem, not the converse as specified
        in IV3.2 spec.
        (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
        vr5000 which saves LO in a GPR separatly.
        * configure.in (enable-sim-igen): For vr5000, select vr5000
        specific instructions.
        * configure: Re-generate.
 1997-11-14 08:27:38 +00:00
Andrew Cagney
a94c5493a7 Make the signess of compares between GPR's explicit using a cast to 
signed_word.
 1997-11-11 12:31:24 +00:00
Andrew Cagney
030843d7f8 Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, 
SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI,
MFHI instructions.
Trace nullified instruction.
 1997-11-11 07:50:13 +00:00
Andrew Cagney
95469cebdd Replace global IPC with function argument cia or current instruction 
address.
Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
 1997-11-06 14:24:57 +00:00
Andrew Cagney
7ce8b9178c IGEN likes to cache the current instruction address (CIA). Change the 
MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
 1997-11-06 09:16:16 +00:00
Andrew Cagney
44b8585a3d Add option --enable-sim-igen to mips configuration. Allows user to 
attempt a build of an older MIPS simulator using igen.
 1997-11-05 09:43:34 +00:00
Andrew Cagney
63be8febf7 Rewrite the MIPS simulator's memory model so that it uses the generic 
common/sim-core.

Add support for 3, 5, 6, 7 byte transfers to sim core.
 1997-11-05 08:17:26 +00:00
Andrew Cagney
22de994d0e Delete -l and -n options, didn't do anything. 
Rename option trace to dinero-trace & dinero-file - -t clashed with
common options.
Enable common trace options.
 1997-11-05 01:08:12 +00:00
Andrew Cagney
525d929e49 Rewrite sim_monitor (implements read, write, open, et.al. system 
calls) and sim_open so that they uses the virtual memory data transfer
functions sim_read & sim_write.  This eliminates all code (other than
in load_memory & store_memory) that makes assumptions about the
implementation of the underlying memory model.
 1997-11-05 00:08:14 +00:00
Gavin Romig-Koch
6205f37913 * gencode.c: Add tx49 configury and insns. 
* configure.in: Add tx49 configury.
	* configure: Update.
 1997-10-29 19:42:49 +00:00
Andrew Cagney
01b9cd49ca common/sim-bits.h: Document ROTn macro. 
igen/{igen.c,ld-insns.h}: Document mnemonic string formats.
mips/Makefile.in: Add dependencies for files included by mips.igen
mips/vr5400.igen: checkpoint vr5400 instructions.
 1997-10-29 04:02:30 +00:00
Andrew Cagney
89d0973831 Add support for 16 byte quantities to sim-endian macro H2T. 
Add model-filter field to option, include, model anf function igen records
 1997-10-28 07:10:36 +00:00
Andrew Cagney
16bd5d6e52 Separate r5900 specifoc and mips16 instructions. 
Add support for this to configure (vr5400 target only)
 1997-10-27 07:55:24 +00:00
Andrew Cagney
90ad43b2de Add mips64vr5400 to configuration list 
Mark mipsIV instructions as being implemented by the vr5400.
Sanitize.
 1997-10-27 06:42:13 +00:00
Gavin Romig-Koch
635ae9cb7c * sim/mips/gencode.c (build_instruction): Follow sim_write's lead in using 
BigEndianMem instead of !ByteSwapMem.
 1997-10-25 20:53:46 +00:00
Andrew Cagney
122edc03de Add basic igen configuration to autoconf. Disable. 1997-10-24 07:54:21 +00:00
Andrew Cagney
dad6f1f326 Add function to fetch 32bit instructions 
When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
 1997-10-24 06:43:51 +00:00
Andrew Cagney
92ad193bb0 Use SIM*_OVERFLOW_RESULT defined in sim-alu.h 1997-10-21 07:57:33 +00:00
Andrew Cagney
aa324b9b1e Output pc profile statistics once gathered. 1997-10-21 07:40:00 +00:00
Andrew Cagney
e2f8ffb736 Delete profile support from MIPS simulator, use sim/common/sim-profile 
module instead.
Generate a "gmon.out" (gprof) when profiling the target PC.
Add target PC profiling option --profile-pc-granularity (bucket size)
 1997-10-21 03:41:21 +00:00
Andrew Cagney
fb5a2a3e39 Make mips registers of type unsigned_word. 
Ensure all references to MIPS registers use same type.
 1997-10-20 06:28:53 +00:00
Andrew Cagney
ea985d2472 Move register definitions and macros out of interp.c and into sim-main.h 1997-10-16 03:50:48 +00:00
Andrew Cagney
284e759d1f Rename generated file engine.c to oengine.c. 1997-10-16 03:39:13 +00:00
Andrew Cagney
339fb14904 * gencode.c (build_instruction): Use FPR_STATE not fpr_state. 1997-10-16 03:29:47 +00:00
Andrew Cagney
8b70f83790 * gencode.c (build_instruction): For "FPSQRT", output correct number 
of arguments to Recip.
 1997-10-16 03:23:16 +00:00
Andrew Cagney
0c2c5f6141 Move global MIPS simulator variables into sim_cpu struct. 1997-10-14 09:26:03 +00:00
Andrew Cagney
18c64df613 o Add support for configuring wordsize, fp hardware and target 
endianness.  Provide defaults for some tier-1 mips targets.
o	Parameterize all functions with SIM_DESC.
 1997-10-14 07:27:31 +00:00
Andrew Cagney
adf4739efe Add access to hi part of r5900 128 bit registers. 1997-09-30 03:45:51 +00:00
Bob Manson
26b20b0a0e * configure: Regenerated. 
Can't hack one without the other...
 1997-09-29 21:46:32 +00:00
Mark Alexander
6eedf3f4e5 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. 1997-09-26 20:56:55 +00:00
Andrew Cagney
e63bc706fe Allow gencode.c to generate input to the igen generator. 1997-09-25 04:23:24 +00:00
Andrew Cagney
eb2e3c85ca Pacify GCC -Wall 1997-09-25 04:13:50 +00:00
Andrew Cagney
92f91d1ff0 Remove need to update <targ>/Makefile.in when adding optional options 
to <targ>/configure.in.
Simplify logic used to select target [default] endianness.
 1997-09-23 01:25:26 +00:00
Andrew Cagney
76a6247f07 Add memory alignment config option. 1997-09-22 09:40:57 +00:00
Andrew Cagney
794e9ac96a Simplify logic behind the generic configuration option --enable-sim-alignment. 1997-09-22 02:49:57 +00:00
Andrew Cagney
b45caf050c Add support for --enable-sim-alignment to simulator common aclocal.m4 
Add support for --alignment={strict,nonstrict,forced} to simulator common
run-time options.
For v850 use, make the default NONSTRICT_ALIGNMENT.
 1997-09-22 00:24:46 +00:00
Gavin Romig-Koch
7afa8d4edc * gencode.c: Add r3900 (tx39). 
* gencode.c: Fix some configuration problems by improving
	the relationship between tx19 and tx39.
 1997-09-19 13:39:55 +00:00
Gavin Romig-Koch
667065d0d4 * sim/mips/gencode.c (build_instruction): Don't need to subtract 4 for 
JALR, just 2.
 1997-09-16 20:01:00 +00:00
Gavin Romig-Koch
9cb8397f86 * sim/mips/interp.c: Correct some HASFPU problems. 1997-09-16 15:36:18 +00:00
Andrew Cagney
a2ab5e65eb Update to reflect change to sim/common/aclocal.m4 (allow sim/common 
directory to specify its own unqiue config.h file).
 1997-09-15 08:25:04 +00:00
Andrew Cagney
11ac69e013 Short form of sample-size option had wrong value. 1997-09-12 02:29:04 +00:00
Andrew Cagney
972f3a34f5 mips/sim_info was just returning????? 1997-09-10 23:50:32 +00:00
Andrew Cagney
9eeaaefa0f Better word error messages. 1997-09-09 10:38:39 +00:00
Andrew Cagney
c31c13b481 Remove GCC specific `0x...LL', replace with SIGNED64 (0x...). 1997-09-09 07:02:02 +00:00
Gavin Romig-Koch
b637f306ba tx19 and related necessary changes. 
* config.sub: Add tx19/r1900.
	* sim/mips/configure.in, sim/mips/gencode: Add tx19/r1900.
	* gcc/config.sub, gcc/configure: Add tx19/r1900.
	* gcc/config/mips/r1900.h, config/mips/t-r1900: New.
	* gas/config/tc-mips.c: Add tx19/r1900.

	* gcc/config/mips/mips.c: Don't build 16 bit to 32 bit stubs for
	TARGET_SOFT_FLOAT.

	* config.sub: Add "marketing-names" patch.
	* gcc/config.sub: Add "marketing-names" patch.

	* gcc/configure: Change "as" link from "../gas/as.new" to "../gas/as-new";
	Same for "ld" link.
 1997-09-07 20:33:22 +00:00
David Edelsohn
6fea47635b * configure: Regenerated to track ../common/aclocal.m4 changes. 1997-09-05 00:42:05 +00:00
Andrew Cagney
52352d38d6 Test/fix pabsh, pabsw, psrlvw. 1997-09-01 09:47:03 +00:00
Andrew Cagney
8811705410 Fix doco on enable-sim-inline. 1997-08-27 22:43:18 +00:00
Andrew Cagney
fafce69ab1 Add ABFD argument to sim_create_inferior. Document. 
Add file sim-hload.c - generic load for hardware only simulators.
Review each simulators sim_open, sim_load, sim_create_inferior so that
they more closely match required behavour.
 1997-08-27 04:44:41 +00:00
Andrew Cagney
7230ff0faa Flush defunct sim_kill. 1997-08-26 02:05:18 +00:00
Andrew Cagney
247fccdeb5 Add ABFD argument to sim_open call. Pass through to sim_config so 
that image properties such as endianness can be checked.

More strongly document the expected behavour of each of the sim_*
interfaces.

Add default endian argument to simulator config macro
SIM_AC_OPTION_ENDIAN.  Use in sim_config.
 1997-08-25 23:14:25 +00:00
Gavin Romig-Koch
c12e2e4c48 gencode.c: Two arg MADD should not assign result to /bin/bash. 1997-07-25 19:10:05 +00:00
Andrew Cagney
1e851d2c82 Fix a number of problems in the r5900 specific p* (parallel) instructions. 
In particular a host endian dependency one fixed resolved most problems.
 1997-07-11 03:07:29 +00:00