* config/tc-mips.c (mips_fix_adjustable): On REL targets also
reject PC-relative relocations.
gas/testsuite/
* gas/mips/branch-misc-2.d: Adjust for relocation change.
* gas/mips/branch-misc-2pic.d: Likewise.
* gas/mips/branch-misc-4.d: New test for PC-relative relocation
overflow.
* gas/mips/branch-misc-4-64.d: Likewise.
* gas/mips/branch-misc-4.s: Source for the new tests.
* testsuite/gas/mips/mips.exp: Run the new tests.
The BYTEOP2M insn was part of the initial Blackfin designs, but never made
it into any actual silicon. So punt support for it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The mmod field is decoded in a few places (gas/opcodes/sim), so move it to
a common place to avoid duplication.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* doc/as.texinfo: Refer to and include c-ppc.texi for PowerPC options.
(Overview <Target PowerPC options>): Add a number of missing options.
* doc/c-ppc.texi: Likewise. Add markup for use in manpage generation.
value when reporting the inability to write to the output file.
* config/tc-rx.c (rx_handle_align): Do not insert NOPs into align
frag that has a non-zero fill value.
* gas/all/align.d: Skip for the RX.
* gas/elf/group1a.d: Likewise.
* gas/elf/groupautoa.d: Likewise.
* gas/elf/elf.exp: Do not run section5 test for the RX port.
* gas/elf/section4.d: Likewise.
* gas/elf/section7.d: Likewise.
* gas/macros/semi.s: Fill with a non-zero pattern.
* gas/macros/semi.d: Expect non-zero fill value.
* gas/rx/bcnd.d: Update expected disassembly.
* gas/rx/bra.d: Likewise.
* gas/rx/macros.inc: Add reg1 macro.
* gas/rx/max.sm: Use reg1 macro to avoid generating illegal NOP
instruction.
* gas/rx/mov.sm: Likewise.
* gas/rx/max.d: Update expected disassembly.
* gas/rx/mov.d: Likewise.
* gas/rx/rx-asm-good.s: Use Renesas section names.
* gas/rx/rx-asm-good.d: Update expected disassembly.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
* elf32-rx.c: Add it to the list, corresponding to R_RX_OPneg.
* config/tc-rx.c (tc_gen_reloc): Emit an RX_OP_NEG expression
instead of an RH_NEG32 one.
* config/tc-hppa.c (pa_ip): Revert last change. Add variable need_cond
to determine whether a 64-bit condition is needed for 'A' and 'S'
conditions. Default to 32-bit never condition for logical and unit
instructions. Add error message for missing branch on bit condition.
* hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
"bb" entries.
* hppa-dis.c (compare_cond_64_names): Change never condition to ",*".
(add_cond_64_names): Likewise.
(logical_cond_64_names): Likewise.
(unit_cond_64_names): Likewise.
* config/tc-hppa.c (pa_ip): Set doubleword carry/borrow bit when a
doubleword completer or doubleword condition is found in an add/sub
instruction. Reject match for 'A'/'S' only if there is no condition
and d bit is not set.
* gas/hppa/basic/add2.s: Add test for a simple doubleword carry
instruction.
* gas/hppa/basic/sub2.s: Add tests for simple word and doubleword
borrow instructions.
* gas/hppa/basic/basic.exp: Update regexps for above.
* opcode/hppa.h: Clear "d" bit in "add" and "sub" patterns.
for new fake labels created off the dot special symbol.
* config/tc-mips.h (tc_new_dot_label): New macro.
(mips_record_label): New prototype.
* config/tc-mips.c (my_getExpression): Remove MIPS16 fake label
annotation.
(s_cons, s_float_cons, s_gpword, s_gpdword): Only clear labels
recorded once data expressions have been evaluated.
(mips_define_label): Move code to record labels over to...
(mips_record_label): ... this new function.
* doc/internals.texi: Document tc_new_dot_label.
* config/tc-mips.c (file_ase_mips16): Adjust comment.
(append_insn): Update file_ase_mips16.
(mips_after_parse_args): Don't set file_ase_mips16 here.
gas/testsuite/
* gas/mips/elf_ase_mips16.d: Update test for new MIPS16 ASE flag
semantics.
* gas/mips/elf_ase_mips16-2.d: New test.
* gas/mips/nop.s: Source for the new test.
* gas/mips/mips.exp: Run the new test.
binutils/testsuite/
* lib/binutils-common.exp (regexp_diff): Implement inverse
matching, requested by `!'.
* config/tc-mips.c (macro) <ld_st>: Don't load a zero into an
auxiliary register when using a signed 16-bit constant offset.
gas/testsuite/
* gas/mips/ldstla-32.d: Update according to a 16-bit constant
offset optimization.
* gas/mips/ldstla-32-mips3.d: Likewise.
* gas/mips/ldstla-32-shared.d: Likewise.
* gas/mips/ldstla-32-mips3-shared.d: Likewise.
* config/tc-z80.c (emit_mx, emit_ldxhl): Do not use
symbol_get_value_expression on a symbol that may not yet have
a value.
* testsuite/gas/z80/atend.s: New file, test case for bug 12269,
provided by Chris Smith.
* testsuite/gas/z80/atend.d: New file, expected results for atend.s.
* testsuite/gas/z80/z80.exp: Run new test case.
* config/tc-s390.c (current_cpu): Initialize with latest CPU.
(init_default_arch): Default to z/Architecture mode if CPU provides it.
Remove the check setting the CPU default.
2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
* gas/config/tc-arm.c (arm_arch_v6m_only): New variable.
(aeabi_set_public_attributes): Ensure we only set the Operating System
Extension when we are on an M-profile core.
* gas/testsuite/gas/arm/pr12198-1.d: New test.
* gas/testsuite/gas/arm/pr12918-1.s: Likewise.
* gas/testsuite/gas/arm/pr12198-2.d: Likewise.
* gas/testsuite/gas/arm/pr12918-2.s: Likewise.
* include/opcode/arm.h (ARM_AEXT_V6M_ONLY): New define.
(ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
(ARM_ARCH_V6M_ONLY): New define.
* config/tc-mips.c (macro_build): Remove gas_assert from 'o' case.
Use a restricted gas_assert for 'i' and 'j'.
gas/testsuite/
* gas/mips/elf-rel28.s, gas/mips/elf-rel28-n32.d,
gas/mips/elf-rel28-n64.d: New test.
* gas/mips/mips.exp: Run it.
(OPTION_NOPS): Define.
(md_longopts): Add --nops.
(md_parse_option): Handle it.
(md_show_usage): Publish.
(ppc_handle_align): Pad with a branch followed by nops if more
than nop_limit nops.
* config/tc-s390.c (md_begin): Only add to hash table if cpu and
mode mask fit.
2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
* config/obj-elf.c (elf_adjust_symtab): New. Move group section
processing here from elf_frob_file. Ensure that group signature
symbols have the name of the group.
(elf_frob_file): Move group section processing to
elf_adjust_symtab.
* config/obj-elf.h (elf_adjust_symtab): Declare.
(obj_adjust_symtab): Define.
* config/tc-arm.c (arm_adjust_symtab): Call elf_adjust_symtab.
2010-10-23 Mark Mitchell <mark@codesourcery.com>
* gas/elf/elf.exp: Add group0c test.
* gas/elf/group0c.d: New.
* gas/elf/group0a.d: Expect ".group" for the name of group
sections.
* gas/elf/group0b.d: Likewise.
* gas/elf/group1a.d: Likewise.
* gas/elf/group1b.d: Likewise.
* gas/elf/groupautoa.d: Likewise.
* gas/elf/groupautob.d: Likewise.
* gas/elf/section4.d: Likewise.
* gas/ia64/group-1.d: Likewise. Adjust hard-coded constants.
2010-10-22 Mark Mitchell <mark@codesourcery.com>
* binutils-all/group-5.d: Expect ".group" for the name of group
sections.
* binutils-all/strip-2.d: Likewise.
2010-10-23 Mark Mitchell <mark@codesourcery.com>
* ld-elf/group10.d: Expect ".group" for the name of group
sections.
* ld-elf/group2.d: Likewise.
* ld-elf/group7.d: Likewise.
* emulparams/elf32_sparc_sol2.sh (OUTPUT_FORMAT): Set to
elf32-sparc-sol2.
* emulparams/elf64_sparc_sol2.sh (OUTPUT_FORMAT): Set to
elf64-sparc-sol2.
gas:
* config/tc-sparc.h [TE_SOLARIS] (ELF_TARGET_FORMAT): Define as
elf32-sparc-sol2.
(ELF64_TARGET_FORMAT): Define as elf64-sparc-sol2.
bfd:
* elfxx-sparc.c (tpoff): Define bed, static_tls_size.
Consider static_tls_alignment.
* elf32-sparc.c (TARGET_BIG_SYM): Redefine to
bfd_elf32_sparc_sol2_vec.
(TARGET_BIG_NAME): Redefine to elf32-sparc-sol2.
(elf32_bed): Redefine to elf32_sparc_sol2_bed.
(elf_backend_static_tls_alignment): Redefine to 8.
Include elf32-target.h.
(elf_backend_static_tls_alignment): Undef again for VxWorks.
* elf64-sparc.c (TARGET_BIG_SYM): Redefine to
bfd_elf64_sparc_sol2_vec.
(TARGET_BIG_NAME): Redefine to elf64-sparc-sol2.
(ELF_OSABI): Undef.
(elf64_bed): Redefine to elf64_sparc_sol2_bed.
(elf_backend_static_tls_alignment): Redefine to 16.
Include elf64-target.h.
* config.bfd (sparc-*-solaris2.[0-6]): Split from sparc-*-elf*.
Set targ_defvec to bfd_elf32_sparc_sol2_vec.
[BFD64] (sparc-*-solaris2*): Set targ_defvec to
bfd_elf32_sparc_sol2_vec.
Replace bfd_elf64_sparc_vec by bfd_elf64_sparc_sol2_vec in
targ_selvecs.
* configure.in: Handle bfd_elf32_sparc_sol2_vec,
bfd_elf64_sparc_sol2_vec.
* configure: Regenerate.
* targets.c (bfd_elf32_sparc_sol2_vec): Declare.
(bfd_elf64_sparc_sol2_vec): Declare.
(_bfd_target_vector): Add bfd_elf32_sparc_sol2_vec,
bfd_elf64_sparc_sol2_vec.
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
macros before their corresponding MIPS III hardware instructions.
gas/
* config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs.
gas/testsuite/
* gas/mips/lineno.s: Convert to o32.
* gas/mips/lineno.d: Adjust patterns accordingly. Force the o32
ABI.
The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode.
Once we've fixed that, it's easy to see that the disassembler also likes
to decode this insn incorrectly. So fix that and then add some tests.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
gas/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Add disp32_encoding.
(md_assemble): Don't call optimize_disp if disp32_encoding is
set.
(parse_insn): Support .d32 to force 32bit displacement.
(output_branch): Use BIG if disp32_encoding is set.
* doc/c-i386.texi: Document .d32 encoding suffix.
gas/testsuite/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/disp32.d: New.
* gas/i386/disp32.s: Likewise.
* gas/i386/x86-64-disp32.d: Likewise.
* gas/i386/x86-64-disp32.s: Likewise.
* gas/i386/i386.exp: Run disp32 and x86-64-disp32.
Currently, trying to declare single letter variables in Blackfin assembly
can sometimes lead to parser errors if that letter is used for insn flags.
For example, X, Z, S, M, and T are used to change the behavior of insns:
R0 = 1; R0 = 1 (X); R0 = 1 (Z);
But the current parser just looks for single letter tokens rather than
ones that show up in the (FLAGS) field. So only match these letters as
flags when they're in parentheses.
Not a complete fix, but it at least lets gcc tests pass now (the test
gcc/testsuite/gcc.c-torture/compile/mangle-1.c to be exact). A complete
fix would require a significant parser rewrite in order to handle:
R0 = (x) (x); /* zero extend the address of the symbol "x" */
R0 = W; R0 = W[P0];
Signed-off-by: Steve Kilbane <steve.kilbane@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current LOOP_BEGIN/LOOP_END pseudo insns hit parser errors when trying
to use numeric local labels. So add support for them.
Signed-off-by: David Gibson <david.gibson@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current LOOP_BEGIN/LOOP_END pseudo insns hit "Internal errors" when
using local labels as the loop names due to attempts at removing them.
Signed-off-by: David Gibson <david.gibson@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* config/tc-tic6x.c (tic6x_try_encode): Correct encoding of fstg field
in SPKERNEL instructions.
opcodes/
* tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
in SPKERNEL instructions.
gas/testsuite/
* gas/tic6x/insns-c674x-sploop.d: Add two more sploop/spkernel tests.
* gas/tic6x/insns-c674x-sploop.s: Likewise.
* elf32-arm.c (elf32_arm_stub_long_branch_any_arm_pic,
elf32_arm_stub_long_branch_any_arm_pic): Use a consistent name for
ip/r12.
(arm_type_of_stub): Remove superfluous braces.
gas/
* config/tc-arm.c (encode_branch): Remove superfluous braces.
(do_t_branch): Move reloc setting to end of routine.
* config/tc-mips.c (mips_fix_cn63xxp1): New variable.
(mips_ip): Add errata work around when mips_fix_cn63xxp1 set.
(OPTION_FIX_CN63XXP1, OPTION_NO_FIX_CN63XXP1): New enum options
enumerations.
(md_longopts): Add options for -mfix-cn63xxp1 and -mno-fix-cn63xxp1.
(md_parse_option): Handle OPTION_FIX_CN63XXP1 and
OPTION_NO_FIX_CN63XXP1.
(md_show_usage): Add documentation for -mfix-cn63xxp1.
* doc/c-mips.texi (-mfix-cn63xxp1, -mno-fix-cn63xxp1): Document
the new options.
2010-10-04 David Daney <ddaney@caviumnetworks.com>
* gas/mips/mips.exp (octeon-pref): Run the new test.
* gas/mips/octeon-pref.s: New test.
* gas/mips/octeon-pref.d: New expected results for the new test.
* gas/config/tc-arm.c (arm_ext_virt): New variable.
(arm_reg_type): Add REG_TYPE_RNB for banked registers.
(reg_entry): Allow registers to be larger than a byte.
(reg_alias): Fix type warning.
(parse_operands): Parse banked registers when appropriate.
(do_mrs): Add support for Virtualization Extensions.
(do_hvc): New function.
(do_t_mrs): Add support for Virtualization Extensions.
(do_t_msr): Likewise.
(do_t_hvc): New function.
(SPLRBANK): New define.
(reg_names): Add banked registers.
(insns): Add support for Virtualization Extensions.
(md_apply_fixup): Likewise.
(arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions.
(arm_extensions): Add 'virt' extension.
(aeabi_set_public_attributes): Add support for Virtualization
Extensions.
* gas/doc/c-arm.texi: Document 'virt' extension.
* gas/testsuite/gas/arm/armv7-a+virt.d: New test.
* gas/testsuite/gas/arm/armv7-a+virt.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions.
* gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test.
* gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise.
* include/opcode/arm.h (ARM_EXT_VIRT): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
Extensions.
* opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
(thumb32_opcodes): Likewise.
(banked_regname): New function.
(print_insn_arm): Add Virtualization Extensions support.
(print_insn_thumb32): Likewise.
(do_div): New function.
(insns): Accept UDIV and SDIV in ARM state.
(arm_cpus): The cortex-a15 option has all current v7-A extensions.
(arm_extensions): Add 'idiv' extension.
(aeabi_set_public_attributes): Update Tag_DIV_use values for the
Integer Divide extension.
* gas/doc/c-arm.texi: Document the idiv extension.
* gas/testsuite/gas/arm/armv7-a+idiv.d: New test.
* gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension.
* gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test.
* include/opcode/arm.h (ARM_AEXT_ADIV): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
* opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
ARM state.
(arm_ext_m): Add support for OS extension.
(arm_ext_os): New variable.
(do_t_swi): In v6-M ensure we have the OS extension.
(arm_cpus): The cortex-m1 and cortex-m0 options have the OS
extension by default.
(arm_archs): Add armv6s-m.
(arm_extensions): Add 'os' extension.
(cpu_arch_ver): Add support for v6S-M.
* gas/doc/c-arm.texi: Document the OS Extension, and v6-m and v6s-m
architecture options.
* gas/testsuite/gas/arm/archv6s-m-bad.d: New test.
* gas/testsuite/gas/arm/archv6s-m-bad.l: Likewise.
* gas/testsuite/gas/arm/archv6s-m.d: Likewise.
* gas/testsuite/gas/arm/archv6s-m.s: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6s-m.d: Likewise.
* include/opcode/arm.h (ARM_EXT_OS): New define.
(ARM_AEXT_V6SM): Likewise.
(ARM_ARCH_V6SM): Likewise.
Check for & reject attempts to use multiple store insns in a single
parallel insn combination. These are illegal per the Blackfin ISA.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin ISA supports moving just about anything to/from EMUDAT, so
make sure the assembler accepts these insns too.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Using "Register mismatch" everywhere can be a bit vague, so clarify
why exactly we're barfing on these unsupported insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some extended registers when given to the DBG/DBGCMPLX pseudo insns are
not encoded properly. So fix them, fix the display of them when being
disassembled, and add testcases.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Accept any 8bit char with the high bit set so as to support multibyte
characters. Also use the locale safe regular expressions to match
chars/digits. This brings the Blackfin assembler inline with the
behavior of other assemblers.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Support a few more ASTAT bits with the standard insns that operate on
ASTAT bits directly.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The disassembler has partial (but incomplete/broken) support already for
the pseudo debug insn OUTC, so let's fix it up and finish it. And now
that the disassembler can handle it, make sure our assembler can output
it too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
There is a pseudo debug insn named ABORT that is commonly used in
simulation, so support it in the assembler too. The disassembler
already supports it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We don't use the # character in the Blackfin assembly language, so let it
start end-of-line comments like most other assemblers.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas/testsuite/gas/arm/attr-cpu-directive.d: Update test for change in canonical
CPU name.
* gas/testsuite/gas/arm/attr-mcpu.d: Likewise.
* ld/testsuite/ld-arm/attr-merge-6.attr: Update tests for change in canonical
CPU name.
* ld/testsuite/ld-arm/attr-merge-7.attr: Likewise.
* ld/testsuite/ld-arm/attr-merge-2.attr: Likewise.
* ld/testsuite/ld-arm/attr-merge-arch-2.attr: Likewise.
* config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead
of just RR.
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand.
* gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also
add disassembly for test added in copro.s
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
* config/tc-mips.c (macro)[M_JAL_1, M_JAL_2]: Handle the JALR
delay slot in the noreorder mode with the o32 ABI.
gas/testsuite/
* gas/mips/jal-svr4pic-noreorder.d: New test case.
* gas/mips/mips1@jal-svr4pic-noreorder.d: New test
subarchitecture.
* gas/mips/r3000@jal-svr4pic-noreorder.d: Likewise.
* gas/mips/jal-svr4pic-noreorder.s: Source for the new test
case.
* gas/mips/mips.exp: Run the new test case.
* config/tc-mips.c (mips_frob_file): Use symbol_same_p to match
symbols.
gas/testsuite/
* gas/mips/elf-rel27.d: New test for HI16/LO16 relocation
pairing.
* gas/mips/elf-rel27.s: Source for the new test.
* gas/mips/mips.exp: Create "mips16" architecture. Adjust
conditions involving negated properties throughout to require
"mips1" as appropriate. Run the new test.
(mips_arch_destroy): New procedure.
* config/tc-ppc.c (ppc_set_cpu): Cast PPC_OPCODE_xxx to ppc_cpu_t
before inverting.
binutils/:
* ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
ppc_cpu_t before inverting.
* config/tc-tic6x.h (tic6x_segment_info_type): Add field
func_units_used.
* config/tc-tic6x.c (tic6x_cons_align: Clear func_units_used.
(md_assemble): Clear func_units_used for new execute packet.
Check for duplicate functional units and update func_units_used
for instructions using a functional unit.
gas/testsuite:
* gas/tic6x/resource-func-unit-1.d,
gas/tic6x/resource-func-unit-1.l,
gas/tic6x/resource-func-unit-1.s,
gas/tic6x/resource-func-unit-2.d,
gas/tic6x/resource-func-unit-2.l,
gas/tic6x/resource-func-unit-2.s: New.
* config/tc-ppc.c (md_assemble): Emit APUinfo section for
PPC_OPCODE_E500.
gas/testsuite/
* gas/ppc/e500.s: Add eieio, mbar and lwsync
* gas/ppc/e500.d: Likewise.
include/opcode/
* ppc.h (PPC_OPCODE_E500): Define.
opcodes/
* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
* ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
touch floating point regs and are enabled by COM, PPC or PPCCOM.
Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
Treat lwsync as msync on e500.
2010-06-10 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (update_code_flag): New.
(set_code_flag): Use it.
(i386_target_format): Replace set_code_flag with update_code_flag.
2010-06-10 Tristan Gingold <gingold@adacore.com>
* som.c: Can now be compiled on any host.
Include bfd headers instead of system one.
(som_compute_checksum): Parameter is now a pointer to a
som_external_header structure. Adjust.
(struct section_to_type): Field section is now const.
(R_DLT_REL, R_AUX_UNWIND, R_SEC_STMT): Removed conditional
definition.
(R_LONG_PCREL_MODE, R_N0SEL, R_N1SEL, R_LINETAB): Ditto.
(R_LINETAB_ESC, R_LTP_OVERRIDE, R_COMMENT): Ditto.
(som_swap_clock_in, som_swap_clock_out): New functions.
(som_swap_header_in, som_swap_header_out): Likewise.
(som_swap_space_dictionary_in): Likewise.
(som_swap_space_dictionary_out): Likewise.
(som_swap_subspace_dictionary_in): Likewise.
(som_swap_subspace_dictionary_record_out): Likewise.
(som_swap_aux_id_in, som_swap_aux_id_out): Likewise.
(som_swap_string_auxhdr_out): Likewise.
(som_swap_compilation_unit_out): Likewise.
(som_swap_exec_auxhdr_in): Likewise.
(som_swap_exec_auxhdr_out): Likewise.
(som_swap_lst_header_in): Likewise.
(som_object_setup): Adjust parameter type using bfd types.
(setup_sections): Likewise. Ditto for object file types.
Use intermediate variables for external representation and use the
swap functions to convert.
(som_object_p): Ditto. Remove #ifdef/#endif on always defined
macros.
(som_prep_headers): Likewise.
(som_write_symbol_strings): Likewise.
(som_begin_writing): Likewise.
(som_finish_writing): Likewise.
(som_build_and_write_symbol_table): Likewise.
(bfd_section_from_som_symbol): Likewise.
(som_slurp_symbol_table): Likewise.
(som_bfd_print_private_bfd_data): Likewise.
(bfd_som_attach_aux_hdr): Likewise. Clear the padding.
(bfd_som_attach_compilation_unit): Likewise.
(som_bfd_count_ar_symbols): Likewise.
(som_bfd_fill_in_ar_symbols): Likewise.
(som_slurp_armap): Likewise.
(som_bfd_ar_write_symbol_stuff): Likewise.
(som_write_armap): Likewise. Use _bfd_ar_spacepad instead of
sprintf to write header fields.
* som.h: Include bfd headers instead of system one.
(FILE_HDR_SIZE, AUX_HDR_SIZE): Removed.
(struct somdata): Use bfd structures instead of system ones.
(struct som_section_data_struct): Likewise.
(struct som_subspace_dictionary_record): Removed (now in
include/som/internal.h)
gas/
2010-06-10 Tristan Gingold <gingold@adacore.com>
* config/obj-som.h: Includes som/reloc.h
2010-06-10 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (cpu_arch): Add comment.
(i386_target_format): Set cpu_arch_isa_flags and cpu_arch_tune_flags
from the generic entries of cpu_arch[].
value.
(parse_operands): Add support for OP_RRnpctw.
(insns): Update floating-point load/store multiples so the
first register is of type OP_RRnpctw.
* gas/testsuite/gas/arm/vldm-arm.d: New test.
* gas/testsuite/gas/arm/vldm-thumb-bad.d: Likewise.
* gas/testsuite/gas/arm/vldm-thumb-bad.l: Likewise.
* gas/testsuite/gas/arm/vldm.s: Likewise.
* gas/testsuite/gas/arm/vldmw-arm-bad.d: Likewise.
* gas/testsuite/gas/arm/vldmw-bad.l: Likewise.
* gas/testsuite/gad/arm-vldmw-bad.s: Likewise.
* gas/testsuite/gas/arm/vldmw-thumb-bad.d: Likewise.
lsls and not adds.
* gas/testsuite/gas/arm/thumb2_it_auto.d: Update for change in movs encoding.
gas/arm/thumb2_it.d: Likewise.
gas/arm/thumb32.d: Likewise.
writeback when base register is in register list an error, and
correct check.
(do_t_ldmstm): Change warnings.
* gas/arm/thumb2_ldmstm.d: Add new testcases.
* gas/arm/thumb2_ldmstm.s: Likeiwse.
* gas/arm/thumb2_ldmstm_bad.d: Add testcases to check for
UNPREDICTABLE ldm/stm.
* gas/arm/thumb2_ldmstm_bad.l: Likewise.
* gas/arm/thumb2_ldmstm_bad.s: Likewise.
Joseph Myers <joseph@codesourcery.com>
Andrew Stubbs <ams@codesourcery.com>
bfd/
* config.bfd (sh-*-uclinux* | sh[12]-*-uclinux*): Add
bfd_elf32_shl_vec, and FDPIC vectors to targ_selvecs.
* configure.in: Handle FDPIC vectors.
* elf32-sh-relocs.h: Add FDPIC and movi20 relocations.
* elf32-sh.c (DEFAULT_STACK_SIZE): Define.
(SYMBOL_FUNCDESC_LOCAL): Define. Use it instead of
SYMBOL_REFERENCES_LOCAL for function descriptors.
(fdpic_object_p): New.
(sh_reloc_map): Add FDPIC and movi20 relocations.
(sh_elf_info_to_howto, sh_elf_relocate_section): Handle new invalid
range.
(struct elf_sh_plt_info): Add got20 and short_plt. Update all
definitions.
(FDPIC_PLT_ENTRY_SIZE, FDPIC_PLT_LAZY_OFFSET): Define.
(fdpic_sh_plt_entry_be, fdpic_sh_plt_entry_le, fdpic_sh_plts): New.
(FDPIC_SH2A_PLT_ENTRY_SIZE, FDPIC_SH2A_PLT_LAZY_OFFSET): Define.
(fdpic_sh2a_plt_entry_be, fdpic_sh2a_plt_entry_le)
(fdpic_sh2a_short_plt_be, fdpic_sh2a_short_plt_le, fdpic_sh2a_plts):
New.
(get_plt_info): Handle FDPIC.
(MAX_SHORT_PLT): Define.
(get_plt_index, get_plt_offset): Handle short_plt.
(union gotref): New.
(struct elf_sh_link_hash_entry): Add funcdesc, rename tls_type to
got_type and adjust all uses. Add GOT_FUNCDESC.
(struct sh_elf_obj_tdata): Add local_funcdesc. Rename
local_got_tls_type to local_got_type.
(sh_elf_local_got_type): Renamed from sh_elf_local_got_tls_type. All
users changed.
(sh_elf_local_funcdesc): Define.
(struct elf_sh_link_hash_table): Add sfuncdesc, srelfuncdesc, fdpic_p,
and srofixup.
(sh_elf_link_hash_newfunc): Initialize new fields.
(sh_elf_link_hash_table_create): Set fdpic_p.
(sh_elf_omit_section_dynsym): New.
(create_got_section): Create .got.funcdesc, .rela.got.funcdesc
and .rofixup.
(allocate_dynrelocs): Allocate local function descriptors and space
for R_SH_FUNCDESC-related relocations, and for rofixups.
Handle GOT_FUNCDESC. Create fixups. Handle GOT entries which
require function descriptors.
(sh_elf_always_size_sections): Handle PT_GNU_STACK and __stacksize.
(sh_elf_modify_program_headers): New.
(sh_elf_size_dynamic_sections): Allocate function descriptors for
local symbols. Allocate .got.funcdesc contents. Allocate rofixups.
Handle local GOT entries of type GOT_FUNCDESC. Create fixups for
local GOT entries. Ensure that FDPIC libraries always have a PLTGOT
entry in the .dynamic section.
(sh_elf_add_dyn_reloc, sh_elf_got_offset, sh_elf_initialize_funcdesc)
(sh_elf_add_rofixup, sh_elf_osec_to_segment)
(sh_elf_osec_readonly_p, install_movi20_field): New functions.
(sh_elf_relocate_section): Handle new relocations, R_SH_FUNCDESC,
R_SH_GOTFUNCDESC and R_SH_GOTOFFFUNCDESC. Use sh_elf_got_offset
and .got.plt throughout to find _GLOBAL_OFFSET_TABLE_. Add rofixup
read-only section warnings. Handle undefined weak symbols. Generate
fixups for R_SH_DIR32 and GOT entries. Check for cross-segment
relocations and clear EF_SH_PIC. Handle 20-bit relocations.
Always generate R_SH_DIR32 for FDPIC instead of R_SH_RELATIVE.
(sh_elf_gc_sweep_hook): Handle R_SH_FUNCDESC, R_SH_GOTOFF20,
R_SH_GOTFUNCDESC, R_SH_GOTFUNCDESC20, and R_SH_GOTOFFFUNCDESC.
Handle 20-bit relocations.
(sh_elf_copy_indirect_symbol): Copy function descriptor reference
counts.
(sh_elf_check_relocs): Handle new relocations. Make symbols
dynamic for FDPIC relocs. Account for rofixups. Error for FDPIC
symbol mismatches. Allocate a GOT for R_SH_DIR32. Allocate fixups
for R_SH_DIR32.
(sh_elf_copy_private_data): Copy PT_GNU_STACK size.
(sh_elf_merge_private_data): Copy initial flags. Do not clobber
non-mach flags. Set EF_SH_PIC for FDPIC. Reject FDPIC mismatches.
(sh_elf_finish_dynamic_symbol): Do not handle got_funcdesc entries
here. Rename sgot to sgotplt and srel to srelplt. Handle short_plt,
FDPIC descriptors, and got20. Create R_SH_FUNCDESC_VALUE for FDPIC.
Use install_movi20_field. Rename srel to srelgot. Always generate
R_SH_DIR32 for FDPIC instead of R_SH_RELATIVE.
(sh_elf_finish_dynamic_sections): Fill in the GOT pointer in rofixup.
Do not fill in reserved GOT entries for FDPIC. Correct DT_PLTGOT.
Rename sgot to sgotplt. Assert that the right number of rofixups
and dynamic relocations were allocated.
(sh_elf_use_relative_eh_frame, sh_elf_encode_eh_address): New.
(elf_backend_omit_section_dynsym): Use sh_elf_omit_section_dynsym.
(elf_backend_can_make_relative_eh_frame)
(elf_backend_can_make_lsda_relative_eh_frame)
(elf_backend_encode_eh_address): Define.
(TARGET_BIG_SYM, TARGET_BIG_NAME, TARGET_LITTLE_SYM)
(TARGET_LITTLE_NAME, elf_backend_modify_program_headers, elf32_bed):
Redefine for FDPIC vector.
* reloc.c: Add SH FDPIC and movi20 relocations.
* targets.c (_bfd_target_vector): Add FDPIC vectors.
* configure, bfd-in2.h, libbfd.h: Regenerated.
binutils/
* readelf.c (get_machine_flags): Handle EF_SH_PIC and EF_SH_FDPIC.
gas/
* config/tc-sh.c (sh_fdpic): New.
(sh_check_fixup): Handle relocations on movi20.
(parse_exp): Do not reject PIC operators here.
(build_Mytes): Check for unhandled PIC operators here. Use
sh_check_fixup for movi20.
(enum options): Add OPTION_FDPIC.
(md_longopts, md_parse_option, md_show_usage): Add --fdpic.
(sh_fix_adjustable, md_apply_fix): Handle FDPIC and movi20 relocations.
(sh_elf_final_processing): Handle --fdpic.
(sh_uclinux_target_format): New.
(sh_parse_name): Handle FDPIC relocation operators.
* config/tc-sh.h (TARGET_FORMAT): Define specially for TE_UCLINUX.
(sh_uclinux_target_format): Declare for TE_UCLINUX.
* configure.tgt (sh-*-uclinux* | sh[12]-*-uclinux*): Set
em=uclinux.
* doc/c-sh.texi (SH Options): Document --fdpic.
gas/testsuite/
* gas/sh/basic.exp: Run new tests. Handle uClinux like Linux.
* gas/sh/fdpic.d: New file.
* gas/sh/fdpic.s: New file.
* gas/sh/reg-prefix.d: Force big-endian.
* gas/sh/sh2a-pic.d: New file.
* gas/sh/sh2a-pic.s: New file.
* lib/gas-defs.exp (is_elf_format): Include sh*-*-uclinux*.
include/elf/
* sh.h (EF_SH_PIC, EF_SH_FDPIC): Define.
(R_SH_FIRST_INVALID_RELOC_6, R_SH_LAST_INVALID_RELOC_6): New. Adjust
other invalid ranges.
(R_SH_GOT20, R_SH_GOTOFF20, R_SH_GOTFUNCDESC, R_SH_GOTFUNCDESC20)
(R_SH_GOTOFFFUNCDESC, R_SH_GOTOFFFUNCDESC20, R_SH_FUNCDESC)
(R_SH_FUNCDESC_VALUE): New.
ld/
* Makefile.am (ALL_EMULATIONS): Add eshelf_fd.o and eshlelf_fd.o.
(eshelf_fd.c, eshlelf_fd.c): New rules.
* Makefile.in: Regenerate.
* configure.tgt (sh-*-uclinux*): Add shelf_fd and shlelf_fd
emulations.
* emulparams/shelf_fd.sh: New file.
* emulparams/shlelf_fd.sh: New file.
* emulparams/shlelf_linux.sh: Update comment.
ld/testsuite/
* ld-sh/sh.exp: Handle uClinux like Linux.
* lib/ld-lib.exp (is_elf_format): Include sh*-*-uclinux*.
* ld-sh/fdpic-funcdesc-shared.d: New file.
* ld-sh/fdpic-funcdesc-shared.s: New file.
* ld-sh/fdpic-funcdesc-static.d: New file.
* ld-sh/fdpic-funcdesc-static.s: New file.
* ld-sh/fdpic-gotfuncdesc-shared.d: New file.
* ld-sh/fdpic-gotfuncdesc-shared.s: New file.
* ld-sh/fdpic-gotfuncdesc-static.d: New file.
* ld-sh/fdpic-gotfuncdesc-static.s: New file.
* ld-sh/fdpic-gotfuncdesci20-shared.d: New file.
* ld-sh/fdpic-gotfuncdesci20-shared.s: New file.
* ld-sh/fdpic-gotfuncdesci20-static.d: New file.
* ld-sh/fdpic-gotfuncdesci20-static.s: New file.
* ld-sh/fdpic-goti20-shared.d: New file.
* ld-sh/fdpic-goti20-shared.s: New file.
* ld-sh/fdpic-goti20-static.d: New file.
* ld-sh/fdpic-goti20-static.s: New file.
* ld-sh/fdpic-gotofffuncdesc-shared.d: New file.
* ld-sh/fdpic-gotofffuncdesc-shared.s: New file.
* ld-sh/fdpic-gotofffuncdesc-static.d: New file.
* ld-sh/fdpic-gotofffuncdesc-static.s: New file.
* ld-sh/fdpic-gotofffuncdesci20-shared.d: New file.
* ld-sh/fdpic-gotofffuncdesci20-shared.s: New file.
* ld-sh/fdpic-gotofffuncdesci20-static.d: New file.
* ld-sh/fdpic-gotofffuncdesci20-static.s: New file.
* ld-sh/fdpic-gotoffi20-shared.d: New file.
* ld-sh/fdpic-gotoffi20-shared.s: New file.
* ld-sh/fdpic-gotoffi20-static.d: New file.
* ld-sh/fdpic-gotoffi20-static.s: New file.
* ld-sh/fdpic-plt-be.d: New file.
* ld-sh/fdpic-plt-le.d: New file.
* ld-sh/fdpic-plt.s: New file.
* ld-sh/fdpic-plti20-be.d: New file.
* ld-sh/fdpic-plti20-le.d: New file.
* ld-sh/fdpic-stack-default.d: New file.
* ld-sh/fdpic-stack-size.d: New file.
* ld-sh/fdpic-stack.s: New file.
