* gas/config/tc-arm.c (operand_parse_code): Add OP_RRnpctw enum
value. (parse_operands): Add support for OP_RRnpctw. (insns): Update floating-point load/store multiples so the first register is of type OP_RRnpctw. * gas/testsuite/gas/arm/vldm-arm.d: New test. * gas/testsuite/gas/arm/vldm-thumb-bad.d: Likewise. * gas/testsuite/gas/arm/vldm-thumb-bad.l: Likewise. * gas/testsuite/gas/arm/vldm.s: Likewise. * gas/testsuite/gas/arm/vldmw-arm-bad.d: Likewise. * gas/testsuite/gas/arm/vldmw-bad.l: Likewise. * gas/testsuite/gad/arm-vldmw-bad.s: Likewise. * gas/testsuite/gas/arm/vldmw-thumb-bad.d: Likewise.
This commit is contained in:
Matthew Gretton-Dann
parent
e1df38aad4
commit
55881a11e8
11 changed files with 131 additions and 30 deletions
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@ -1,3 +1,11 @@
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2010-06-08 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (operand_parse_code): Add OP_RRnpctw enum
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value.
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(parse_operands): Add support for OP_RRnpctw.
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(insns): Update floating-point load/store multiples so the
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first register is of type OP_RRnpctw.
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2010-06-08 Quentin Neill <quentin.neill@amd.com>
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* config/tc-i386.c (pi): Rename local loop counter
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@ -5759,6 +5759,8 @@ enum operand_parse_code
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OP_RRnpc, /* ARM register, not r15 */
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OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
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OP_RRnpcb, /* ARM register, not r15, in square brackets */
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OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
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optional trailing ! */
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OP_RRw, /* ARM register, not r15, optional trailing ! */
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OP_RCP, /* Coprocessor number */
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OP_RCN, /* Coprocessor register */
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@ -6128,6 +6130,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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po_char_or_fail (']');
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break;
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case OP_RRnpctw:
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case OP_RRw:
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case OP_oRRw:
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po_reg_or_fail (REG_TYPE_RN);
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@ -6436,6 +6439,13 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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}
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break;
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case OP_RRnpctw:
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if (inst.operands[i].isreg
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&& inst.operands[i].reg == REG_PC
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&& (inst.operands[i].writeback || thumb))
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inst.error = BAD_PC;
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break;
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case OP_CPSF:
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case OP_ENDI:
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case OP_oROR:
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@ -17426,22 +17436,22 @@ static const struct asm_opcode insns[] =
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/* Memory operations. */
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cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
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cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
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cCE("fldmias", c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
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cCE("fldmfds", c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
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cCE("fldmdbs", d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
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cCE("fldmeas", d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
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cCE("fldmiax", c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
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cCE("fldmfdx", c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
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cCE("fldmdbx", d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
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cCE("fldmeax", d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
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cCE("fstmias", c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
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cCE("fstmeas", c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
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cCE("fstmdbs", d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
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cCE("fstmfds", d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
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cCE("fstmiax", c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
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cCE("fstmeax", c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
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cCE("fstmdbx", d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
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cCE("fstmfdx", d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
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cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
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cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
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cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
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cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
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cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
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cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
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cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
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cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
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cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
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cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
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cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
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cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
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cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
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cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
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cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
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cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
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/* Monadic operations. */
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cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
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@ -17469,14 +17479,14 @@ static const struct asm_opcode insns[] =
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implementations. */
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cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
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cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
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cCE("fldmiad", c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
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cCE("fldmfdd", c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
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cCE("fldmdbd", d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
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cCE("fldmead", d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
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cCE("fstmiad", c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
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cCE("fstmead", c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
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cCE("fstmdbd", d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
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cCE("fstmfdd", d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
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cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
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cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
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cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
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cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
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cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
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cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
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cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
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cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
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@ -17556,12 +17566,12 @@ static const struct asm_opcode insns[] =
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NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
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NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
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NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
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NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
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NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm),
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NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
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NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
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NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm),
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NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
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NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
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NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
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NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
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NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
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NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
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NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
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NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
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@ -1,3 +1,14 @@
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2010-06-09 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/vldm-arm.d: New test.
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* gas/arm/vldm-thumb-bad.d: Likewise.
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* gas/arm/vldm-thumb-bad.l: Likewise.
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* gas/arm/vldm.s: Likewise.
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* gas/arm/vldmw-arm-bad.d: Likewise.
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* gas/arm/vldmw-bad.l: Likewise.
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* gad/arm-vldmw-bad.s: Likewise.
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* gas/arm/vldmw-thumb-bad.d: Likewise.
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2010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/thumb-eabi.d: Add case for divided syntax encoding of movs.
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* gas/arm/thumb.d: Likewise.
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22
gas/testsuite/gas/arm/vldm-arm.d
Normal file
22
gas/testsuite/gas/arm/vldm-arm.d
Normal file
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@ -0,0 +1,22 @@
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# name: VFP VLDM and VSTM, ARM mode
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# as: -mfpu=vfp3
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# source: vldm.s
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# objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> ec9f0b04 vldmia pc, {d0-d1}
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0[0-9a-f]+ <[^>]+> ea000003 b 00000018 <bar>
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0[0-9a-f]+ <[^>]+> 00000000 .word 0x00000000
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0[0-9a-f]+ <[^>]+> 3ff00000 .word 0x3ff00000
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0[0-9a-f]+ <[^>]+> 9999999a .word 0x9999999a
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0[0-9a-f]+ <[^>]+> 3ff19999 .word 0x3ff19999
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0[0-9a-f]+ <[^>]+> ec8f0b04 vstmia pc, {d0-d1}
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0[0-9a-f]+ <[^>]+> ea000003 b 00000030 <foo2>
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0[0-9a-f]+ <[^>]+> 00000000 .word 0x00000000
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0[0-9a-f]+ <[^>]+> 3ff00000 .word 0x3ff00000
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0[0-9a-f]+ <[^>]+> 9999999a .word 0x9999999a
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0[0-9a-f]+ <[^>]+> 3ff19999 .word 0x3ff19999
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0[0-9a-f]+ <[^>]+> e1a00000 nop.*
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0[0-9a-f]+ <[^>]+> e1a00000 nop.*
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4
gas/testsuite/gas/arm/vldm-thumb-bad.d
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4
gas/testsuite/gas/arm/vldm-thumb-bad.d
Normal file
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# name: VFP VLDM and VSTM, Thumb mode
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# as: -mfpu=vfp3 -mthumb
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# source: vldm.s
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# error-output: vldm-thumb-bad.l
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3
gas/testsuite/gas/arm/vldm-thumb-bad.l
Normal file
3
gas/testsuite/gas/arm/vldm-thumb-bad.l
Normal file
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@ -0,0 +1,3 @@
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[^:]*: Assembler messages:
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[^:]*:4: Error: r15 not allowed here -- `vldmia pc,{d0-d1}'
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[^:]*:9: Error: r15 not allowed here -- `vstmia pc,{d0-d1}'
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16
gas/testsuite/gas/arm/vldm.s
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16
gas/testsuite/gas/arm/vldm.s
Normal file
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@ -0,0 +1,16 @@
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.syntax unified
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foo:
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vldmia pc, {d0-d1}
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b bar
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baz:
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.word 0x00000000, 0x3ff00000, 0x9999999a, 0x3ff19999
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bar:
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vstmia pc, {d0-d1}
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b foo2
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baz2:
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.word 0x00000000, 0x3ff00000, 0x9999999a, 0x3ff19999
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foo2:
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nop
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nop
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4
gas/testsuite/gas/arm/vldmw-arm-bad.d
Normal file
4
gas/testsuite/gas/arm/vldmw-arm-bad.d
Normal file
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# name: VFP VLDM and VSTM with writeback, ARM mode
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# as: -mfpu=vfp3
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# source: vldmw-bad.s
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# error-output: vldmw-bad.l
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3
gas/testsuite/gas/arm/vldmw-bad.l
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3
gas/testsuite/gas/arm/vldmw-bad.l
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@ -0,0 +1,3 @@
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[^:]*: Assembler messages:
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[^:]*:4: Error: r15 not allowed here -- `vldmia pc!,{d0-d1}'
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[^:]*:9: Error: r15 not allowed here -- `vstmia pc!,{d0-d1}'
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16
gas/testsuite/gas/arm/vldmw-bad.s
Normal file
16
gas/testsuite/gas/arm/vldmw-bad.s
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@ -0,0 +1,16 @@
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.syntax unified
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foo:
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vldmia pc!, {d0-d1}
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b bar
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baz:
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.word 0x00000000, 0x3ff00000, 0x9999999a, 0x3ff19999
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bar:
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vstmia pc!, {d0-d1}
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b foo2
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baz2:
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.word 0x00000000, 0x3ff00000, 0x9999999a, 0x3ff19999
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foo2:
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nop
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nop
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4
gas/testsuite/gas/arm/vldmw-thumb-bad.d
Normal file
4
gas/testsuite/gas/arm/vldmw-thumb-bad.d
Normal file
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@ -0,0 +1,4 @@
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# name: VFP VLDM and VSTM with writeback, Thumb mode
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# as: -mfpu=vfp3 -mthumb
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# source: vldmw-bad.s
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# error-output: vldmw-bad.l
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Loading…
Reference in a new issue