* config/tc-arm.c (encode_thumb2_ldmstm): Make warning about
writeback when base register is in register list an error, and
correct check.
(do_t_ldmstm): Change warnings.
* gas/arm/thumb2_ldmstm.d: Add new testcases.
* gas/arm/thumb2_ldmstm.s: Likeiwse.
* gas/arm/thumb2_ldmstm_bad.d: Add testcases to check for
UNPREDICTABLE ldm/stm.
* gas/arm/thumb2_ldmstm_bad.l: Likewise.
* gas/arm/thumb2_ldmstm_bad.s: Likewise.
This commit is contained in:
Nick Clifton
parent
91a45c33cd
commit
1e5b037994
9 changed files with 130 additions and 12 deletions
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@ -1,3 +1,10 @@
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2010-05-27 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (encode_thumb2_ldmstm): Make warning about
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writeback when base register is in register list an error, and
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correct check.
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(do_t_ldmstm): Change warnings.
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2010-05-26 Catherine Moore <clm@codesourcery.com>
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* config/tc-mips.c (is_opcode_valid): Remove expansionp.
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@ -9760,6 +9760,12 @@ encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
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if (mask & (1 << 13))
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inst.error = _("SP not allowed in register list");
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if ((mask & (1 << base)) != 0
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&& writeback)
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inst.error = _("having the base register in the register list when "
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"using write back is UNPREDICTABLE");
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if (load)
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{
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if (mask & (1 << 15))
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@ -9769,19 +9775,11 @@ encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
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else
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set_it_insn_type_last ();
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}
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if ((mask & (1 << base)) != 0
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&& writeback)
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as_warn (_("base register should not be in register list "
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"when written back"));
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}
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else
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{
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if (mask & (1 << 15))
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inst.error = _("PC not allowed in register list");
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if (mask & (1 << base))
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as_warn (_("value stored for r%d is UNPREDICTABLE"), base);
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}
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if ((mask & (mask - 1)) == 0)
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@ -9847,7 +9845,7 @@ do_t_ldmstm (void)
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if (inst.instruction == T_MNEM_stmia
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&& (inst.operands[1].imm & mask)
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&& (inst.operands[1].imm & (mask - 1)))
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as_warn (_("value stored for r%d is UNPREDICTABLE"),
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as_warn (_("value stored for r%d is UNKNOWN"),
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inst.operands[0].reg);
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inst.instruction = THUMB_OP16 (inst.instruction);
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@ -9887,7 +9885,7 @@ do_t_ldmstm (void)
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as_warn (_("this instruction will write back the base register"));
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if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
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&& (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
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as_warn (_("value stored for r%d is UNPREDICTABLE"),
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as_warn (_("value stored for r%d is UNKNOWN"),
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inst.operands[0].reg);
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}
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else
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@ -1,3 +1,12 @@
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2010-05-27 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/thumb2_ldmstm.d: Add new testcases.
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* gas/arm/thumb2_ldmstm.s: Likeiwse.
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* gas/arm/thumb2_ldmstm_bad.d: Add testcases to check for
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UNPREDICTABLE ldm/stm.
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* gas/arm/thumb2_ldmstm_bad.l: Likewise.
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* gas/arm/thumb2_ldmstm_bad.s: Likewise.
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2010-05-26 Catherine Moore <clm@codesoucery.com>
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Maxim Kuvyrkov <maxim@codesourcery.com>
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@ -181,7 +181,7 @@
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[^:]*:124: Error: lo register required -- `stmia r8!,{r1,r2}'
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[^:]*:125: Error: lo register required -- `stmia r7!,{r8}'
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[^:]*:126: Warning: this instruction will write back the base register
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[^:]*:127: Warning: value stored for r7 is UNPREDICTABLE
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[^:]*:127: Warning: value stored for r7 is UNKNOWN
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[^:]*:129: Error: invalid register list to push/pop instruction -- `push {r8,r9}'
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[^:]*:130: Error: invalid register list to push/pop instruction -- `pop {r8,r9}'
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[^:]*:133: Error: immediate value out of range -- `bkpt #257'
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@ -1,6 +1,8 @@
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# name: Thumb-2 LDM/STM single reg
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# name: Thumb-2 LDM/STM
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# as: -march=armv6t2
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# objdump: -dr --prefix-addresses --show-raw-insn
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# not-target: *-*-*aout*
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.*: +file format .*arm.*
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@ -25,3 +27,27 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f846 cc04 str.w ip, \[r6, #-4\]
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0[0-9a-f]+ <[^>]+> f846 bd04 str.w fp, \[r6, #-4\]!
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0[0-9a-f]+ <[^>]+> f845 8d04 str.w r8, \[r5, #-4\]!
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0[0-9a-f]+ <[^>]+> c80e ldmia r0!, {r1, r2, r3}
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0[0-9a-f]+ <[^>]+> c80f ldmia r0, {r0, r1, r2, r3}
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0[0-9a-f]+ <[^>]+> c802 ldmia r0!, {r1}
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0[0-9a-f]+ <[^>]+> e890 0f00 ldmia.w r0, {r8, r9, sl, fp}
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0[0-9a-f]+ <[^>]+> e8b0 000e ldmia.w r0!, {r1, r2, r3}
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0[0-9a-f]+ <[^>]+> e8b0 0f00 ldmia.w r0!, {r8, r9, sl, fp}
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0[0-9a-f]+ <[^>]+> e8b0 5000 ldmia.w r0!, {ip, lr}
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0[0-9a-f]+ <[^>]+> e8b0 9000 ldmia.w r0!, {ip, pc}
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0[0-9a-f]+ <[^>]+> bf08 it eq
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0[0-9a-f]+ <[^>]+> e8b0 9000 ldmiaeq.w r0!, {ip, pc}
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0[0-9a-f]+ <[^>]+> c00f stmia r0!, {r0, r1, r2, r3}
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0[0-9a-f]+ <[^>]+> c0f0 stmia r0!, {r4, r5, r6, r7}
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0[0-9a-f]+ <[^>]+> e8a0 00f0 stmia.w r0!, {r4, r5, r6, r7}
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0[0-9a-f]+ <[^>]+> e8a0 0f00 stmia.w r0!, {r8, r9, sl, fp}
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0[0-9a-f]+ <[^>]+> e880 000f stmia.w r0, {r0, r1, r2, r3}
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0[0-9a-f]+ <[^>]+> e880 0f00 stmia.w r0, {r8, r9, sl, fp}
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0[0-9a-f]+ <[^>]+> f850 1b04 ldr.w r1, \[r0\], #4
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0[0-9a-f]+ <[^>]+> f8d0 1000 ldr.w r1, \[r0\]
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0[0-9a-f]+ <[^>]+> f858 9b04 ldr.w r9, \[r8\], #4
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0[0-9a-f]+ <[^>]+> f8d8 9000 ldr.w r9, \[r8\]
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0[0-9a-f]+ <[^>]+> f840 1b04 str.w r1, \[r0\], #4
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0[0-9a-f]+ <[^>]+> f8c0 1000 str.w r1, \[r0\]
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0[0-9a-f]+ <[^>]+> f848 9b04 str.w r9, \[r8\], #4
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0[0-9a-f]+ <[^>]+> f8c8 9000 str.w r9, \[r8\]
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@ -22,3 +22,36 @@ ldmstm:
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stmdb r6!, {fp}
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stmdb r5!, {r8}
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@ Valid Thumb-2 encodings of LDM/LDMIA/LDMFD as specified by section
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@ A8.6.53 of the ARM ARM
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ldmia r0!, {r1-r3} @ Encoding T1
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ldmia r0, {r0-r3} @ Encoding T1
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ldmia r0!, {r1} @ Encoding T1
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ldmia r0, {r8-r11} @ Encoding T2
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ldmia.w r0!, {r1-r3} @ Encoding T2
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ldmia r0!, {r8-r11} @ Encoding T2
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ldmia r0!, {r12, r14} @ Encoding T2
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ldmia r0!, {r12, pc} @ Encoding T2
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it eq
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ldmiaeq r0!, {r12, pc} @ Encoding T2
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@ Valid Thumb-2 encodings of STM/STMIA/STMEA as specified by section
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@ A8.6.189 of the ARMARM.
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stmia r0!, {r0-r3} @ Encoding T1, Allowed as r0 is lowest reg
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stmia r0!, {r4-r7} @ Encoding T1
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stmia.w r0!, {r4-r7} @ Encoding T2
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stmia r0!, {r8-r11} @ Encoding T2
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stmia r0, {r0-r3} @ Encoding T2
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stmia r0, {r8-r11} @ Encoding T2
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@ The following are technically UNPREDICTABLE if we assemble them
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@ as written, but gas translates (stm|ldm) rn(!), {rd} into an
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@ equivalent, and well-defined, (ldr, str) rd, [rn], (#4).
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ldmia.w r0!, {r1} @ ldr.w r1, [r0], #4
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ldmia.w r0, {r1} @ ldr.w r1, [r0]
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ldmia r8!, {r9} @ ldr.w r9, [r8], #4
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ldmia r8, {r9} @ ldr.w r9, [r8]
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stmia.w r0!, {r1} @ str.w r1, [r0], #4
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stmia r0, {r1} @ str.w r1, [r0]
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stmia r8!, {r9} @ str.w r9, [r8], #4
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stmia r8, {r9} @ str.w r9, [r8]
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3
gas/testsuite/gas/arm/thumb2_ldmstm_bad.d
Normal file
3
gas/testsuite/gas/arm/thumb2_ldmstm_bad.d
Normal file
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@ -0,0 +1,3 @@
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#name: Invalid Thumb-2 LDM/STM instructions
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#as: -march=armv6t2
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#error-output: thumb2_ldmstm_bad.l
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12
gas/testsuite/gas/arm/thumb2_ldmstm_bad.l
Normal file
12
gas/testsuite/gas/arm/thumb2_ldmstm_bad.l
Normal file
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@ -0,0 +1,12 @@
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[^:]*: Assembler messages:
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[^:]*:6: Error: r15 not allowed here -- `ldmia r15,{r0-r3}'
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[^:]*:7: Error: r15 not allowed here -- `ldmia r15!,{r0-r3}'
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[^:]*:8: Error: LR and PC should not both be in register list -- `ldmia r1,{r14,r15}'
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[^:]*:9: Error: having the base register in the register list when using write back is UNPREDICTABLE -- `ldmia r0!,{r0-r3}'
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[^:]*:12: Error: branch must be last instruction in IT block -- `ldmiaeq r0,{r12,r15}'
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[^:]*:13: Error: having the base register in the register list when using write back is UNPREDICTABLE -- `ldmiaeq r0!,{r0,r1}'
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[^:]*:17: Error: having the base register in the register list when using write back is UNPREDICTABLE -- `stmia.w r0!,{r0-r3}'
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[^:]*:18: Warning: value stored for r1 is UNKNOWN
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[^:]*:19: Error: r15 not allowed here -- `stmia r15!,{r0-r3}'
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[^:]*:20: Error: r15 not allowed here -- `stmia r15,{r0-r3}'
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[^:]*:21: Error: having the base register in the register list when using write back is UNPREDICTABLE -- `stmia r8!,{r0-r11}'
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30
gas/testsuite/gas/arm/thumb2_ldmstm_bad.s
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30
gas/testsuite/gas/arm/thumb2_ldmstm_bad.s
Normal file
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@ -0,0 +1,30 @@
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.syntax unified
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.thumb
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ldmstm_bad:
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@ UNPREDICTABLE Thumb-2 encodings of LDM/LDMIA/LDMFD as specified
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@ by section A8.6.53 of the ARMARM.
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ldmia r15, {r0-r3} @ Encoding T2, UNPREDICTABLE
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ldmia r15!, {r0-r3} @ Encoding T2, UNPREDICTABLE
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ldmia r1, {r14, r15} @ Encoding T2, UNPREDICTABLE
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ldmia r0!, {r0-r3} @ Encoding T2, UNPREDICTABLE
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itt eq
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ldmiaeq r0, {r12, r15} @ Encoding T2, UNPREDICTABLE
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ldmiaeq r0!, {r0, r1} @ Encoding T2, UNPREDICTABLE
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@ UNPREDICTABLE Thumb-2 encodings of STM/STMIA/STMEA as specified
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@ by section A8.6.189 of the ARMARM.
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stmia.w r0!, {r0-r3} @ Encoding T2, UNPREDICTABLE
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stmia r1!, {r0-r3} @ Encoding T1, r1 is UNKNOWN
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stmia r15!, {r0-r3} @ Encoding T2, UNPREDICTABLE
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stmia r15, {r0-r3} @ Encoding T2, UNPREDICTABLE
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stmia r8!, {r0-r11} @ Encoding T2, UNPREDICTABLE
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@ The following are technically UNDEFINED, but gas converts them to
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@ an equivalent, and well-defined instruction automatically.
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@stmia.w r0!, {r1} @ str.w r1, [r0], #4
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@stmia r8!, {r9} @ str.w r9, [r8], #4
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@stmia r8, {r9} @ str.w r9, [r8]
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@ldmia.w r0!, {r1} @ ldr.w r1, [r0], #4
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@ldmia r8!, {r9} @ ldr.w r9, [r8], #4
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@ldmia r8, {r9} @ ldr.w r9, [r8]
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